n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM PRELIMINARY Some of contents are subject to change without notice. DESCRIPTION The MH8S72BAFD is 8388608 - word x 72-bit Synchronous DRAM stacked structural module. This consist of nine industry standard 8M x 8 Synchronous DRAMs in TSOP. The mounting of TSOP on a card edge dual in-line package provides any application where high densities and large of quantities memory are required. This is a socket-type memory module ,suitable for easy interchange or addition of module. FEATURES CLK Access Time [component level] MH8S72BAFD-7 100MHz 6ns (CL = 2, 3) MH8S72BAFD-8 100MHz 6ns (CL = 3) APPLICATION Main memory unit for computers, Microcomputer memory. MIT-DS-0273-0.2 1pin 94pin 10pin 95pin 11pin 124pin 40pin 125pin 41pin 168pin 84pin Front side Utilizes industry standard 8M X 8 Synchronous DRAMs in TSOP package , industry standard Resister in TSSOP package Single 3.3V +/- 0.3V supply LVTTL Interface 4096 refresh cycles every 64ms Discrete IC and module design conform to PC/100 specification. (module Spec. Rev. 1.1 and SPD 1.2A) Back side Type name Max. Frequency 85pin 1/ Dec./1998 MITSUBISHI ELECTRIC 1 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. 1 VSS 43 VSS 2 DQ0 44 NC 3 DQ1 45 4 DQ2 46 5 DQ3 47 6 VDD 48 7 DQ4 8 DQ5 PIN NAME 85 VSS 127 VSS 86 DQ32 128 CKE0 /S2 87 DQ33 129 NC DQMB2 88 DQ34 130 DQMB6 DQMB3 89 DQ35 131 DQMB7 NC 90 VDD 132 49 VDD 91 DQ36 133 NC VDD 50 NC 92 DQ37 134 NC 9 DQ6 51 NC 93 DQ38 135 NC 10 DQ7 52 CB2 94 DQ39 136 CB6 11 DQ8 VSS 53 CB3 VSS 95 DQ40 137 54 96 VSS 138 CB7 VSS 13 DQ9 55 DQ16 97 DQ41 139 DQ48 14 DQ10 56 DQ17 98 DQ42 140 DQ49 15 DQ11 57 DQ18 99 DQ43 141 DQ50 16 DQ12 58 DQ19 100 DQ44 142 DQ51 17 DQ13 59 VDD 101 DQ45 143 VDD 18 VDD 60 DQ20 102 VDD 144 DQ52 19 DQ14 61 DQ46 145 NC DQ15 62 NC NC 103 20 104 DQ47 146 NC 21 CB0 63 CKE1 105 CB4 147 REGE 22 64 VSS 106 VSS 65 DQ21 107 CB5 VSS 148 23 CB1 VSS 149 DQ53 24 NC 66 DQ22 108 NC 150 DQ54 25 NC 67 NC 151 DQ55 68 110 VDD 152 VSS 27 VDD /WE DQ23 VSS 109 26 69 DQ24 111 /CAS 153 DQ56 28 DQMB0 70 DQ25 112 DQMB4 154 DQ57 29 DQMB1 71 DQ26 113 DQMB5 155 DQ58 30 /S0 72 DQ27 114 NC 156 DQ59 31 NC 73 VDD 115 /RAS 157 VDD 32 VSS 74 DQ28 116 VSS 158 DQ60 33 A0 75 DQ29 117 A1 159 DQ61 34 A2 76 DQ30 118 A3 160 DQ62 35 A4 77 DQ31 119 A5 161 DQ63 36 A6 78 VSS 120 A7 162 VSS 37 A8 79 A9 163 A10 80 CK2 NC 121 38 122 BA0 164 CK3 NC 39 BA1 VDD 81 WP 123 SA0 82 SDA 124 A11 VDD 165 40 166 SA1 41 42 VDD CK0 83 84 SCL VDD 125 126 CK1 NC 167 168 SA2 VDD 12 NC = No Connection MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 2 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM /RS0 RDQMB0 RDQMB1 RDQMB4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 D0 RDQMB5 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 D1 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D8 RDQMB6 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 D2 /RS2 RDQMB7 RDQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 D3 RDQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 D4 SERIAL PD SCL WP 47K A0 A1 A2 SDA /S0 , /S2 DQMB0 to DQMB7 BA0-BA1 A0-A11 /RAS /CAS CKE0 /WE 10K VDD MIT-DS-0273-0.2 CK2 REGE SA0 SA1 SA2 CK0,CK1,CK3 /RS0 , /RS2 RDQMB0 to RDQMB7 BA0-BAN:D0-D8 RBA0-RBA1 A0-A11:D0-D8 RA0-RA11 /RAS: D0-D8 R/RAS /CAS: D0-D8 R/CAS RCKE0 /WE:D0-D8 R/WE D0-D8(3EACH) VDD D0 to D8 VSS D0 to D8 1/ Dec./1998 MITSUBISHI ELECTRIC 3 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Serial Presence Detect Table Byte Function described SPD enrty data SPD DATA(hex) 0 Defines # bytes written into serial memory at module mfgr 128 80 1 Total # bytes of SPD memory device 256 Bytes 08 2 Fundamental memory type SDRAM 04 3 # Row Addresses on this assembly A0-A11 0C 4 # Column Addresses on this assembly A0-A8 09 5 # Module Banks on this assembly 1BANK 01 6 Data Width of this assembly... x72 48 7 ... Data Width continuation 0 00 8 Voltage interface standard of this assembly LVTTL 01 9 SDRAM Cycletime at Max. Supported CAS Latency (CL). -7 -8 10ns A0 -7 -8 6ns 60 ECC 02 Cycle time for CL=3 10 SDRAM Access from Clock tAC for CL=3 11 DIMM Configuration type (Non-parity,Parity,ECC) 12 Refresh Rate/Type self refresh(15.625uS) 80 13 SDRAM width,Primary DRAM x8 08 14 Error Checking SDRAM data width x8 08 15 Minimum Clock Delay,Back to Back Random Column Addresses 1 01 Burst Lengths Supported 1/2/4/8/FP 8F 16 17 # Banks on Each SDRAM device 4bank 18 CAS# Latency CL=2/3 06 19 CS# Latency 0 01 20 Write Latency 0 01 21 SDRAM Module Attributes 22 SDRAM Device Attributes:General 23 SDRAM Cycle time(2nd highest CAS latency) Cycle time for CL=2 24 SDRAM Access form Clock(2nd highest CAS latency) tAC for CL=2 25 SDRAM Cycle time(3rd highest CAS latency) Cycle time for CL= 26 SDRAM Access form Clock(3rd highest CAS latency) tAC for CL= MIT-DS-0273-0.2 04 Registered and Buffered 1B Precharge All,Auto precharge,sw/br 0E -7 10ns A0 -8 -7 13ns 6ns D0 60 -8 -7 7ns N/A 70 00 -8 N/A 00 -7 N/A 00 -8 N/A 00 1/ Dec./1998 MITSUBISHI ELECTRIC 4 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Serial Presence Detect Table 27 28 Precharge to Active Minimum Row Active to Row Active Min. 20ns 14 20ns 14 29 RAS to CAS Delay Min 20ns 14 30 Active to Precharge Min 50ns 32 31 Density of each bank on module 64MByte 10 32 Command and Address signal input setup time 2ns 20 33 Command and Address signal input hold time 1ns 10 34 Data signal input setup time 2ns 20 35 Data signal input hold time 1ns 10 36-61 Superset Information (may be used in future) option 00 rev 1.2A 12 SPD Revision 62 63 64-71 72 Checksum for bytes 0-62 Check sum for -7 Manufactures Jedec ID code per JEP-108E Manufacturing location Check sum for -8 32 72 MITSUBISHI 1CFFFFFFFFFFFFFF Miyoshi,Japan 01 Tajima,Japan 02 NC,USA 03 Germany 73-90 Manufactures Part Number 04 MH8S72BAFD-7 4D4838533634424146442D37202020202020 MH8S72BAFD-8 4D4838533634424146442D38202020202020 91-92 Revision Code PCB revision rrrr 93-94 Manufacturing date year/week code yyww serial number ssssssss option 00 -8 100MHz 64 -7 CK0,1,2,3,CL=2/3,AP FF -8 CK0,1,2,3,CL=3,AP FD 95-98 99-125 126 127 128+ Assembly Serial Number Manufacture Specific Data Intetl specification frequency Intel specification detail for 100MHz support open Unused storage locations MIT-DS-0273-0.2 00 1/ Dec./1998 MITSUBISHI ELECTRIC 5 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM PIN FUNCTION Input Master Clock:All other inputs are referenced to the rising edge of CK CKE0 Input Clock Enable:CKE controls internal clock.When CKE is low,internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE E becomes asynchronous input.Self refresh is maintained as long as CKE is low. /S0,2 Input Chip Select: When /S is high,any command means No Operation. /RAS,/CAS,/W Input Combination of /RAS,/CAS,/W defines basic commands. A0-11 Input A0-11 specify the Row/Column Address in conjunction with BA.The Row Address is specified by A0-11.The Column Address is specified by A0-9.A10 is also used to indicate precharge option.When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, both banks are precharged. BA0-1 Input Bank Address:BA0,1 is not simply BA.BA0,1 specifies the bank to which a command is applied.BA must be set with ACT,PRE,READ,WRITE commands CK0 DQ0-63 CB0-7 DQM0-7 Vdd,Vss REGE MIT-DS-0273-0.2 Data In and Data out are referenced to the rising edge of Input/Output CK Input Din Mask/Output Disable:When DQMB is high in burst write.Din for the current cycle is masked.When DQMB is high in burst read,Dout is disabled at the next but one cycle. Power Supply Power Supply for the memory mounted module. Output Register enable:When REGE is low,All control signals and address are buffered. (Buffer mode) When REGE is high,All control and address are latched. (Latch mode) 1/ Dec./1998 MITSUBISHI ELECTRIC 6 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM BASIC FUNCTIONS The MH8S72BAFD provides basic functions,bank(row)activate,burst read / write, bank(row)precharge,and auto / self refresh. Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and precharge option,respectively. To know the detailed definition of commands please see the command truth table. CK /S Chip Select : L=select, H=deselect /RAS Command /CAS Command /WE Command CKE Refresh Option @refresh command A10 Precharge Option @precharge or read/write command define basic commands Activate(ACT) [/RAS =L, /CAS = /WE =H] ACT command activates a row in an idle bank indicated by BA. Read(READ) [/RAS =H,/CAS =L, /WE =H] READ command starts burst read from the active bank indicated by BA.First output data appears after /CAS latency. When A10 =H at this command,the bank is deactivated after the burst read(auto-precharge,READA). Write(WRITE) [/RAS =H, /CAS = /WE =L] WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write(auto-precharge,WRITEA). Precharge(PRE) [/RAS =L, /CAS =H,/WE =L] PRE command deactivates the active bank indicated by BA. This command also terminates burst read / write operation. When A10 =H at this command, both banks are deactivated(precharge all, PREA). Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H] PEFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically. MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 7 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM COMMAND TRUTH TABLE COMMAND MNEMONIC CK n-1 CK n /S Deselect No Operation DESEL NOP H H X X H L X H Row Adress Entry & Bank Activate ACT H X L Single Bank Precharge Precharge All Bank PRE PREA H H X X Column Address Entry & Write WRITE H Column Address Entry & Write with AutoPrecharge WRITEA Column Address Entry & Read /RAS /CAS /WE BA A10 A0-9 X H X H X X X X X X L H H V V V L L L L H H L L V V L H X X X L LH H L V L V H X L H L L V H V READ H X L H L H V L V Column Address Entry & Read with Auto Precharge READA H X L H L H V H V Auto-Refresh Self-Refresh Entry Self-Refresh Exit REFA REFS REFSX Burst Terminate Mode Register Set TERM MRS H H L L H H H L H H X X L L H L L L HL L LX H H L L L X H H L H H X H L L X X X X X L X X X X X L X X X X X V*1 H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number NOTE: 1.A7-9 = 0, A0-6 = Mode Address MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 8 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM FUNCTION TRUTH TABLE Current State /S IDLE H L X H X H X H X X L H H L BA L H L X BA,CA,A10 L L H H BA,RA ACT L L H L BA,A10 PRE/PREA L L L H X L L L L H X X X X DESEL NOP L H H H X NOP NOP L H H L BA TBST NOP L H L H BA,CA,A10 L H L L BA,CA,A10 L L H H BA,RA ACT Bank Active/ILLEGAL*2 L L H L BA,A10 PRE/PREA Precharge/Precharge All L L L H X L L L L H X X X X DESEL NOP(Continue Burst to END) L H H H X NOP NOP(Continue Burst to END) L H H L BA TBST Terminate Burst ROW ACTIVE READ /RAS /CAS /WE Address Command DESEL NOP TBST Action NOP NOP ILLEGAL*2 READ/WRITE ILLEGAL*2 Op-Code, Mode-Add Mode-Add NOP*4 REFA Auto-Refresh*5 MRS Mode Register Set*5 READ/READA Op-Code, Bank Active,Latch RA Begin Read,Latch CA, Determine Auto-Precharge WRITE/ Begin Write,Latch CA, WRITEA Determine Auto-Precharge REFA ILLEGAL MRS ILLEGAL Terminate Burst,Latch CA, L H L H BA,CA,A10 READ/READA Begin New Read,Determine Auto-Precharge*3 Terminate Burst,Latch CA, L H L L BA,CA,A10 WRITE/WRITEA Begin Write,Determine AutoPrecharge*3 MIT-DS-0273-0.2 L L H H BA,RA ACT L L H L BA,A10 PRE/PREA L L L H X L L L L Op-Code, Mode-Add Bank Active/ILLEGAL*2 Terminate Burst,Precharge REFA ILLEGAL MRS ILLEGAL 1/ Dec./1998 MITSUBISHI ELECTRIC 9 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM FUNCTION TRUTH TABLE(continued) Current State WRITE READ with AUTO PRECHARGE WRITE with AUTO PRECHARGE MIT-DS-0273-0.2 /S H L L /RAS /CAS X X H H H H /WE Address X X H X L BA L H L H BA,CA,A10 L H L L BA,CA,A10 L L H H BA,RA L L L L H L L H L L L L BA,A10 X Op-Code, H L L L X H H H X H H L X H L H Mode-Add X X BA BA,CA,A10 L H L L BA,CA,A10 L L H H BA,RA L L L L H L L H L L L L H L L L X H H H X H H L X H L H BA,A10 X Op-Code, Mode-Add X X BA BA,CA,A10 L H L L BA,CA,A10 L L L L L L H H L H L H L L L L BA,RA BA,A10 X Op-Code, Mode-Add Command DESEL NOP TBST Action NOP(Continue Burst to END) NOP(Continue Burst to END) Terminate Burst Terminate Burst,Latch CA, READ/READA Begin Read,Determine AutoPrecharge*3 Terminate Burst,Latch CA, WRITE/ Begin Write,Determine AutoWRITEA Precharge*3 ACT Bank Active/ILLEGAL*2 PRE/PREA REFA MRS DESEL NOP TBST READ/READA WRITE/ WRITEA ACT PRE/PREA REFA MRS DESEL NOP TBST READ/READA WRITE/ WRITEA ACT PRE/PREA REFA MRS Terminate Burst,Precharge ILLEGAL ILLEGAL NOP(Continue Burst to END) NOP(Continue Burst to END) ILLEGAL ILLEGAL ILLEGAL Bank Active/ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP(Continue Burst to END) NOP(Continue Burst to END) ILLEGAL ILLEGAL ILLEGAL Bank Active/ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL 1/ Dec./1998 MITSUBISHI ELECTRIC 10 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM FUNCTION TRUTH TABLE(continued) Current State /S PRE - H X X X X DESEL NOP(Idle after tRP) CHARGING L H H H X NOP NOP(Idle after tRP) L H H L BA TBST ILLEGAL*2 L H L X BA,CA,A10 L L H H BA,RA ACT L L H L BA,A10 PRE/PREA L L L H X L L L L ROW H X X X X DESEL NOP(Row Active after tRCD ACTIVATING L H H H X NOP NOP(Row Active after tRCD L H H L BA TBST ILLEGAL*2 L H L X BA,CA,A10 L L H H BA,RA ACT ILLEGAL*2 L L H L BA,A10 PRE/PREA ILLEGAL*2 L L L H X L L L L WRITE RE- H X X X X DESEL NOP COVERING L H H H X NOP NOP L H H L BA TBST ILLEGAL*2 L H L X BA,CA,A10 L L H H BA,RA ACT ILLEGAL*2 L L H L BA,A10 PRE/PREA ILLEGAL*2 L L L H X L L L L MIT-DS-0273-0.2 /RAS /CAS /WE Address Command Action READ/WRITE ILLEGAL*2 Op-Code, Mode-Add ILLEGAL*2 NOP*4(Idle after tRP) REFA ILLEGAL MRS ILLEGAL READ/WRITE ILLEGAL*2 Op-Code, Mode-Add REFA ILLEGAL MRS ILLEGAL READ/WRITE ILLEGAL*2 Op-Code, Mode-Add REFA ILLEGAL MRS ILLEGAL 1/ Dec./1998 MITSUBISHI ELECTRIC 11 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM FUNCTION TRUTH TABLE(continued) Current State /S /RAS /CAS /WE Address Command Action RE- H X X X X DESEL NOP(Idle after tRC) FRESHING L H H H X NOP NOP(Idle after tRC) L H H L BA TBST ILLEGAL L H L X BA,CA,A10 L L H H BA,RA ACT ILLEGAL L L H L BA,A10 PRE/PREA ILLEGAL L L L H X REFA ILLEGAL L L L L MRS ILLEGAL MODE H X X X X DESEL NOP(Idle after tRSC) REGISTER L H H H X NOP NOP(Idle after tRSC) SETTING L H H L BA TBST ILLEGAL L H L X BA,CA,A10 L L H H BA,RA ACT ILLEGAL L L H L BA,A10 PRE/PREA ILLEGAL L L L H X REFA ILLEGAL L L L L MRS ILLEGAL READ/WRITE ILLEGAL Op-Code, Mode-Add READ/WRITE ILLEGAL Op-Code, Mode-Add ABBREVIATIONS: H = Hige Level, L = Low Level, X = Don't Care BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation NOTES: 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state.May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and / or date-integrity are not guaranteed. MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 12 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM FUNCTION TRUTH TABLE FOR CKE Current State CK n-1 CK n /S SELF - H X X X REFRESH*1 L H H L H L /RAS /CAS /WE Add Action X X X INVALID X X X X Exit Self-Refresh(Idle after tRC) L H H H X Exit Self-Refresh(Idle after tRC) H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP(Maintain Self-Refresh) POWER H X X X X X X INVALID DOWN L H X X X X X Exit Power Down to Idle L L X X X X X NOP(Maintain Self-Refresh) ALL BANKS H H X X X X X Refer to Function Truth Table IDLE*2 H L L L L H X Enter Self-Refresh H L H X X X X Enter Power Down H L L H H H X Enter Power Down H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L X X X ILLEGAL L X X X X X X Refer to Current State = Power Down ANY STATE H H X X X X X Refer to Function Truth Table other than H L X X X X X Begin CK0 Suspend at Next Cycle*3 listed above L H X X X X X Exit CK0 Suspend at Next Cycle*3 L L X X X X X Maintain CK0 Suspend ABBREVIATIONS: H = High Level, L = Low Level, X = Don't Care NOTES: 1. CKE Low to High transition will re-enable CK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only form the All banks idle State. 3. Must be legal command. MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 13 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM POWER ON SEQUENCE Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning. 1. Apply power and start clock. Attempt to maintain CKE high, DQMB high and NOP condition at the inputs. 2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 500µs. 3. Issue precharge commands for all banks. (PRE or PREA) 4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation. MODE REGISTER Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register(MRS). The mode register stores these date until the next MRS command, which may be issue when both banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command. CK /S BA0 BA1 A11 A10 A9 A8 A7 A6 0 0 A5 A4 A3 A2 A1 A0 /RAS /CAS 0 0 0 0 WM LTMODE BT BL /WE V BA0,1 A11-0 LATENCY MODE WRITE MODE CL 000 001 010 011 100 101 110 111 0 1 MIT-DS-0273-0.2 /CAS LATENCY R R 2 3 R R R R BURST SINGLE BIT BURST LENGTH BURST TYPE BL BT= 0 BT= 1 000 001 010 011 100 101 110 111 1 2 4 8 R R R FP 1 2 4 8 R R R R 0 1 SEQUENTIAL INTERLEAVED R:Reserved for Future Use FP: Full Page 1/ Dec./1998 MITSUBISHI ELECTRIC 14 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM CK Command Read Write Y Y Address Q0 DQ CL= 3 BL= 4 /CAS Latency Q1 Q2 Q3 D0 Burst Length D1 D2 D3 Burst Length Burst Type Initial Address BL Column Addressing A2 A1 A0 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 Sequential Interleaved 8 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 - 0 0 0 1 2 3 0 1 2 3 - 0 1 1 2 3 0 1 0 3 2 4 - 1 0 2 3 0 1 2 3 0 1 - 1 1 3 0 1 2 3 2 1 0 - - 0 0 1 0 1 1 0 1 0 2 - - 1 MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 15 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Parameter Condition Ratings Unit Vdd Supply Voltage with respect to Vss -0.5 ~ 4.6 V VI Input Voltage with respect to Vss -0.5 ~ 4.6 V VO Output Voltage with respect to Vss -0.5 ~ 4.6 V IO Output Current 50 mA Pd Power Dissipation 11 W Topr Operating Temperature 0 ~ 70 °C Tstg Storage Temperature -45 ~ 100 °C Ta=25°C RECOMMENDED OPERATING CONDITION (Ta=0 ~ 70°C, unless otherwise noted) Limits Parameter Symbol Min. Typ. Max. Unit Vdd Supply Voltage 3.0 3.3 3.6 V Vss Supply Voltage 0 0 0 V VIH High-Level Input Voltage all inputs 2.0 Vdd+0.3 V VIL Low-Level Input Voltage all inputs -0.3 0.8 V CAPACITANCE (Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted) Symbol Parameter Test Condition Limits(max.) Unit CI(A) Input Capacitance, address pin VI = Vss 20 pF CI(C) Input Capacitance, control pin 20 pF 38 pF 22 pF CI(K) Input Capacitance, CK pin CI/O MIT-DS-0273-0.2 Input Capacitance, I/O pin f=1MHz Vi=25mVrms 1/ Dec./1998 MITSUBISHI ELECTRIC 16 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM AVERAGE SUPPLY CURRENT from Vdd (Ta=0 ~70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted) Parameter Symbol Limits (max) Test Condition Unit -7, -8 operating current one bank active (discrete) precharge stanby current in power-down mode precharge stanby current in non power-down mode active stanby current in power-down mode active stanby current in non power-down mode Icc1 tRC=min.tCLK=min, BL=1, IOL=min Icc2P CKE=VILmax,tCLK=15ns Icc2PS CKE=CLK=VILmax(fixed) Icc2N CKE=/CS=VIHmin,tCLK=15ns(Note) Icc2NS CKE=VIHmin,CLK=VILmax(fixed) Icc3P CKE=VILmax,tCLK=15ns Icc3PS CKE=CLK=VILmax(fixed) mA 42 mA mA mA mA mA mA 33 222 204 60 42 burst current auto-refresh current Icc3N CKE=/CS=VIHmin,tCLK=15ns Icc3NS CKE=VIHmin,CLK=VILmax(fixed) Icc4 tCLK=min, BL=4, CL=3,IOL=0mAall banks active(discerte) tRC=min, tCLK=min Icc5 self-refresh current Icc6 one bank active (discrete) 1014 CKE <0.2V 519 384 1059 1374 mA mA 33 mA mA mA Note:Input signals are changed one time during 30ns. AC OPERATING CONDITIONS AND CHARACTERISTICS (Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted) Symbol VOH(DC) VOL(DC) VOH(AC IOZ )VOL(AC) Ii Parameter High-Level Output Voltage(DC) Low-Level Output Voltage(DC) High-Level Off-stare Output Output Current Voltage(AC) Input Current Low-Level Output Voltage(AC) MIT-DS-0273-0.2 Test Condition IOH=-2mA IOL=2mA CL=50pF, Q floating VO=0 ~ Vdd IOH=-2mA CL=50pF, VIH=0 ~ Vdd+0.3V IOL=2mA Limits Unit Min. Max. 2.4 V 0.4 V 2 V -5 5 uA V -10 0.8 10 uA 1/ Dec./1998 MITSUBISHI ELECTRIC 17 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM AC TIMING REQUIREMENTS (Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted) Input Pulse Levels: 0.8V to 2.0V Input Timing Measurement Level: 1.4V LATCH MODE Limits -7 Symbol Parameter Min. CL=3 CL=4 tCLK CK cycle time tCH tCL tT tIS tIH tRC tRCD tRAS tRP tWR tRRD tCCD tRSC tSRX tREF CK High pulse width CK Low pilse width Transition time of CK Input Setup time(all inputs) Input Hold time(all inputs) Row cycle time Row to Column Delay Row Active time Row Precharge time Write Recovery time Act to Act Deley time Col to Col Delay time Mode Register Set Cycle time Self Refresh Exit time Refresh Interval time Unit -8 Max. Min. 10 13 10 3 3 1 2 0 70 20 50 20 10 20 10 20 10 10 4 4 1 2 0 70 20 50 20 10 20 10 20 10 10 100000 64 Max. 10 100000 64 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms Note:1 The timing requirements are assumed tT=1ns. If tT is longer than 1ns, (tT-1)ns should be added to the parameter. CK 1.4V Signal 1.4V MIT-DS-0273-0.2 Any AC timing is referenced to the input signal crossing through 1.4V. 1/ Dec./1998 MITSUBISHI ELECTRIC 18 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM BUFFER MODE Limits -7 Symbol Parameter Min. CL=2 CL=3 tCLK CK cycle time tCH tCL tT tIS tIH tRC tRCD tRAS tRP tWR tRRD tCCD tRSC tSRX tREF CK High pulse width CK Low pilse width Transition time of CK Input Setup time(all inputs) Input Hold time(all inputs) Row cycle time Row to Column Delay Row Active time Row Precharge time Write Recovery time Act to Act Deley time Col to Col Delay time Mode Register Set Cycle time Self Refresh Exit time Refresh Interval time Unit -8 Max. Min. 10 13 10 3 3 1 8 0 70 20 50 20 10 20 10 20 10 10 4 4 1 8 0 70 20 50 20 10 20 10 20 10 10 100000 Max. 10 100000 64 64 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms Note:1 The timing requirements are assumed tT=1ns. If tT is longer than 1ns, (tT-1)ns should be added to the parameter. SWITCHING CHARACTERISTICS (Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted) LATCH MODE Limits -7 Symbol Parameter Min. tAC tOH tOLZ tOHZ Access time from CK Output Hold time from CK Delay time, output low impedance from CK Delay time, output high impedance from CK MIT-DS-0273-0.2 CL=3 CL=4 -8 Max. Min. Unit Max. 6 7 6 6 ns 3 3 ns 0 0 ns 3 6 3 6 ns 1/ Dec./1998 MITSUBISHI ELECTRIC 19 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM BUFFER MODE Limits -7 Symbol Parameter Min. tAC tOH tOLZ tOHZ Access time from CK CL=2 CL=3 Output Hold time from CK Delay time, output low impedance from CK Delay time, output high impedance from CK -8 Max. Min. Unit Max. 6 7 6 6 ns 3 3 ns 0 0 ns 3 6 3 6 ns Output Load Condition VTT=1.4V CK 1.4V 50Ω DQ 1.4V VOUT 50pF Output Timing Measurement Reference Point CK 1.4V DQ 1.4V tAC MIT-DS-0273-0.2 tOH tOHZ 1/ Dec./1998 MITSUBISHI ELECTRIC 20 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM WRITE CYCLE (single bank) 0 1 2 3 4 5 6 7 BL=4,Buffer mode(REGE="L") 8 9 10 11 12 13 14 15 16 17 CLK tRC /CS tRAS tRP /RAS tRCD tRCD /CAS /WE tWR CKE DQM A0-9 X A10 X X A11 X X BA0,1 0 Y X 0 0 0 Y 0 REGE D0 DQ ACT#0 D0 WRITE#0 D0 D0 D0 PRE#0 ACT#0 D0 D0 D0 WRITE#0 Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 21 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM WRITE CYCLE (dual bank) 0 1 2 3 4 5 6 7 BL=4,Buffer mode(REGE="L") 8 9 10 11 12 13 14 15 16 17 CLK tRC /CS tRRD tRRD tRAS tRP /RAS tRCD tRCD /CAS /WE tWR tWR CKE DQM A0-9 X X A10 X A11 BA0,1 Y Y X X X X X X X X X 0 1 0 1 0 D1 D1 0 1 2 Y 0 REGE D0 DQ ACT#0 D0 WRITE#0 ACT#1 D0 D0 D1 D1 PRE#0 WRITE#1 D0 ACT#0 D0 D0 D0 ACT#2 WRITE#0 PRE#1 Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 22 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM WRITE CYCLE (single bank) 0 1 2 3 4 5 6 7 BL=4,Lacth mode(REGE="H") 8 9 10 11 12 13 14 15 16 17 CLK tRC /CS tRAS tRP /RAS tRCD tRCD /CAS /WE tWR CKE DQM A0-9 X A10 X X A11 X X BA0,1 0 Y X 0 0 0 Y 0 REGE D0 DQ ACT#0 WRITE#0 D0 D0 D0 PRE#0 D0 ACT#0 D0 D0 D0 WRITE#0 Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 23 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM WRITE CYCLE (dual bank) 0 1 2 3 4 5 6 7 BL=4,Latch mode(REGE="H") 8 9 10 11 12 13 14 15 16 17 CLK tRC /CS tRRD tRRD tRAS tRP /RAS tRCD tRCD /CAS /WE tWR tWR CKE DQM A0-9 X X A10 X A11 BA0,1 Y Y X X X X X X X X X 0 1 0 1 0 0 D0 D1 1 2 Y 0 REGE D0 DQ ACT#0 WRITE#0 ACT#1 D0 D0 D1 PRE#0 WRITE#1 D1 D1 ACT#0 D0 D0 D0 ACT#2 WRITE#0 PRE#1 Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 24 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM READ CYCLE (single bank) 0 1 2 3 4 5 6 7 BL=4,CL=3,Buffer mode(REGE="L") 8 9 10 11 12 13 14 15 16 17 CLK tRC /CS tRAS tRP /RAS tRCD tRCD /CAS /WE CKE DQM DQM read latency =2 A0-9 X A10 X X A11 X X BA0,1 0 Y X 0 0 0 Y 0 REGE CL=3 Q0 DQ ACT#0 READ#0 Q0 Q0 PRE#0 Q0 Q0 ACT#0 Q0 READ#0 READ to PRE ≥BL allows full data out Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 25 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM READ CYCLE (dual bank) 0 1 2 3 4 5 6 7 BL=4,CL=3,Buffer mode(REGE="L") 8 9 10 11 12 13 14 15 16 17 CLK tRC /CS tRRD tRRD tRAS tRP /RAS tRCD tRCD /CAS /WE CKE DQM DQM read latency =2 A0-9 X X A10 X A11 BA0,1 Y Y X X X X X X X X X 0 1 0 1 0 0 1 2 Q1 Q1 Q1 Y 0 REGE CL=3 CL=3 Q0 DQ ACT#0 READ#0 ACT#1 Q0 Q0 Q0 PRE#0 READ#1 Q1 ACT#0 PRE#1 Q0 READ#0 ACT#2 Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 26 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM READ CYCLE (single bank) 0 1 2 3 4 5 6 7 BL=4, CL=3,Latch mode(REGE="H") 8 9 10 11 12 13 14 15 16 17 CLK tRC /CS tRAS tRP /RAS tRCD tRCD /CAS /WE CKE DQM DQM read latency =3 A0-9 X A10 X X A11 X X BA0,1 0 Y X 0 0 0 Y 0 REGE CL=3 Q0 DQ ACT#0 READ#0 Q0 Q0 PRE#0 Q0 Q0 ACT#0 Q0 READ#0 READ to PRE ≥BL allows full data out Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 27 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM READ CYCLE (dual bank) 0 1 2 3 4 5 6 7 BL=4,CL=3,Latch mode(REGE="H") 8 9 10 11 12 13 14 15 16 17 CLK tRC /CS tRRD tRRD tRAS tRP /RAS tRCD tRCD /CAS /WE CKE DQM DQM read latency =3 A0-9 X X A10 X A11 BA0,1 Y Y X X X X X X X X X 0 1 0 1 0 0 1 2 Q1 Q1 Q1 Y 0 REGE CL=3 CL=3 Q0 DQ ACT#0 READ#0 ACT#1 Q0 Q0 Q0 PRE#0 READ#1 Q1 ACT#0 PRE#1 Q0 READ#0 ACT#2 Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 28 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Burst WRITE (multi bank) with AUTO-PRECHARGE BL=4,Buffer mode(REGE="L") 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK tRC /CS tRRD tRRD /RAS tRCD tRCD tRCD /CAS BL-1+ tWR + tRP BL-1+ tWR + tRP /WE CKE DQM A0-9 X X A10 X X X X A11 X X X X BA0,1 0 1 Y Y 0 X 1 Y X 0 0 1 D1 D0 D0 Y 1 REGE D0 DQ ACT#0 ACT#1 D0 D0 WRITE#0 with AutoPrecharge D0 D1 D1 D1 ACT#0 WRITE#1 with AutoPrecharge D0 WRITE#0 ACT#1 D0 D1 WRITE#1 Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 29 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Burst WRITE (multi bank) with AUTO-PRECHARGE BL=4,Latch mode(REGE="H") 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK tRC /CS tRRD tRRD /RAS tRCD tRCD tRCD /CAS BL-1+ tWR + tRP BL-1+ tWR + tRP /WE CKE DQM A0-9 X X A10 X X X X A11 X X X X BA0,1 0 1 Y Y 0 X 1 Y 0 0 X Y 1 1 REGE D0 DQ ACT#0 ACT#1 D0 WRITE#0 with AutoPrecharge D0 D0 D1 D1 D1 ACT#0 WRITE#1 with AutoPrecharge D1 D0 D0 WRITE#0 ACT#1 D0 D0 WRITE#1 Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 30 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Burst READ (multi bank) with AUTO-PRECHARGE 0 1 2 3 4 5 6 7 8 9 BL=4,Buffer mode(REGE="L") 10 11 12 13 14 15 16 17 CLK tRC /CS tRRD tRRD /RAS tRCD tRCD tRCD /CAS BL+tRP BL+tRP /WE CKE DQM DQM read latency =2 A0-9 X X A10 X X X X A11 X X X X BA0,1 0 1 Y Y 0 X 1 Y 0 0 X Y 1 1 REGE CL=3 CL=3 Q0 DQ ACT#0 ACT#1 READ#0 with Auto-Precharge Q0 Q0 CL=3 Q0 Q1 Q1 ACT#0 READ#1 with Auto-Precharge Q1 Q1 Q0 Q0 READ#0 ACT#1 Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 31 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Burst READ (multi bank) with AUTO-PRECHARGE 0 1 2 3 4 5 6 7 8 9 BL=4,Latch mode(REGE="H") 10 11 12 13 14 15 16 17 CLK tRC /CS tRRD tRRD /RAS tRCD tRCD tRCD /CAS BL+tRP BL+tRP /WE CKE DQM DQM read latency =3 A0-9 X X A10 X X X X A11 X X X X BA0,1 0 1 Y Y 0 X 1 Y 0 0 X Y 1 1 REGE CL=3 CL=3 Q0 DQ ACT#0 ACT#1 READ#0 with Auto-Precharge Q0 Q0 CL=3 Q0 Q1 Q1 ACT#0 READ#1 with Auto-Precharge Q1 Q1 Q0 Q0 READ#0 ACT#1 Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 32 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Page Mode Burst Write (multi bank) 0 1 2 3 4 5 6 7 8 9 BL=4,Buffer mode(REGE="L") 10 11 12 13 14 15 16 17 CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A0-9 X X A10 X X A11 X X BA0,1 0 1 Y Y Y Y 0 0 1 0 REGE D0 DQ ACT#0 D0 WRITE#0 ACT#1 D0 D0 D0 D0 D0 D0 D1 D1 WRITE#0 D1 D1 D0 D0 D0 WRITE#0 WRITE#1 Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 33 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Page Mode Burst Write (multi bank) 0 1 2 3 4 5 6 7 8 9 BL=4,Latch mode(REGE="H") 10 11 12 13 14 15 16 17 CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A0-9 X X A10 X X A11 X X BA0,1 0 1 Y Y Y Y 0 0 1 0 REGE D0 DQ ACT#0 WRITE#0 ACT#1 D0 D0 D0 D0 D0 D0 D0 D1 WRITE#0 D1 D1 D1 D0 D0 WRITE#0 WRITE#1 Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 34 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Page Mode Burst Read (multi bank) 0 1 2 3 4 5 6 7 8 9 BL=4,Buffer mode(REGE="L") 10 11 12 13 14 15 16 17 CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM DQM read latency=2 A0-9 X X A10 X X A11 X X BA0,1 0 1 Y Y Y Y 0 0 1 0 REGE CL=3 CL=3 Q0 DQ ACT#0 READ#0 ACT#1 Q0 Q0 Q0 CL=3 Q0 Q0 Q0 READ#0 Q0 Q1 Q1 Q1 Q1 READ#0 READ#1 Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 35 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Page Mode Burst Read (multi bank) 0 1 2 3 4 5 6 7 8 9 BL=4,Latch mode(REGE="H") 10 11 12 13 14 15 16 17 CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM DQM read latency=3 A0-9 X X A10 X X A11 X X BA0,1 0 1 Y Y Y Y 0 0 1 0 REGE CL=3 CL=3 Q0 DQ ACT#0 READ#0 ACT#1 Q0 Q0 Q0 CL=3 Q0 Q0 Q0 READ#0 Q0 Q1 Q1 Q1 Q1 READ#0 READ#1 Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 36 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Write Interrupted by Write / Read 0 1 2 3 4 5 6 7 8 BL=4,Buffer mode(REGE="L") 9 10 11 12 13 14 15 16 17 CLK /CS tRRD /RAS tRCD tCCD /CAS /WE CKE DQM A0-9 X X A10 X X A11 X X BA0,1 0 1 Y Y Y Y Y 0 0 0 1 0 REGE CL=3 D0 DQ D0 D0 D0 D0 D0 D1 D1 Q0 Q0 Q0 Q0 ACT#0 WRITE#0 WRITE#0 WRITE#0 READ#0 ACT#1 WRITE#1 Burst Write can be interrupted by Write or Read of any active bank. Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 37 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Write Interrupted by Write / Read 0 1 2 3 4 5 6 7 8 BL=4,Latch mode(REGE="H") 9 10 11 12 13 14 15 16 17 CLK /CS tRRD /RAS tRCD tCCD /CAS /WE CKE DQM A0-9 X X A10 X X A11 X X BA0,1 0 1 Y Y Y Y Y 0 0 0 1 0 REGE CL=3 D0 DQ D0 D0 D0 D0 D0 D1 D1 Q0 Q0 Q0 Q0 ACT#0 WRITE#0 WRITE#0 WRITE#0 READ#0 ACT#1 WRITE#1 Burst Write can be interrupted by Write or Read of any active bank. Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 38 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Read Interrupted by Read / Write 0 1 2 3 4 5 6 7 8 BL=4,Buffer mode(REGE="L") 9 10 11 12 13 14 15 16 17 CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM DQM read latency=2 A0-9 X X A10 X X A11 X X BA0,1 0 1 DQ Y Y Y Y Y Y 0 0 0 1 0 0 Q0 Q0 Q0 Q0 Q0 Q0 Q1 Q1 Q0 D0 D0 REGE ACT#0 READ#0 READ#0 READ#0 READ#0 WRITE#0 ACT#1 READ#1 blank to prevent bus contention Burst Read can be interrupted by Read or Write of any active bank. Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 39 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Read Interrupted by Read / Write 0 1 2 3 4 5 6 7 8 BL=4,Latch mode(REGE="H") 9 10 11 12 13 14 15 16 17 CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM DQM read latency=3 A0-9 X X A10 X X A11 X X BA0,1 0 1 DQ Y Y Y Y Y Y 0 0 0 1 0 0 Q0 Q0 Q0 Q0 Q0 Q0 Q1 Q1 Q0 D0 REGE ACT#0 READ#0 READ#0 READ#0 READ#0 WRITE#0 ACT#1 READ#1 blank to prevent bus contention Burst Read can be interrupted by Read or Write of any active bank. Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 40 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Write Interrupted by Precharge 0 1 2 3 4 5 6 7 8 BL=4,Buffer mode(REGE="L") 9 10 11 12 13 14 15 16 17 CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A0-9 X X A10 X X X A11 X X X BA0,1 0 1 Y 0 D0 DQ Y D0 D0 D0 X 1 0 D1 D1 1 1 Y 1 D1 D1 D1 REGE ACT#0 WRITE#0 ACT#1 PRE#0 WRITE#1 PRE#1 Burst Write is not interrupted by Precharge of the other bank. ACT#1 WRITE#1 Burst Write is interrupted by Precharge of the same bank. Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 41 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Write Interrupted by Precharge 0 1 2 3 4 5 6 7 8 BL=4,Latch mode(REGE="H") 9 10 11 12 13 14 15 16 17 CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A0-9 X X A10 X X X A11 X X X BA0,1 0 1 Y Y 0 D0 DQ D0 D0 X 1 0 1 D0 D1 D1 1 Y 1 D1 D1 D1 REGE ACT#0 WRITE#0 ACT#1 PRE#0 WRITE#1 PRE#1 Burst Write is not interrupted by Precharge of the other bank. ACT#1 WRITE#1 Burst Write is interrupted by Precharge of the same bank. Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 42 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Read Interrupted by Precharge 0 1 2 3 4 5 6 7 8 BL=4,Buffer mode(REGE="L") 9 10 11 12 13 14 15 16 17 CLK /CS tRRD tRP /RAS tRCD tRCD /CAS /WE CKE DQM DQM read latency=2 A0-9 X X A10 X X X A11 X X X BA0,1 0 1 Y Y 0 Q0 DQ X 1 0 1 Q0 Q0 Q0 1 Q1 Y 1 Q1 REGE ACT#0 READ#0 ACT#1 PRE#0 READ#1 PRE#1 Burst Read is not interrupted by Precharge of the other bank. ACT#1 READ#1 Burst Read is interrupted by Precharge of the same bank. Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 43 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Read Interrupted by Precharge 0 1 2 3 4 5 6 7 8 BL=4,Latch mode(REGE="H") 9 10 11 12 13 14 15 16 17 CLK /CS tRRD tRP /RAS tRCD tRCD /CAS /WE CKE DQM DQM read latency=3 A0-9 X X A10 X X X A11 X X X BA0,1 0 1 Y Y 0 Q0 DQ X 1 0 1 Q0 Q0 Q0 1 Q1 Y 1 Q1 REGE ACT#0 READ#0 ACT#1 PRE#0 READ#1 PRE#1 Burst Read is not interrupted by Precharge of the other bank. ACT#1 READ#1 Burst Read is interrupted by Precharge of the same bank. Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 44 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Mode Register Setting 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS tRSC tRC /RAS tRCD /CAS /WE CKE DQM A0-9 M X A10 X A11 X BA0,1 0 0 Y 0 D0 DQ D0 D0 D0 REGE Auto-Ref (last of 8 cycles) Mode Register Setting ACT#0 WRITE#0 Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 45 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Auto-Refresh @BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS tRC /RAS tRCD /CAS /WE CKE DQM A0-9 X A10 X A11 X BA0,1 0 Y 0 D0 DQ D0 D0 D0 REGE Auto-Refresh ACT#0 WRITE#0 Before Auto-Refresh, all banks must be idle state. After tRC from Auto-Refresh, all banks are idle state. Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 46 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Self-Refresh 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK CLK can be stopped tRC /CS /RAS /CAS /WE tSRX CKE CKE must be low to maintain Self-Refresh DQM A0-9 X A10 X A11 X BA0,1 0 DQ REGE Self-Refresh Entry Before Self-Refresh Entry, all banks must be idle state. Self-Refresh Exit ACT#0 After tRC from Self-Refresh Exit, all banks are idle state. Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 47 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM DQM Write Mask @BL=4 0 1 2 3 4 5 6 BL=4,Buffer mode(REGE="L") 7 8 9 10 11 12 13 14 15 16 17 CLK /CS /RAS tRCD /CAS /WE CKE DQM A0-9 X A10 X A11 X BA0,1 0 Y Y Y 0 0 0 masked D0 DQ D0 D0 D0 masked D0 D0 D0 REGE ACT#0 WRITE#0 WRITE#0 WRITE#0 Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 48 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM DQM Write Mask @BL=4 0 1 2 3 4 5 6 BL=4,Latch mode(REGE="H") 7 8 9 10 11 12 13 14 15 16 17 CLK /CS /RAS tRCD /CAS /WE CKE DQM A0-9 X A10 X A11 X BA0,1 0 Y Y Y 0 0 0 masked D0 DQ D0 D0 D0 masked D0 D0 D0 REGE ACT#0 WRITE#0 WRITE#0 WRITE#0 Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 49 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM DQM Read Mask @BL=4 CL=3 0 1 2 3 4 5 6 7 BL=4,Buffer mode(REGE="L") 8 9 10 11 12 13 14 15 16 17 CLK /CS /RAS tRCD /CAS /WE CKE DQM read latency=2 DQM A0-9 X A10 X A11 X BA0,1 0 Y Y Y 0 0 0 masked Q0 DQ Q0 Q0 Q0 masked Q0 Q0 Q0 REGE ACT#0 READ#0 READ#0 READ#0 Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 50 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM DQM Read Mask @BL=4 CL=3 0 1 2 3 4 5 6 7 BL=4,Latch mode(REGE="H") 8 9 10 11 12 13 14 15 16 17 CLK /CS /RAS tRCD /CAS /WE CKE DQM read latency=3 DQM A0-9 X A10 X A11 X BA0,1 0 Y Y Y 0 0 0 masked Q0 DQ Q0 Q0 Q0 masked Q0 Q0 Q0 REGE ACT#0 READ#0 READ#0 READ#0 Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 51 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Power Down 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS /RAS /CAS /WE Standby Power Down Active Power Down CKE CKE latency=1 DQM A0-9 X A10 X A11 X BA0,1 0 DQ REGE Precharge All ACT#0 Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 52 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM CLK Suspend @BL=4 CL=3 0 1 2 3 4 5 6 BL=4,Buffer mode(REGE="L") 7 8 9 10 11 12 13 14 15 16 17 CLK /CS /RAS tRCD /CAS /WE CKE CKE latency=1 CKE latency=1 DQM A0-9 X A10 X A11 X BA0,1 0 Y Y 0 0 D0 DQ D0 D0 D0 Q0 Q0 Q0 Q0 REGE ACT#0 WRITE#0 READ#0 CLK suspended CLK suspended Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 53 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM CLK Suspend @BL=4 CL=3 0 1 2 3 4 5 6 BL=4,Latch mode(REGE="H") 7 8 9 10 11 12 13 14 15 16 17 CLK /CS /RAS tRCD /CAS /WE CKE CKE latency=2 CKE latency=2 DQM A0-9 X A10 X A11 X BA0,1 0 Y Y 0 0 D0 DQ D0 D0 D0 Q0 Q0 Q0 Q0 REGE ACT#0 WRITE#0 READ#0 CLK suspended CLK suspended Italic parameter indicates minimum case MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 54 n mi i l Pre ec. Sp MITSUBISHI LSIs ary MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM 133.35 8.89 6.35 11.43 1.27 6.35 36.83 24.495 3 17.78 3 4 3 54.61 42.18 127.35 38.1 4.18Min 4.008Min 3.9Max 1.27 MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 55 n mi i l Pre ec. Sp ary MITSUBISHI LSIs MH8S72BAFD -7, -8 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable,but there is always the possibility that trouble may occur with them. Trouble with semiconductors consideration to safety when making your circuit designs,with appropriate measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1.These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application;they do not convey any license under any intellectual property rights,or any other rights,belonging to Mitsubishi Electric Corporation or a third party. 2.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights,originating in the use of any product data,diagrams,charts or circuit application examples contained in these materials. 3.All information contained in these materials,including product data, diagrams and charts,represent information on products at the time of publication of these materials,and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. 4.Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for special applications,such as apparatus or systems for transportation, vehicular,medical,aerospace,nuclear,or undersea repeater use. 5.The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. 6.If these products or technologies are subject the Japanese export control restrictions,they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 7.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. MIT-DS-0273-0.2 1/ Dec./1998 MITSUBISHI ELECTRIC 56