Order this document by MC145003/D SEMICONDUCTOR TECHNICAL DATA Product Preview CMOS 1 ORDERING INFORMATION MC145003FU MC145004FU QFP QFP PIN ASSIGNMENT FP32 FP31 FP30 FP29 FP28 FP27 FP26 FP25 FP24 FP23 FP22 FP21 FP20 52 51 50 49 48 47 46 45 44 43 42 41 40 1 39 2 38 3 37 4 36 5 35 6 34 7 33 8 32 9 31 10 30 11 29 12 28 13 27 14 15 16 17 18 19 20 21 22 23 24 25 26 NC FP19 FP18 FP17 FP16 FP15 V LCD VSS FP14 FP13 FP12 FP11 NC • Drives 128 Segments Per Package • Devices May Be Cascaded for Larger LCD Applications • May Be Used with the Following LCDs: Segmented Alphanumeric, Bar Graph, Dot Matrix, Custom • Quiscent Supply Current: 85 µA @ 2.8 V VDD • Operating Voltage Range: 2.8 to 5.5 V • Operating Temperature Range: – 40 to 85°C • Separate Access to LCD Drive Section’s Supply Voltage to Allow for Temperature Compensation • See Application Notes AN1066 and AN442 52 QFP FU SUFFIX CASE 848B NC OSC1 OSC2 V DD BP1 BP2 BP3 BP4 A0 A1 A2 ENB NC The MC145003/5004 are 128–segment, multiplexed–by–four LCD Drivers. The two devices are functionally the same except for their data input protocols. The MC145003 uses an SPI data input protocol which is directly compatible with that of the MC6805 family of microcomputers. Using a minimal amount of software (see example), the device may be interfaced to the MC68HCXX product families. The MC145004 has a IIC interface and has essentially the same protocol, except that the device sends an acknowledge bit back to the transmitter after each eight–bit byte is received. MC145004 also has a “read mode”, whereby data sent to the device may be retrieved via the IIC bus. The MC145003/MC145004 drives the liquid–crystal displays in a multiplexed–by–four configuration. The device accepts data from a microprocessor or other serial data source to drive one segment per bit. The chip does not have a decoder, allowing for the flexibility of formatting the segment data externally. Devices are independently addressable via a two–wire (or three–wire) communication link which can be common with other MC145003/MC145004 and/or other peripheral devices. BLOCK DIAGRAM VLCD OSC1 OSC2 BP1–BP4 OSCILLATOR DRIVERS FS FRAME SYNC GENERATOR A0 A1 A2 ENB DATA AND ADDRESS CONTROL AND TIMING POR DCLK Din NC = NO CONNECTION FP1–FP32 LCD VOLTAGE WAVEFORM AND TIMING GENERATOR DRIVERS 128 – 32 MULTIPLEX 128–BIT LATCH 128–BIT SHIFT REGISTER This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice. Motorola, Inc. 1994 REV 1 12/94 Din DCLK FS FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 FP9 FP10 ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS) Parameter Symbol VDD Vin Vin osc Iin Tstg Value Unit – 0.5 to + 6.5 V – 0.5 to 15 V – 0.5 to VDD + 0.5 V ± 10 mA – 65 to + 150 °C DC Supply Voltage Input Voltage, Din, and Data Clock Input Voltage, OSCin of Master DC Input Current, per Pin Storage Temperature Range This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Descriptions section. ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) – 40°C 25°C 85°C S b l Symbol VDD V VLCD V Min Max Min Max Min Max VO = 0.15 V IFH IFL 5 5 2.8 2.8 360 360 — — 260 260 — — 240 240 — — VO = 2.65 V IFH IFL 5 5 2.8 2.8 – 320 – 320 — — – 240 – 240 — — – 240 – 240 — — VO = 1.72 V IFH IFL 5 5 2.8 2.8 – 95 — — – 1.5 – 40 — — – 1.5 – 60 — — –1 VO = 1.08 V IFH IFL 5 5 2.8 2.8 90 — — 2 40 — — 2 55 — — 1 VO = 0.15 V IFH IFL 5 5 5.5 5.5 600 600 — — 600 600 — — 580 580 — — VO = 5.35 V IFH IFL 5 5 5.5 5.5 – 490 – 490 — — – 520 – 520 — — – 520 – 520 — — VO = 3.52 V IFH IFL 5 5 5.5 5.5 – 100 — — – 1.5 – 35 — — – 1.5 – 50 — — –1 VO = 1.98 V IFH IFL 5 5 5.5 5.5 100 — — 1.5 55 — — 1 70 — — 1 IDDQ ILCDQ IDDQ ILCDQ 2.8 — 5.5 — — 2.8 — 5.5 — — — — 65 30 350 60 — — — — 140 45 1050 90 — — — — 85 20 350 35 Input Current Iin — — — — – 0.1 0.1 — — µA Input Capacitance Cin — — — — — 7.5 — — pF fOSC2 fFS fFS fBP fOSC2 5 5 5 5 5 5 5 5 5 5 103 100 4.7 100 22.5 111 110 5 110 24.5 100 100 3.6 100 23 150 140 5.6 140 33 123 120 3.5 120 28 136 133 3.9 133 31 kHz Hz µs Hz kHz Ch Characteristic i i U i Unit µA Output Drive Current — Frontplanes Supply Currents (fOSC) = 110 kHz IDD = Quiescent @ Iout = 0 µA ILCD = Quiescent @ Iout = 0 µA IDD = Quiescent @ Iout = 0 µA ILCD = Quiescent @ Iout = 0 µA µA Frequencies OSC2 Frequency @ R1; R1 = 200 kΩ FS Frequency @ R1 FS Pulse @ R1 BP Frequency @ R1 OSC2 Frequency @ R2; R2 = 996 kΩ Average DC Offset Voltage (BP Relative to FP) Input Voltage VOO 5 2.8 – 50 + 50 – 50 + 50 – 50 + 50 mV “0” Level VIL VIL 2.8 5.5 5 5 — — — — — — 0.85 1.65 — — — — V “1” Level VIH VIH 2.8 5.5 5 5 — — — — 2 3.85 — — — — — — (continued) MC145003 • MC145004 2 MOTOROLA ELECTRICAL CHARACTERISTICS (Continued) VLCD V 40°C 25°C 85°C Ch Characteristic i i S b l Symbol VDD V Min Max Min Max Min Max U i Unit Output Drive Current — Backplanes VO = 2.65 V IBH* IBL 5 5 2.8 2.8 – 290 – 290 — — – 240 – 240 — — – 240 – 240 — — µA VO = 0.15 V IBH IBL 5 5 2.8 2.8 310 310 — — 260 260 — — 230 230 — — VO = 1.08V IBH IBL 5 5 2.8 2.8 90 — — 1 40 — — 2 55 — — 1 VO = 1.72 V IBH IBL 5 5 2.8 2.8 – 90 — — – 1.5 – 40 — — –1 – 60 — — –1 VO = 5.35 V IBH IBL 5 5 5.5 5.5 – 490 – 490 — — – 520 – 520 — — – 520 – 520 — — VO = 0.15 V IBH IBL 5 5 5.5 5.5 600 600 — — 600 600 — — 580 580 — — VO = 1.98 V IBH IBL 5 5 5.5 5.5 100 — — 1.5 55 — — 1 70 — — 1 VO = 3.52 V IBH IBL 5 5 5.5 5.5 – 100 — — –1 – 35 — — –1 – 50 — — –1 Pulse Width, Data Clock (Figure 1) tw 5 3 50 100 — — ns DCLK Rise/Fall Time (Figure 1) tr, tf 5 3 — — 20 120 µs Setup Time, Din to DCLK (Figure 2) tsu 5 3 0 0 — — ns Hold Time, Din to DCLK (Figure 2) th 5 3 30 60 — — ns DCLK Low to ENB High (Figure 3) th 5 3 10 20 — — ns ENB High to DCLK High (Figure 3) trec 5 3 10 20 — — ns ENB High Pulse Width (Figure 3) tw 5 3 50 100 — — ns ENB Low to DCLK High (Figure 3) tsu 5 3 10 20 — — ns NOTE: Timing for Figures 1, 2, and 3 are design estimates only. * For a time (t = 4/OSC FREQ.) after the backplane waveform changes to a new voltage level, the circuit is maintained in the high–current state to allow the load capacitances to charge quickly. The circuit is then returned to the low–current state until the next voltage change. SWITCHING WAVEFORMS VALID tf tr Din VDD 90% CLK 50% 10% GND tsu GND tw tw VDD 50% CLK th 50% Figure 1. VDD GND Figure 2. tw ENB tw VDD 50% tsu GND th trec CLK 50% FIRST CLK LAST CLK VDD GND Figure 3. MOTOROLA MC145003 • MC145004 3 FUNCTIONAL DESCRIPTION The MC145003/MC145004 has essentially two sections which operate asynchronously from each other; the data input and storage section and the LCD drive section. The LCD drive and timing is derived from the oscillator, while the data input and storage is controlled by the Data In (Din), Data Clock (DCLK), Address (A0, A1, A2), and Enable (ENB) pins. Data is shifted serially into the 128–bit shift register and arranged into four consecutive blocks of 32 parallel data bits. A time–multiplex of the four backplane drivers is made (each backplane driver becoming active then inactive one after another) and, at the start of each backplane active period, the corresponding block of 32 bits is made available at the frontplane drivers. A high input to a plane driver turns the driver on, and a low input turns the driver off. Figure 4 shows the sequence of backplanes. Figure 5 shows the possible configurations of the frontplanes relative to the backplanes. When a backplane driver is on, its output switches from VLCD to 0 V, and when it is off, it switches from 1/3 VLCD to 2/3 VLCD. When a frontplane driver is on, its output switches from 0 V to VLCD, and when it is off, it switches from 2/3 VLCD to 1/3 VLCD. The LCD drive and timing section provides the multiplex signals and backplane driver input signals and formats the frontplane and backplane waveforms. It also provides a “frame sync” pulse which may be used in a system where many LCD drivers are cascaded, to synchronize the backplanes/frontplanes of all participating LCD drivers. The address pins are used in cascaded systems to uniquely distinguish one LCD driver from another (and from any other chips on the same bus) and to define one LCD driver as the “master” in the system. There must be one master in any system. The enable pin may be used as a third control line in the communication bus. It may be used to define the moment when the data is latched. If not used, then the data is latched after 128 bits of data have been received. TIME FRAME VLCD FRAME SYNC PULSE 0V VLCD 2/3 (VLCD) 1/3 (VLCD) BP1 0V VLCD 2/3 (VLCD) 1/3 (VLCD) BP2 0V VLCD 2/3 (VLCD) 1/3 (VLCD) BP3 0V VLCD 2/3 (VLCD) 1/3 (VLCD) BP4 0V Figure 4. Backplane Sequence MC145003 • MC145004 4 MOTOROLA TIME FRAME FRAME SYNC PULSE TIME FRAME VLCD FRAME SYNC PULSE 0V FP DATA BITS 4321 0000 1000 0100 1100 0010 1010 0110 1110 VLCD 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 2/3 (VLCD) 1/3 (VLCD) VLCD 0V FP DATA BITS 4321 0001 1001 VLCD 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 2/3 (VLCD) 1/3 (VLCD) 0V 0V VLCD 2/3 (VLCD) 1/3 (VLCD) VLCD 2/3 (VLCD) 1/3 (VLCD) 0101 0V 0V VLCD 2/3 (VLCD) 1/3 (VLCD) VLCD 2/3 (VLCD) 1/3 (VLCD) 1101 0V 0V VLCD 2/3 (VLCD) 1/3 (VLCD) VLCD 2/3 (VLCD) 1/3 (VLCD) 0011 0V 0V VLCD 2/3 (VLCD) 1/3 (VLCD) VLCD 2/3 (VLCD) 1/3 (VLCD) 1011 0V 0V VLCD 2/3 (VLCD) 1/3 (VLCD) VLCD 2/3 (VLCD) 1/3 (VLCD) 0111 0V 0V VLCD 2/3 (VLCD) 1/3 (VLCD) VLCD 2/3 (VLCD) 1/3 (VLCD) 1111 0V 0V Figure 5. Frontplane Combinations MOTOROLA MC145003 • MC145004 5 PIN DESCRIPTIONS 1. Supplying the oscillator input to all slaves. 2. Sending one frame sync pulse at the beginning of every BP1 (backplane 1) period to keep the MC145003/ MC145004 synchronized. 3. Supplying a common set of backplane signals to be shared by all participating devices in the cascaded system (if desired). NOTE Note: In applications where the circuit will be isolated from external manual interference the system designer may take advantage of the self–programming feature. Upon power–on, address pins which are left open–circuit will be charged to VDD. However, care must be taken not to inadvertently discharge the pins after power–on since the address may then be lost. A similar feature is also available on the ENB pin. CAUTION The configuration A0, A1, A2 = 000 should not be used. This does not give a valid address and is reserved for Motorola’s use only. All three address pins should never be tied to 0 V simultaneously. Any other combination of Master (111) plus six Slaves (110, 101, 100, 011, 010, 001) is allowed. ENB Enable Input (Pin 41) If the ENB pin is tied to VDD, the MC145003/MC145004 will always latch the data after 128 bits have been received. The latched data is multiplexed and fed to the frontplane drivers for display. If external control of this latching function is required (for example, in a cascaded application where multiplexing of new data may require a delay until all participating MC145003/MC145004 data is updated), then the ENB pin should be held low, followed by one high pulse on ENB when data display is required. (This may also be useful in a system where one MC145003/MC145004 is permanently addressed and only the last 128 bits of data sent are required to be latched for display). The pulse on the ENB pin must occur while DCLK is high. MC145003 • MC145004 6 DCLK, Din Data Clock and Data Input (Pins 38, 39) Address input and data input controls. See Data Input Protocol sections for relevant option. OSC1, OSC2 Oscillator Pins (Pins 51, 50) To use the on–board oscillator, an external resistor should be connected between OSC1 and OSC2 of the master device. Optionally, the OSC1 pin of the master device may be driven by an externally generated clock signal. The oscillator signal for any slave(s) in the system is provided by the master device by connecting the master’s OSC2 pin to the slaves’(s) OSC2 pin(s). The slaves’(s) OSC1 pin(s) should be connected to ground. A resistor of 680 kΩ connected between the master’s OSC1 and OSC2 pins gives an oscillator frequency of about 30 kHz, giving approximately 30 Hz as seen at the LCD driver outputs. A resistor of 200 kΩ gives about 100 kHz, which results in 100 Hz at the driver outputs. LCD manufacturers recommend an LCD drive frequency of between 30 Hz and 100 Hz. See Figure 6. EXTERNAL RESISTOR VALUE A0–A2 Address Inputs (Pins 42–44) The devices have to receive a correct address before they will accept data. Three address pins (A2, A1, A0) are used to define the states of the three programmable bits of MC145003/MC145004’s 8–bit address. The address is 0111vwxy where v, w, x represent A2, A1, and A0 respectively. Where v, w, x = 0, then A2, A1, and A0 should be tied to 0 V. Where v, w, x = 1, then A2, A1, and A0 should be tied to VDD. For systems where only one MC145003/MC145004 is used, the address pins must be tied to VDD. This defines the device as a master. Other configurations of the address pins (except 000*) defines a device to be a slave. For systems with more than one MC145003/MC145004 (cascaded application) one of the MC145003/MC145004 must have all of its address pins tied to VDD (this defines it as the master). The master is responsible for: 10 M 1M 100 k 10 k 1k 10 k 100 k 1M 10 M OSCILLATOR FREQUENCY Figure 6. Oscillator Frequency vs Load Resistance (Approximate) FS Frame Sync (Pin 37) The frame sync pin (FS) is configured as an output on the master device and as an input on the slave device(s). The master device outputs a pulse on the FS pin once at the beginning of each BP1 (backplane 1) active period to keep all MC145003/MC145004s synchronized. FP1–FP32 Frontplane Drivers (Pins 36–27, 25–22, 19–15, 13–1) Frontplane driver outputs. BP1–BP4 Backplane Drivers (Pins 48–45) Backplane driver outputs. VLCD LCD Driver Supply (Pin 20) Power supply input for LCD drive outputs. May be used to supply a temperature–compensated voltage to the LCD drive section, which can be separate from the logic voltage supply, VDD. MOTOROLA VDD Positive Power Supply (Pin 49) This pin supplies power to the main processor interface and logic portions of the device. The voltage range is 2.8 to 5.5 V with respect to the VSS pin. For optimum performance, VDD should be bypassed to VSS using a low inductance capacitor mounted very closely to these pins. Lead length on this capacitor should be minimized. VSS Ground (Pin 21) Common ground. DATA INPUT PROTOCOL Two–wire communication bus DCLK, Din; three–wire communication bus DCLK, Din, ENB. MC145003 — SPI DEVICE (FIGURE 7) Before communication with an MC145003 can begin, a start condition must be set up on the bus by the transmitter. To establish a start condition, the transmitter must pull the data line low while the clock line is high. The “idle” state for the clock line and data line is the high state. After the start condition has been established, an eight–bit address should be sent by the transmitter. If the address sent corresponds to the address of (one of) the MC145003(s) then on each successive clock pulse, the addressed device will accept a data bit. If the ENB pin is permanently high, then the addressed MC145003’s internal counter latches the data to be displayed after 128 data bits have been received. Otherwise, the control of this latch function may be overridden by holding the ENB line low until the new data is required to be displayed, then a high pulse should be sent on the ENB line. The high pulse must be sent during DCLK high (clock idle). To end communication with an MC145003, a stop condition should be set up on the bus (or another start condition may be set up if another communication is desired). Note that the communication channel to an addressed device may be left open after the 128 data bits have been sent by not setting up a stop or a start condition. In such a case, the 129th rising DCLK edge, which normally would be used to set up the stop or start condition, is ignored by the MC145003 and data continues to be received on the 130th rising DCLK. The latch function continues to work as normal (i.e., data is be latched either after each block of 128 data bits has been received or under external control as required). At any time during data transmission, the transfer may be interrupted with a stop condition. Data transmission may be resumed with a start condition and resending the address. Interfacing the MC145003 with the MC6805 family The MC145003 performs as a slave receiver in an SPI environment if the clock idle state has been defined to be “high” (SPICR5 = 1). In three–wire or four–wire SPI environments, the slave select wire (SPISS) can be used for the ENB pin on the MC145003 as described above. Note that in full duplex SPI environments, MC145003 only receives data, it does not re–transmit data. MC145004 — IIC DEVICE (FIGURE 8) Before communication with an MC145004 can begin, a start condition must be set up on the bus by the controller. To establish a start condition, the controller must pull the data line low while the clock line is high. MOTOROLA After the start condition has been established, an eight–bit address should be sent by the controller followed by an extra clock pulse while the data line is left high. In this option, only the seven most significant bits of the address are used to uniquely define devices on the bus, the least significant bit is used as a read/write control: if the least significant bit is 0, then the controller writes to the LCD driver; if it is 1, then the controller reads from the LCD driver’s 128–bit shift register on a first–in first–out basis. If the seven most significant address bits sent correspond to the address of (one of) the LCD driver(s) then the addressed LCD driver responds by sending an “acknowledge” bit back to the controller (i.e., the LCD driver pulls the data line low during the extra clock pulse supplied by the controller). If the least significant address bit was 0, then the controller should continue to send data to the LCD driver in blocks of eight bits followed by an extra ninth clock pulse to allow the LCD driver to pull the data line Din low as an acknowledgement. If the least significant address bit was 1, then the LCD driver sends data back to the controller (the clock is supplied by the controller). After each successive group of eight bits sent, the LCD driver leaves the data line high for one pulse. If the ENB pin is permanently high, then the addressed MC145004’s internal counter latches the data to be displayed after 128 data bits have been received. Otherwise the control of this latch function may be overridden by holding the ENB line low until the new data is required to be displayed, then a high pulse should be sent on the ENB line. The high pulse must be sent during DCLK high (clock idle). To end communication with an MC145004, a stop condition should be set up on the bus (or another start condition may be set up if another communication is desired). Note that the communication channel to an addressed device may be left open after the 128 data bits have been sent by not setting up a stop or a start condition. In such a case the rising DCLK edge which comes after all 128 data bits have been sent and after the last acknowledge–related clock pulse has been made is ignored; data continues to be received on the following DCLK high. The latch function continues to work as normal (i.e., data is latched either after each block of 128 data bits has been received or under external control as required). At any time during data transmission, the transfer may be interrupted with a stop condition. Data transmission may be resumed with a start condition and resending the address. CASCADED OPERATION The master device supplies the oscillator input via its OSC2 pin to the slave devices via their OSC2 pin(s). It sends a frame sync pulse via its FS pin to the slaves via their FS pins at the beginning of every BP1 valid time. In Figure 9, the ENB pins are tied together and used as a chip enable to latch the new data — the ENB pins could have been tied to VDD if it were desirable to use the internal data bit counter to latch the new data. The four backplane inputs may come from the master only, with the slave backplanes being left open, as shown in Figure 6, or if more drive is required, then the slaves’ backplanes may be connected to the corresponding backplanes of the master. Example: at room temperature, with a drive frequency of 30 Hz, around four to five MC145003/MC145004s may be used in a system where only the master’s backplanes are connected to the LCD. For applications with heavier loads (e.g., large liquid crystals) or high drive frequencies or at high temperatures, the dc voltage component seen by the LCD may be kept to a minimum by connecting the corresponding backplanes of all participating MC145003/MC145004s together. MC145003 • MC145004 7 MC145003 • MC145004 8 ENB (IF USED) DCLK D in START A1 A0 FP1 BP3 BP2 BP1 BP4 x: 1 →(BPi, FPj) ON 0 →(BPi, FPj) OFF FP1 FP2 FP4 FP5 FP6 Figure 7b. Serial 128 Bits Data FP3 BP1 128-BITS DATA FP2 BP3 BP2 Figure 7a. Data Input — MC145003 BP4 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 D in x BP 8-BITS ADDRESS A2 •• • Figure 7. MC145003 (SPI DEVICE) MOTOROLA FP32 4 3 2 1 ENABLE PULSE MAY OCCUR AS REQUIRED; BUT MUST BE DURING DCLK HIGH. START 129TH DCLK HIGH: (DOES NOT SHIFT DATA) Figure 8. Data Input MC145004 (IIC Device) MOTOROLA MC145003 • MC145004 9 START D in (FROM LCD DRIVER) DCLK D in (FROM CONTROLLER) START READ FROM LCD DRIVER ENB (IF USED) D in (FROM LCD DRIVER) DCLK D in (FROM CONTROLLER) WRITE TO LCD DRIVER A1 A0 8-BITS ADDRESS ENTIRE CLK FOR ACKNOWLEDGE PULLED LOW BY DRIVER ENTIRE CLK FOR ACKNOWLEDGE BP4 BP3 LEFT HIGH BY CONTROLLER BP1 BP4 8-BITS DATA 8-BITS DATA BP2 FP1 ADDRESS ACKNOWLEDGED BY DRIVER (LOW-ORDER BIT = 1) 8-BITS ADDRESS A2 (LOW-ORDER BIT = 0) BP3 ENTIRE CLK FOR ACKNOWLEDGE LEFT HIGH BY DRIVER LEFT HIGH BY DRIVER STOP LAST DCLK PULSE (DOES NOT SHIFT DATA) CONTINUES TO CLOCK DATA AND ACKNOWLEDGE ENTIRE CLK FOR ACKNOWLEDGE ENABLE PULSE MAY OCCUR AS REQUIRED; BUT MUST BE DURING DCLK HIGH. STOP LAST DCLK PULSE (DOES NOT SHIFT DATA) CONTINUES TO CLOCK DATA AND ACKNOWLEDGE ENTIRE CLK FOR ACKNOWLEDGE BP1 LEFT HIGH BY CONTROLLER PULLED LOW BY DRIVER BP2 FP2 MC145003 • MC145004 10 FP22 FP8 FP21 FP20 FP9 FP10 FP11 FP13 FP12 FP25 Din A1 A2 FP10 ENB FP15 VLCD VSS FP14 FP13 FP12 FP11 BP4 A0 BP3 LCD DRIVER (MASTER) FP26 VSS FP14 FP27 FP26 LCD DRIVER (SLAVE) FP27 FP15 VLCD FP16 FP17 DCLK FP30 FS FP29 FP1 FP28 FP2 FP25 FP5 FP24 FP6 FP23 FP7 FP22 FP8 FP21 FP9 FP31 DCLK FP30 FS FP29 FP1 FP28 FP2 CONTROLLER V DD VLCD VSS FP6 FP7 FP16 BP1 BP2 V DD OSC2 FP19 FP18 ENB A1 A2 BP4 A0 BP3 BP1 BP2 V DD OSC1 OSC2 BP1–BP4 680 k Ω ON BUS TO OTHER CHIPS BP1–BP4 FP1–FP32 FP1–FP32 FP31 SS CLOCK DATA FP24 FP23 FP17 FP32 OSC1 FP20 FP19 FP18 FP1–FP32 FP33–FP64 LIQUID CRYSTAL DISPLAY FP32 Din FP3 FP4 FP3 FP4 FP5 Figure 9. Cascading Example MOTOROLA APPLICATION INFORMATION Figure 10 shows an interface example. Example 1 shows a semi–automatic SPI Mode (only start and stop conditions are done in non–SPI Mode). Example 2 contains the software to use HC11 with MC145003 in manual SPI Mode. Both examples use the same hardware connection. VDD VDD 1 kΩ A0 MOSI MC68HC11 A1 A2 OSC1 Din SCK DCLK SS ENB R = 470 kΩ MC145003 BP1–BP4 OSC2 FP1–FP32 1/4 MUX DISPLAY Figure 10. Interface Example Between MC68HC11 and MC145003 CPOL = 0 CPHA = 0 SPI Off EW = 0 Setup Start Condition with SPI off (Write Data Port to 0) SPI On < ldaa $73, staa $1028 Send Address Byte $7E Send 16 bytes of Data SPI Off < ldaa $33, staa $1028 DATA = 0 SPI Off ENB = 1 Allows the latch of data to the FP outputs CLK = 1 DATA = 1 Stop Condition Example 1. Semi–Automatic SPI Method MOTOROLA MC145003 • MC145004 11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 0000 0000 0000 0000 0000 0000 0000 T T T T T T T ;=======CONSTANTS================================================= extram equ $A000 ;$A000 for 8K RAM stack equ $00FF ;last RAM byte intofs equ $1000 ;Internal Registers data equ $08 clock equ $10 enable equ $20 portd equ 8 A000 A000 A003 A005 A008 A00A A00D A010 T N M T M N T T 8E00FF 8638 B71009 C611 CEA05E BDA010 ;=======PROGRAM BEGIN============================================= org extram ;Program into RAM cold lds #stack ;set stack pointer ldaa #$38 ;set of MOSI,SS,SCK staa $1009 ;DDRD ldab #17 ldx #send jsr spi end cold A010 A014 A018 A01B A01D A020 A025 A026 A027 A029 A02D A030 U J T X T L H H R J T H 18CE1000 181D0820 BDA031 A600 B7102A 181F2980FB 08 5A 26F2 181C0820 BDA04C 39 A031 A033 A036 A03A A03E A042 A046 A048 A04B A04C A04E A051 A055 A059 A05D M T J J J J M T H M T J J J H 8633 B71028 181C0808 181C0810 181D0808 181D0810 8673 B71028 39 8633 B71028 181D0808 181C0810 181C0808 39 start A05E A05F A060 A061 A062 A063 A064 A065 A066 A067 A068 A069 A06A A06B A06C A06D A06E A06F T T T T T T T T T T T T T T T T T H 7E F0 F0 F0 F0 F0 F0 F0 F0 F0 F0 F0 F0 F0 F0 F0 F0 39 send spi again stop ldy bclr jsr ldaa staa brclr inx decb bne bset jsr rts #intofs portd,y #enable start 0 , x $102A $29,y,#$80,* ;EN = 0 ;start condition ;SPI Mode Use ;SPDR ;next DATA again portd,y #enable stop ;stop condition ldaa staa bset bset bclr bclr ldaa staa rts ldaa staa bclr bset bset rts #$33 $1028 portd,y portd,y portd,y portd,y #$73 $1028 #data #clock #data #clock ;Normal Mode ;SPCR ;DATA = 1 ;CLK = 1 ;DATA = 0 ;CLK = 0 ;SPI Mode ;SPCR #$33 $1028 portd,y #data portd,y #clock portd,y #data ;Normal Mode ;SPCR ;DATA = 0 ;CLK = 1 ;DATA = 0 fcb fcb fcb fcb fcb fcb fcb fcb fcb fcb fcb fcb fcb fcb fcb fcb fcb rts $007E $00f0 $00f0 $00f0 $00f0 $00f0 $00f0 $00f0 $00f0 $00f0 $00f0 $00f0 $00f0 $00f0 $00f0 $00f0 $00f0 ;LCD Driver Address ;Data to sent ;=======PROGRAM END=============================================== Example 2. Manual Method MC145003 • MC145004 12 MOTOROLA PACKAGE DIMENSIONS QFP FU SUFFIX CASE 848B–02 L DETAIL A 52 D S V C A–B B M L 0.20 (0.008) -D- -A- 0.20 (0.008) M H A–B 0.05 (0.002) A–B S D S 26 40 S 27 39 14 B 13 1 B -DB 0.20 (0.008) M H A–B 0.05 (0.002) A–B S D S -A,B,DDETAIL A V 0.20 (0.008) M C A–B S D S F DETAIL C M C E J -H- -CH SEATING PLANE N DATUM PLANE BASE METAL 0.10 (0.004) G D M 0.02 (0.008) M C A–B S D S SECTION B-B U T DATUM PLANE R -H- Q K W X DETAIL C MOTOROLA NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –A–, –B– AND –D– TO BE DETERMINED AT DATUM PLANE –H–. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –C–. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –H–. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. DIM A B C D E F G H J K L M N Q R S T U V W X MILLIMETERS MIN MAX 10.10 9.90 10.10 9.90 2.45 2.10 0. 38 0.22 2.10 2.00 0.33 0.22 0.65 BSC 0.25 — 0.23 0.13 0.95 0.65 7.80 REF 10° 5° 0.13 0.17 0° 7° 0.13 0.30 12.95 13.45 0.13 — 0° — 12.95 13.45 0.35 0.45 1.6 REF INCHES MIN MAX 0.390 0.398 0.390 0.398 0.083 0.096 0.009 0.015 0.079 0.083 0.009 0.013 0.026 BSC 0.010 — 0.005 0.009 0.026 0.037 0.307 REF 10° 5° 0.005 0.007 0° 7° 0.005 0.012 0.510 0.530 0.005 — 0° — 0.510 0.530 0.014 0.018 0.063 REF MC145003 • MC145004 13 Motorola reserves the right to make changes without further notice to any products herein. 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