WEDC WED7P1G0CFA7000I25

White Electronic Designs
WED7PxxxCFA70xxI25
CompactFlashTM Card
perfect choice for solid-state mass-storage in industrial
applications and applications that require performance and
extended environmental tolerances. Other applications
include handheld devices such as Digital Cameras, Audio
Players, and PDAs.
FEATURES
CompactFlashTM Compatibility
• 3.3V or 5.0V single power supply.
• 50 pin two piece connector with Type-I form
factor (3.3mm thickness)
• Support for CIS implementation with 256 bytes of
attribute memory
Lead free and RoHS compliant
Interface modes
• PC card memory mode
• True IDE mode
Power consumption:
• 5V operation
Active mode:
Write operation: 28 mA (Typ.)
Read operation: 23 mA (Typ.)
Power down mode: 1.2mA (Typ.) 2.0mA (max.)
• Sustained write: max 6.0 Mbytes/s in ATA PIO
mode 4 cycle timing
• Sustained read: max 6.5 Mbytes/s in ATA PIO
mode 4 cycle timing
W/E Endurance:
Operating Voltage:
3.3V ± 5%
5.0V ± 0.5V
High performance
• Interface Transfer speed in PIO mode 4 or Multi
Word DMA mode 2 cycle timing, 16.6 Mbytes/
second (theoretical)
Storage Capacities:
128MB, 256MB, 512MB and 1.02GB (unformatted)
• PC card I/O mode
Dimensions:
Type I card : 36.4mm(L) x 42.8mm (W) x 3.3mm (H)
• 3.3V operation
Active mode:
Write operation: 25 mA (Typ.)
Read operation: 21 mA (Typ.)
Power down mode: 1.0mA (Typ.) 1.5mA (max.)
100,000cycles1 /300,000cycles2
Notes: 1. TA = -40 to 85°C
2. TA = 0 to 70°C
DESCRIPTION
Environment conditions:
• Operating temperature: -40°C to 85°C
The WED7PxxxCFA70xxI25 series CompactFlash™ card
is an ATA interface flash memory card based on flash
technology. The CompactFlash™ card is constructed with
a flash disk controller chip and NAND-type flash memory
device. Operates from a single 5-Volt or 3.3-Volt power
source. The card is available in CompactFlash™ type-I
form factor with 128MB, 256MB, 512MB and 1.02GB
unformatted capacity. Being able to emulate IDE hard disk
drives and certified in accordance with the CompactFlash™
Certification Plan, WEDC’s CompactFlash™ card is a
• Storage temperature: -45°C to 90°C
• Storage humidity: 95% (max) (No condensation)
* This product is subject to change without notice.
Notes: CompactFlash™ is a trademark of SanDisk Corporation and is licensed royaltyfree to the CFA, which in turn will license it royalty-free to CFA members.
CFA: CompactFlash™ Association.
PRODUCT TYPES
Card Density
128MB
256MB
512MB
1.02GB
Model No.
7P128CFA70xxI25
7P256CFA70xxI25
7P512CFA70xxI25
7P1G0CFA70xxI25
Cylinder
978
978
993
1985
Head
8
16
16
16
Sector
32
32
63
63
Memory capacity1
128,188,416 Byte
256,376,832 Byte
512,483,328 Byte
1024,450,560 Byte
1: It is the logical address capacity including the area used for File System.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED7PxxxCFA70xxI25
PIN ASSIGNMENTS AND PIN TYPE
PC Card Memory Mode
1
2
3
4
5
6
7
8
9
Signal
Name
GND
D03
D04
D05
D06
D07
CE1#
A10
OE#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
A09
A08
A07
VCC
A06
A05
A04
A03
A02
A01
A00
D00
D01
D02
WP
CD2#
CD1#
D111
D121
D131
D141
D151
CE21#
VS1#
IORD#
IOWR#
WE#
READY
VCC
CSEL#
VS2#
RESET
Pin
Pin Type
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
O
O
O
I/O
I/O
I/O
I/O
I/O
I
O
I
I
I
O
I
O
I
PC Card I/O Mode
In, Out
Type
Ground
I4Z,OZ1
I4Z,OZ1
I4Z,OZ1
I4Z,OZ1
I4Z,OZ1
I3U
I3Z
I4U
I3Z
I3Z
I3Z
Power
I3Z
I3Z
I3Z
I3Z
I3Z
I3Z
I3Z
I4Z,OZ1
I4Z,OZ1
I4Z,OZ1
OT1
Ground
Ground
I4Z,OZ1
I4Z,OZ1
I4Z,OZ1
I4Z,OZ1
I4Z,OZ1
I3U
Ground
I4U
I4U
I4U
OT1
Power
I1U
OPEN
I3U
1
2
3
4
5
6
7
8
9
Signal
Name
GND
D03
D04
D05
D06
D07
CE1#
A10
OE#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
A09
A08
A07
VCC
A06
A05
A04
A03
A02
A01
A00
D00
D01
D02
IOIS16#
CD2#
CD1#
D111
D121
D131
D141
D151
CE21#
VS1#
IORD#
IOWR#
WE#
IREQ#
VCC
CSEL#
VS2#
RESET
Pin
True IDE Mode
In, Out
Type
Ground
I4Z,OZ1
I4Z,OZ1
I4Z,OZ1
I4Z,OZ1
I4Z,OZ1
I3U
I3Z
I4U
Pin Type
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I3Z
I3Z
I3Z
Power
I3Z
I3Z
I3Z
I3Z
I3Z
I3Z
I3Z
I4Z,OZ1
I4Z,OZ1
I4Z,OZ1
OT1
Ground
Ground
I4Z,OZ1
I4Z,OZ1
I4Z,OZ1
I4Z,OZ1
I4Z,OZ1
I3U
Ground
I4U
I4U
I4U
OT1
Power
I1U
OPEN
I3U
I
I
I
I
I
I
I
I/O
I/O
I/O
O
O
O
I/O
I/O
I/O
I/O
I/O
I
O
I
I
I
O
I
O
I
1
2
3
4
5
6
7
8
9
Signal
Name
GND
D03
D04
D05
D06
D07
CS0#
A102
ATA# SEL
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
A092
A082
A072
VCC
A062
A052
A042
A032
A02
A01
A00
D00
D01
D02
IOIS16#
CD2#
CD1#
D111
D121
D131
D141
D151
CS11#
VS1#
DIOR#
DIOW#
WE3#
INTRQ
VCC
CSEL#
VS2#
RESET#
Pin
Pin Type
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
O
O
O
I/O
I/O
I/O
I/O
I/O
I
O
I
I
I
O
I
O
I
In, Out
Type
Ground
I4Z,OZ1
I4Z,OZ1
I4Z,OZ1
I4Z,OZ1
I4Z,OZ1
I3U
I3Z
I4U
I3Z
I3Z
I3Z
Power
I3Z
I3Z
I3Z
I3Z
I3Z
I3Z
I3Z
I4Z,OZ1
I4Z,OZ1
I4Z,OZ1
ON1
Ground
Ground
I4Z,OZ1
I4Z,OZ1
I4Z,OZ1
I4Z,OZ1
I4Z,OZ1
I3U
Ground
I4U
I4U
I4U
OZ1
Power
I1U
OPEN
I3U
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 1
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED7PxxxCFA70xxI25
PIN ASSIGNMENTS AND PIN TYPE (cont'd)
PC Card Memory Mode
PC Card I/O Mode
True IDE Mode
Pin
Signal
Name
Pin Type
In, Out
Type
Pin
Signal
Name
Pin Type
In, Out
Type
Pin
Signal
Name
Pin Type
In, Out
Type
42
WAIT#
O
OT1
42
WAIT#
O
OT1
42
IORDY
O
ON1
43
INPACK#
O
OT1
43
INPACK#
O
OT1
43
DMARQ
O
OZ1
44
REG#
I
I3U
44
REG#
I
I3U
44
DMACK#
I
I3U
45
BVD2
I/O
I4U,OT1
45
SPKR#
I/O
I4U,OT1
45
DASP#
I/O
I4U,ON1
46
BVD1
I/O
I4U,OT1
46
STSCHG#
I/O
I4U,OT1
46
PDIAG#
I/O
I4U,ON1
47
D081
I/O
I4Z,OZ1
47
D081
I/O
I4Z,OZ1
47
D081
I/O
I4Z,OZ1
48
D091
48
D091
I/O
I4Z,OZ1
48
D091
I/O
I4Z,OZ1
49
D101
I4Z,OZ1
49
D101
I4Z,OZ1
49
D101
I/O
I4Z,OZ1
50
GND
Ground
50
GND
Ground
50
GND
I/O
I/O
I4Z,OZ1
I/O
Ground
Notes: 1. These signals are required only for 16 bit access and not required when installed in 8 bit systems. Devices allow for 3-state signals to consume no current.
2. Should be grounded by the host.
3. Should be tied to VCC by the host.
ACCESS SPECIFICATIONS
1. Attribute access specifications
When CIS-ROM region or Configuration register region is accessed, read and write operations are executed under the
condition of REG# = ”L” as follows. That region can be accessed by Byte/Word/Odd-byte modes, which are defined by
PC card standard specifications.
Attribute Read Access Mode
Mode
Standby mode
Byte access (8bit)
REG#
CE2#
CE1#
A0
OE#
WE#
D8 to D15
D0 to D7
X
H
H
X
X
X
High-Z
High-Z
L
H
L
L
L
H
High-Z
even byte
L
H
L
H
L
H
High-Z
Invalid
Word access (16bit)
L
L
L
X
L
H
invalid
even byte
Odd byte access (8bit)
L
L
H
X
L
H
invalid
High-Z
Note: X → L or H
Attribute Write Access Mode
Mode
Standby mode
Byte access (8bit)
REG#
CE2#
CE1#
A0
OE#
WE#
D8 to D15
D0 to D7
X
H
H
X
X
X
Don’t care
Don’t care
L
H
L
L
H
L
Don’t care
even byte
L
H
L
H
H
L
Don’t care
Don’t care
Word access (16bit)
L
L
L
X
H
L
Don’t care
even byte
Odd byte access (8bit)
L
L
H
X
H
L
Don’t care
Don’t care
Note: X → L or H
Write CIS-ROM region is invalid.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 1
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED7PxxxCFA70xxI25
2. Task File register access specifications
There are two types of Task File register mapping, one is mapped I/O address area, the other is mapped Memory address
area. Each type of Task File register read and write operation is executed under the condition as follows. That area can
be accessed by Byte/Word/Odd Byte modes, which are defined by PC card standard specifications.
(1) I/O address map – Task File Register Read Access Mode (1)
Mode
Standby mode
Byte access (8bit)
REG#
CE2#
CE1#
A0
IORD#
IOWR#
OE#
WE#
D8 to D15
D0 to D7
X
H
H
X
X
X
X
X
High-Z
High-Z
L
H
L
L
L
H
H
H
High-Z
even byte
L
H
L
H
L
H
H
H
High-Z
odd byte
Word access (16bit)
L
L
L
X
L
H
H
H
odd byte
even byte
Odd byte access (8bit)
L
L
H
X
L
H
H
H
odd byte
High-Z
Note: X → L or H
Task File Register Write Access Mode (1)
Mode
Standby mode
Byte access (8bit)
REG#
CE2#
CE1#
A0
IORD#
IOWR#
OE#
WE#
D8 to D15
D0 to D7
X
H
H
X
X
X
X
X
Don’t care
Don’t care
L
H
L
L
H
L
H
H
Don’t care
even byte
L
H
L
H
H
L
H
H
Don’t care
odd byte
Word access (16bit)
L
L
L
X
H
L
H
H
odd byte
even byte
Odd byte access (8bit)
L
L
H
X
H
L
H
H
odd byte
Don’t care
Note: X → L or H
(2) Memory address map – Task File Register Read Access Mode (2)
Mode
Standby mode
Byte access (8bit)
REG#
CE2#
CE1#
A0
OE#
WE#
IORD#
IOWR#
D8 to D15
D0 to D7
X
H
H
X
X
X
X
X
High-Z
High-Z
H
H
L
L
L
H
H
H
High-Z
even byte
H
H
L
H
L
H
H
H
High-Z
odd byte
Word access (16bit)
H
L
L
X
L
H
H
H
odd byte
even byte
Odd byte access (8bit)
H
L
H
X
L
H
H
H
odd byte
High-Z
Note: X → L or H
Task File Register Write Access Mode (2)
Mode
Standby mode
Byte access (8bit)
REG#
CE2#
CE1#
A0
OE#
WE#
IORD#
IOWR#
D8 to D15
D0 to D7
X
H
H
X
X
X
X
X
Don’t care
Don’t care
H
H
L
L
H
L
H
H
Don’t care
even byte
H
H
L
H
H
L
H
H
Don’t care
odd byte
Word access (16bit)
H
L
L
X
H
L
H
H
odd byte
even byte
Odd byte access (8bit)
H
L
H
X
H
L
H
H
odd byte
Don’t care
Note: X → L or H
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 1
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED7PxxxCFA70xxI25
3. TRUE IDE MODE
The card can be configured in a True IDE. This card is configured in this mode only when the OE# input signal is asserted
to GND by the host during power on . In this True IDE mode Attribute Registers are not accessible from the host. Only
I/O operation to the task file and data register is allowed. If this card is configured during power on sequence, data
register is accessed in word (16-bit). The card permits 8-bit accesses if the user issues a Set Feature Command to put
the device in 8-bit mode.
True IDE Mode Read I/O Function
Mode
CE2#
CE1#
A0~A2
DMACK#
DIOR#
DIOW#
D8~D15
D0~D7
Invalid mode
L
L
X
X
X
X
High-Z
High-Z
Standby mode
H
H
X
H
X
X
High-Z
High-Z
PIO Data register access
H
L
0
H
L
H
Odd byte
even byte
Multiword DMA Data register access
H
H
X
L
L
H
Odd byte
even byte
Alternate status access
L
H
6H
H
L
H
High-Z
Status out
Other task file access
H
L
1~7H
H
L
H
High-Z
Data
DIOR#
DIOW#
D8~D15
D0~D7
Note: X → L or H
True IDE Mode Write I/O Function
Mode
CE2#
CE1#
A0~A2
DMACK#
Invalid mode
L
L
X
X
X
X
Don’t care
Don’t care
Standby mode
H
H
X
H
X
X
Don’t care
Don’t care
PIO Data register access
H
L
0
H
H
L
Odd byte
even byte
Multiword DMA Data register access
H
H
X
L
H
L
Odd byte
even byte
Control register access
L
H
6H
H
H
L
Don’t care
Control in
Other task file access
H
L
1~7H
H
H
L
Don’t care
Data
Note: X → L or H
CARD SYSTEM PERFORMANCE
ITEM
PERFORMANCE
Set up time (Reset to Ready)
250 ms (max.)
Set up time (Power down to Ready)
5.5 ms (max.)
Data transfer rate to / from host
16.6 M byte / s burst (max.), theoretically
Sustained read transfer rate
6.5 M byte / s (max.), actually *1
Sustained write transfer rate
6.0 M byte / s (max.), actually *1
Command to DRQ (Sector Re ad at Ready state)
4 ms (max.)
Command to DRQ (Sector Write at Ready state)
700 ms (max.)
Data transfer cycle end to ready (Sector write)
2 ms (typ.), 200 ms (max.)
Auto Power down time
1.5s (min.), 1.8s (typ.)
Notes:
1. The actual transfer rate is measured under ATA PIO mode 4 with single cycle time as 120ns.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 1
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED7PxxxCFA70xxI25
ELECTRICAL SPECIFICATION
SYMBOL
PARAMETER
MIN
MAX
TYP
UNIT
VIN, VOUT
All input / output voltage
-0.3
VCC+0.3
—
V
VCC
Power Supply Voltage
(Absolute Maximum Ratings)
-0.6
6.0
—
V
4.5
5.5
5.0
V
3.135
3.465
3.3
V
Operating Temperature
-40
85
—
°C
Storage Temperature
-45
90
—
°C
VCC
Power Supply Voltage
(Recommended Operation Condition)
TOPR
TSTG
Input Leakage Current
Type
SYMBOL
PARAMETER
CONDITION
MIN
MAX
TYP
UNIT
NOTES
IxZ
IL
Input leakage current
VIH = Vcc / VIL = GND
-1
1
—
µA
*1
IxU
RPU1
Pull Up Resistor
Vcc = 5.0V
50
500
—
kΩ
*1
IxD
RPD1
Pull Down Resister
Vcc = 5.0V
50
500
—
kΩ
*1
Notes:
1. x refers to the characteristics described in section “DC Characteristics ( Input Characteristics)”. For example, I1U indicates a pull up resister with a type 1 input characteristics.
Output Drive Type
Type
OUTPUT TYPE
VALID CONDITIONS
NOTES
OTx
Totempole
IOH & IOL
*1
OZx
Tri-State N-P Channel
IOH & IOL
*1
OPx
P-Channel only
IOH Only
*1
ONx
N-Channel only
IOL Only
*1
Notes:
1. x refers to the characteristics described in section “DC Characteristics ( Output Drive Characteristics)”. Fo r example, OT1 refers to Totempole output with a type 1 Output drive
characteristics.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 1
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED7PxxxCFA70xxI25
DC CHARACTERISTICS
VCC = 3.3 V ± 5%, 5 V ± 0.5V, -40°C ≤ TA ≤ 85°C
SYMBOL
ILI
ILO
IPU
IPD
PARAMETER
Input leakage current
Output leakage current
Pull-up current (Resistivity)
Pull-down current (Resistivity)
ICCS
Power down mode current
ICCO
Operating current @ 3.3V
Write operation
Read operation
Operating current @ 5V
Write operation
Read operation
MIN
—
—
—
—
—
—
MAX
1
1
—
—
1.5
2.0
TYP.
—
—
43 (75)
-43 (75)
1.0
1.2
UNIT
µA
µA
µA (kΩ)
µA (kΩ)
TEST CONDITIONS
—
VOUT = high impedance
VFORCE = 3.3V
VFORCE = 0V
VCC = 3.3V
VCC = 5V
—
—
—
—
25
21
mA
VCC = 3.3V operation
—
—
—
—
28
23
mA
VCC = 5V operation
mA
Input Characteristics
Type
SYMBOL
PARAMETER
MIN
2.0
2.0
—
—
Input High Voltage CMOS
VIL
Input Low Voltage CMOS
—
1.0
1.0
—
VIH
Input High Voltage
2.0
2.0
—
—
VIL
Input Low Voltage CMOS
—
2
VT+
VTVt
VT+
4
TYP
VIH
1
3
MAX
VTVt
Input Low to High threshold
Schmitt trigger
Input High to Low threshold
Schmitt trigger
1.0
0.8
2.5
2.5
—
0.9
0.9
0.5
0.8
Hysteresis voltage
Input Low to High threshold
Schmitt trigger
Input High to Low threshold
Schmit trigger
—
2.3
2.0
—
1.0
0.8
0.5
0.8
Hysteresis voltage
UNIT
—
2.1
2.1
1.2
1.2
V
2.1
1.8
1.2
1.1
CONDITION
VCC = 3.3 V
VCC = 5 V
VCC = 3.3 V
VCC = 5 V
VCC = 3.3 V
VCC = 5 V
VCC = 3.3 V
VCC = 5 V
VCC = 3.3 V
VCC = 5 V
VCC = 3.3 V
VCC = 5 V
VCC = 3.3 V
VCC = 5 V
VCC = 3.3 V
VCC = 5 V
VCC = 3.3 V
VCC = 5 V
VCC = 3.3 V
VCC = 5 V
Output Drive Characteristics
Type
1
SYMBOL
PARAMETER
MIN
MAX
TYP
VOH
Output High Voltage
VCC - 0.8
—
—
VOL
Output Low Voltage
—
Gnd + 0.4
—
UNIT
CONDITION
V
IOH = -4mA
IOL = 4mA
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July 2005
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7
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WED7PxxxCFA70xxI25
AC CHARACTERISTICS
VCC = 3.3 V ± 5%, 5 V ± 0.5V, -40°C ≤ TA ≤ 85°C
Attribute Memory Read AC Characteristics
SYMBOL
tC
tA
tA
tA
tDIS
tDIS
tEN
tEN
tV
tSU
PARAMETER
Read cycle time
Address access time
CE# access time
OE# access time
Output disable time (CE#)
Output disable time (OE#)
Output enable time (CE#)
Output enable time (OE#)
Data valid time (A)
Address setup time
MIN
250
—
—
—
—
—
5
5
0
30
MAX
—
250
250
125
100
100
—
—
—
—
UNIT
MAX
—
—
—
—
—
—
UNIT
MAX
100
—
—
—
—
—
—
—
—
45
45
35
35
UNIT
ns
Attribute Memory Write AC Characteristics
SYMBOL
tC
tW
tSU
tSU
tH
tREC
PARAMETER
Write cycle time
Write pulse time
Address setup time
Data setup time (-WE)
Data hold time
Write recover time
MIN
250
150
30
80
30
30
ns
I/O Access Read AC Characteristics
SYMBOL
tD
tH
tW
tSUA
tHA
tSUCE
tHCE
tSUREG
tHREG
tDFINPACK
tDRINPACK
tDFIOIS16
tDRIOIS16
PARAMETER
Data delay after IORD#
Data hold following IORD#
IORD# pulse width
Address setup before IORD#
Address hold following IORD#
CE# setup before IORD#
CE# hold following IORD#
REG# setup before IORD#
REG# hold following -IORD
INPACK# delay failing from IORD#
INPACK# delay rising from IORD#
IOIS#16 delay failing from address
IOIS#16 delay rising from address
MIN
—
0
165
70
20
5
20
5
0
0
—
—
—
ns
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July 2005
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WED7PxxxCFA70xxI25
I/O Access Write AC Characteristics
SYMBOL
tSU
tH
tW
tSUA
tHA
tSUCE
tHCE
tSUREG
tHREG
tDFIOIS16
tDRIOIS16
PARAMETER
Data setup before IOWR#
Data hold following IOWR#
IOWR# pulse width
Address setup before IOWR#
Address hold following IOWR#
CE# setup before IOWR#
CE# hold following IOWR#
REG# setup before IOWR#
REG# hold following IOWR#
IOIS16# delay failing from address
IOIS16# delay rising from address
MIN
60
30
165
70
20
5
20
5
0
—
—
MAX
—
—
—
—
—
—
—
—
—
35
35
UNIT
ns
Common Memory Access Read AC Characteristics
SYMBOL
tA
tDIS
tSU
tH
tSU
tH
PARAMETER
OE# access time
Output disable time (OE#)
Address setup time
Address hold time
CE# setup before OE#
OE# hold following OE#
MIN
—
—
30
20
0
20
MAX
125
100
—
—
—
—
UNIT
ns
Common Memory Access Write AC Characteristics
SYMBOL
tSU
tH
tW
tH
tSU
tSU
tREC
tH
PARAMETER
Data setup before WE#
Data hold following WE#
Write pulse width
Address hold time
Address setup time
CE# setup time
Write recover time
CE# hold following WE#
MIN
80
30
150
20
30
0
30
20
MAX
—
—
—
—
—
—
—
—
UNIT
ns
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
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9
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White Electronic Designs
WED7PxxxCFA70xxI25
True IDE Mode IO Read/Write AC Characteristics
SYMBOL
t0
t1
t2
t2
t2i
t3
t4
t5
t6
t6z
t7
t8
t9
PARAMETER
Cycle time
Address valid to -DIOW/-DIOR setup
DIOW#/-DIOR
DIOW#/-DIOR Register (8bit)
DIOW#/-DIOR recoverry time
DIOW# data setup
DIOW# data hold
DIOR# data setup
DIOR# data hold
DIOR# data tristate
Address valid to -IOIS16 assertion
Address valid to -IOIS16 released
DIOW#/-DIOR to address valid hold
MIN
120
25
70
70
25
20
10
20
5
—
—
—
10
MAX
—
—
—
—
—
—
—
—
—
30
35
35
—
UNIT
ns
True IDE Mode Multiword DMA Read/Write AC Characteristics
SYMBOL
t0
tD
tE
tF
tG
tH
tI
tJ
tKR
tKW
tLR
tLW
tM
tN
tZ
PARAMETER
Cycle time
DIOR#/DIOW# assert width
DIOR# data access
DIOR# data hold
DIOW#/DIOR# data setup
DIOW# data hold
DMACK# to DIOR#/DIOW# setup
DIOR#/DIOW# to DMACK hold
DIOR# negated width
DIOW# negated width
DIOR# to DMARQ delay
DIOW# to DMARQ delay
CS0#/CS1# valid to -DIOR#/-DIOW#
CS0#/CS1# hold
DMACK# to read data released
MIN
120
70
—
5
20
10
0
5
25
25
—
—
25
10
—
MAX
—
—
50
—
—
—
—
—
—
—
35
35
—
—
25
UNIT
ns
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
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White Electronic Designs
WED7PxxxCFA70xxI25
Reset Characteristics (only Memory Card Mode or I/O Card Mode)
SYMBOL
PARAMETER
MIN
MAX
UNIT
tSU
Reset setup time
100
—
ms
tREC
CE# recover time
1
—
µs
tPR
VCC rising up time
0.1
100
ms
tPF
VCC falling down time
ms
tW
tH
Reset pulse width
tS
3
300
10
—
µs
1
—
ms
0
—
ms
MAX
UNIT
Power on Reset Characteristics
Power on reset sequence must need by PORST# at the rising edge of VCC.
SYMBOL
PARAMETER
MIN
tSU
CE# setup time
100
—
ms
tPR
VCC rising up time
0.1
100
ms
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 1
11
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WED7PxxxCFA70xxI25
PACKAGE DIMENSIONS
Top View
1.60mm ± .05
(.063 in ± .002)
50
1
25
.99mm ± .05
(.039 in ± .002)
2.44mm ± .07
(.096 in ± .003)
2 x 25.78mm ± .07(2 x 1.015 ± . 003)
.01mm ± .07(.039 in ± .003) .01mm ± .07(.039 in ± .003)
Optional Configuration
(See Note)
2.15mm ± .07
(.085 in x .003)
2 x 3.00mm ± .07
(2 x .118 in ± . 003)
36.40mm ± .15(1.433 in ± . 006)
2 x 12.00mm ± .10
(2 x 472 in ± .004)
3.30mm ± .10
(.130 in ± .004)
26
0.76mm ± .07(0.30 in ± .003)
4xR 0.5mm ± .1
(4xR.020 in ± .004)
41.66mm ± .13(1.640 in ±. 005)
42.80mm ± .10(1.685 in ± .004)
0.63mm ± .07(.025 in ± .003)
Note: The optional notched configuration was shown in the CF Specification Rev.1.0. In Specification
Rev. 1.2. The notch was removed for ease of tooling. This optional configuration can be used
but it is not recommended.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 1
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White Electronic Designs
WED7PxxxCFA70xxI25
ATTENTION FOR CARD USE
•
In the reset or power off mode, the information in all registers are cleared.
•
Note that the card insertion/removal should not be executed while host is active if the card is used in True IDE
mode.
•
After the hard reset, soft reset or power-on reset or ATA reset command is applied the card cannot be accessed
while READY pin is “low.” Flash card can’t be operated in this mode.
•
Before insertion VCC cannot be supplied to the card. After confirmation that CD1#, CD2# pins are set, VCC may
be supplied to the card.
•
OE# must be kept at the VCC level during power on reset in memory card mode and I/O card mode. OE must be
kept constantly at the GND level in True IDE mode.
•
Do not turn off the power or remove WED7PxxxCFA70xxI25 Series from the slot before read/write operation is
complete. Avoid using WED7PxxxCFA70xxI25 Series when the battery is low. Power shortage, power failure
and/or removal of WED7PxxxCFA70xxI25 Series from the slot before read/write operation is complete may
cause malfunction of WED7PxxxCFA70xxI25 Series, data loss and/or damage to data.
•
Routine performance of backing-up data (or taking back-up of data) is strongly recommended.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
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13
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED7PxxxCFA70xxI25
PART NUMBERING GUIDE
WED 7P xxx CFA 70 xx I 25
WEDC
Flash
Memory Size
Compact Flash
Industrial Flash
Housing:
00 = WEDC Logo
01 = Blank Housing
Enhanced Industrial Temp
Speed
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 1
14
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED7PxxxCFA70xxI25
Document Title
128MB to 1GB Industrial Compact Flash
Revision History
Rev #
History
Release Date
Status
Rev 0
Initial Release
March 2005
Final
Rev 1
1.1 Added "ED" to part marking
July 2005
Final
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 1
15
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com