MOTOROLA MC74HC195N

SEMICONDUCTOR TECHNICAL DATA
High–Performance Silicon–Gate CMOS
The MC74HC195 is identical in pinout to the LS195. The device inputs are
compatible with standard CMOS outputs, with pull up resistors, they are
compatible with LSTTL outputs.
This static shift register features parallel load, serial load (shift right), hold,
and reset modes of operation. These modes are tabulated in the Function
Table, and further explanation can be found in the Pin Description section.
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
ORDERING INFORMATION
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 150 FETs or 37.5 Equivalent Gates
MC74HCXXXN
PIN ASSIGNMENT
RESET
1
16
J
2
15
VCC
QA
K
3
14
QB
A
4
13
QC
LOGIC DIAGRAM
SERIAL DATA
INPUTS
2
J
15
3
K
14
4
A
PARALLEL
DATA
INPUTS
5
B
12
7
D
11
CLOCK
10
9
SERIAL SHIFT/
PARALLEL LOAD
B
5
12
QD
C
6
11
QD
D
7
10
CLOCK
GND
8
9
SERIAL SHIFT/
PARALLEL LOAD
QD
QD
PIN 16 = VCC
PIN 8 = GND
1
RESET
PARALLEL
DATA
OUTPUTS
QC
6
C
QA
QB
Plastic
FUNCTION TABLE
Inputs
Serial
Parallel
Outputs
Reset
Shift/
Load
Clock
J
K
A
B
C
D
QA
QB
QC
QD
QD
X
X
X
X
X
X
X
L
L
L
L
H
Reset
X
X
a
b
c
d
a
b
c
d
d
Parallel Load
X
X
X
X
X
X
L
L
H
H
H
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
QA0
L
H
QAn
QA0
QAn
QAn
QAn
QCn
QCn
QCn
QCn
QCn
QCn
QCn
QCn
L
X
H
L
H
H
H
H
H
H
H
H
H
H
L
No Change
H = high level (steady state)
L = low level (steady state)
X = don’t care
= transition from low to high level.
a, b, c, d = the level of steady–state input at inputs
A, B, C, or D, respectively.
QBn
QBn
QBn
QBn
Hold
Retain First Stage
Reset First Stage
Set First Stage
Toggle First Stage
Serial
Shift
QA0 = the level of QA before the indicated steady–state
input conditions were established.
QAn, QBn, QCn = the level of QA, QB, or QC,
respectively, before the most recent
transition
of the clock.
10/95
 Motorola, Inc. 1995
Operating Mode
3–1
REV 6
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MC74HC195
MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
V
Vin
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air
750
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Iin
TL
Plastic DIP†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
_C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP)
v
260
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 1)
0
VCC
V
– 55
+ 125
_C
0
0
0
1000
500
400
ns
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
85_C
125_C
Unit
VIH
Minimum High–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
Minimum High–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
VOH
Vin = VIH or VIL |Iout|
|Iout|
VOL
Maximum Low–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
Vin = VIH or VIL |Iout|
|Iout|
Iin
ICC
4.0 mA
5.2 mA
4.0 mA
5.2 mA
V
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0
8
80
160
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
3–2
High–Speed CMOS Logic Data
DL129 — Rev 6
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MC74HC195
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
VCC
V
– 55 to
25_C
85_C
125_C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 5)
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to any Q or QD
(Figures 1 and 5)
2.0
4.5
6.0
145
29
25
180
36
31
220
44
38
ns
tPLH,
tPHL
Maximum Propagation Delay, Reset to any Q or QD
(Figures 2 and 5)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Maximum Input Capacitance
—
10
10
10
pF
Symbol
Cin
Parameter
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Package)*
pF
95
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* Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit
VCC
V
– 55 to
25_C
85_C
125_C
tsu
Minimum Setup Time, A, B, C, D, J, or K to Clock
(Figure 3)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
tsu
Minimum Setup Time, Serial Shift/Parallel Load to Clock
(Figure 4)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
th
Minimum Hold Time, Clock to A, B, C, D, J, or K
(Figure 3)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
th
Minimum Hold Time, Clock to Serial Shift/Parallel Load
(Figure 4)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
tw
Minimum Pulse Width, Clock
(Figure 1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tw
Minimum Pulse Width, Reset
(Figure 2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
Symbol
trec
tr, tf
Parameter
Unit
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
High–Speed CMOS Logic Data
DL129 — Rev 6
3–3
MOTOROLA
MC74HC195
PIN DESCRIPTION
DATA INPUTS
J, K (Pins 2, 3)
A, B, C, D (Pins 4, 5, 6, 7)
Shift Control. With Serial Shift/Parallel Load high, J and K
control the mode of operation, as illustrated in the Function
Table.
Parallel data inputs.
OUTPUTS
J = L, K = H
With a positive transition of the Clock input, each bit is
shifted to the right (in the direction QA toward QD) one stage
and stage A maintains its previous state.
QA, QB, QC, QD, QD (Pins 15, 14, 13, 12, 11)
Parallel data outputs.
CONTROL INPUTS
J = H, K = L
With a positive transition of the Clock input, each bit is
shifted right (in the direction of QA toward QD) one stage and
the QA output is inverted.
Clock (Pin 10)
Clock input. The shift register is completely static, allowing
Clock rates down to DC in a continuous or intermittent mode.
Serial Shift/Parallel Load (Pin 9)
J=K=L
With a positive transition of the Clock input, each bit is
shifted right (in the direction QA toward QD) one stage and a
low is loaded into stage A.
Shift or load control. A low level applied to this pin allows
data to be loaded from the parallel inputs. Data is loaded with
the positive transition of the Clock input. A high level allows
data to be shifted in the manner dictated by the J and K control inputs.
J=K=H
With a positive transition of the Clock input, each bit is
shifted right (in the direction QA toward QD) one stage and a
high is loaded into stage A.
Reset (Pin 1)
A low level applied to this pin resets all stages and forces
all outputs low.
SWITCHING WAVEFORMS
tw
RESET
tr
GND
tf
tPHL
VCC
90%
50%
10%
tw
CLOCK
VCC
50%
Q
50%
GND
tPLH
1/fmax
tPLH
Q
tPHL
Q
50%
trec
90%
50%
10%
tTLH
50%
CLOCK
tTHL
GND
Figure 1.
Figure 2.
VALID
INPUT
A, B, C,
D, J, OR K
VALID
VCC
SERIAL SHIFT
PARALLEL LOAD
50%
GND
tsu
th
VCC
50%
GND
tsu
th
VCC
CLOCK
VCC
50%
CLOCK
50%
GND
GND
Figure 3.
MOTOROLA
VCC
Figure 4.
3–4
High–Speed CMOS Logic Data
DL129 — Rev 6
MC74HC195
TEST CIRCUIT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
* Includes all probe and jig capacitance
Figure 5.
TIMING DIAGRAM
CLOCK
RESET
SERIAL DATA
INPUTS
SERIAL SHIFT/
PARALLEL LOAD
PARALLEL
DATA
INPUTS
J
K
H
L
A
B
H
L
C
D
PARALLEL DATA
OUTPUTS
QA
QB
QC
QD
SERIAL SHIFT
RESET
High–Speed CMOS Logic Data
DL129 — Rev 6
SERIAL SHIFT
LOAD
3–5
MOTOROLA
MOTOROLA
SERIAL SHIFT/ 9
PARALLEL LOAD
3–6
RESET
CLOCK
1
10
11
QD
D
7
C
Q
R R
C
Q
R R
13
QC
B
5
C
Q
R R
C
D
PARALLEL DATA OUTPUTS
C
12
QD
D
C
6
D
C
PARALLEL
DATA
INPUTS
EXPANDED LOGIC DIAGRAM
14
QB
A
4
C
Q
R R
C
D
3
K
15
QA
VCC = PIN 16
GND = PIN 8
VCC
VCC
SERIAL DATA INPUTS
J
2
MC74HC195
High–Speed CMOS Logic Data
DL129 — Rev 6
MC74HC195
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A
–
16
9
1
8
B
F
C
L
S
–T
–
SEATING
PLANE
K
H
D 16 PL
0.25 (0.010)
M
M
J
G
T A
M
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MILLIMETERS
MIN
MAX
MIN
MAX
0.740 0.770 18.80 19.55
6.35
0.250 0.270
6.85
3.69
0.145 0.175
4.44
0.39
0.015 0.021
0.53
1.02
0.040 0.070
1.77
0.100 BSC
2.54 BSC
0.050 BSC
1.27 BSC
0.21
0.008 0.015
0.38
2.80
0.110 0.130
3.30
7.50
0.295 0.305
7.74
0°
0°
10°
10°
0.020 0.040
0.51
1.01
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High–Speed CMOS Logic Data
DL129 — Rev 6
◊
CODELINE
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*MC74HC195/D*
MC74HC195/D
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