SAMSUNG KM4132G271A

KM4132G271A
CMOS SGRAM
128K x 32Bit x 2 Banks Synchronous Graphic RAM
FEATURES
¡Ü
¡Ü
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¡Ü
¡Ü
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¡Ü
¡Ü
¡Ü
GENERAL DESCRIPTION
The KM4132G271A is 8,388,608 bits synchronous high data
rate Dynamic RAM organized as 2 x 131,072 words by 32 bits,
fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length, and programmable latencies allows the same
device to be useful for a variety of high bandwidth, high performance memory system applications.
Write per bit and 8 columns block write improves performance in
graphics systems.
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Dual bank / Pulse RAS
MRS cycle with address key programs
-. CAS Latency (2, 3)
-. Burst Length (1, 2, 4, 8 & full page)
-. Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Burst Read Single-bit Write operation
DQM 0-3 for byte masking
Auto & self refresh
16ms refresh period (1K cycle)
100 Pin QFP
ORDERING INFORMATION
Graphics Features
¡Ü
¡Ü
¡Ü
Cycle
time
Clock
f
Access
time@CL=3
KM4132G271A-8
8ns
125MHz
7.0ns
KM4132G271A-10
10ns
100MHz
7.0ns
KM4132G271A-12
12ns
83MHz
9.0ns
Part NO.
SMRS cycle.
-. Load mask register
-. Load color register
Write Per Bit(Old Mask)
Block Write(8 Columns)
MASK
REGISTER
DQMi
MASK
BLOCK
WRITE
CONTROL
LOGIC
WRITE
CONTROL
MUX
COLOR
REGISTER
LOGIC
INPUT BUFFER
FUNCTIONAL BLOCK DIAGRAM
CLK
COLUMN
MASK
CKE
DQMi
DQi
(i=0~31)
SENSE
AMPLIFIER
COLUMN
DECORDER
128Kx32
CELL
ARRAY
DSF
128Kx32
CELL
ARRAY
OUTPUT BUFFER
WE
LATENCY &
BURST LENGTH
CAS
PROGRAMING
REGISTER
RAS
TIMING REGISTER
CS
ROW DECORDER
BANK SELECTION
DQMi
SERIAL
COUNTER
COLUMN ADDRESS
BUFFER
ROW ADDRESS
BUFFER
REFRESH
COUNTER
ADDRESS REGISTER
CLOCK ADDRESS(A 0~A9)
Rev.0 (August 1997)
DQ2
VSSQ
DQ1
DQ0
VDD
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
VSS
DQ31
DQ30
VSSQ
DQ29
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
DQ16
DQ17
VSSQ
DQ18
DQ19
VDDQ
VDD
VSS
DQ20
DQ21
VSSQ
DQ22
DQ23
VDDQ
DQM0
DQM2
WE
CAS
RAS
CS
BA(A9)
N.C
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
DQ16
DQ17
VSSQ
DQ18
DQ19
VDDQ
VDD
VSS
DQ20
DQ21
VSSQ
DQ22
DQ23
VDDQ
DQM0
DQM2
WE
CAS
RAS
CS
BA(A9)
N.C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQ29
VSSQ
DQ30
DQ31
VSS
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
VDD
DQ0
DQ1
VSSQ
DQ2
DQ28
VDDQ
DQ27
DQ26
VSSQ
DQ25
DQ24
VDDQ
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
VSS
VDD
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
N.C
DQM3
DQM1
CLK
CKE
DSF
N.C
A8
DQ28
VDDQ
DQ27
DQ26
VSSQ
DQ25
DQ24
VDDQ
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
VSS
VDD
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
N.C
DQM3
DQM1
CLK
CKE
DSF
N.C
A8
KM4132G271A
CMOS SGRAM
PIN CONFIGURATION (TOP VIEW)
Forward Type
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
100 Pin QFP
Forward Type
20 x 14 §±
0.65§® pin Pitch
Reverse Type
100 Pin QFP
Reverse Type
20 x 14 §±
0.65§® pin Pitch
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
A7
A6
A5
A4
VSS
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
VDD
A3
A2
A1
A0
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
A0
A1
A2
A3
VDD
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
VSS
A4
A5
A6
A7
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
PIN CONFIGURATION DESCRIPTION
PIN
NAME
INPUT FUNCTION
CLK
System Clock
Active on the positive going edge to sample all inputs.
CS
Chip Select
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQMi
CKE
Clock Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one clock +tSS prior to new command.
Disable input buffers for power down in standby.
A0 ~ A8
Address
Row / Column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA8, Column address : CA0 ~ CA7
A9(BA)
Bank Select Address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column Address Strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write Enable
Enables write operation and Row precharge.
DQMi
Data Input/Output Mask
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.(Byte Masking)
DQi
Data Input/Output
Data inputs/outputs are multiplexed on the same pins.
DSF
Define Special Function
Enables write per bit, block write and special mode register set.
VDD/VSS
Power Supply/Ground
VDDQ/VSSQ
Data Output Power/Ground
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
ABSOLUTE MAXIMUM RATINGS(Voltage referenced to VSS)
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
VIN, VOUT
-1.0 ~ 4.6
V
Voltage on VDD supply relative to Vss
VDD, VDDQ
-1.0 ~ 4.6
V
TSTG
-55 ~ +150
¡É
Power dissipation
PD
1
W
Short circuit current
IOS
50
mA
Storage temperature
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V)
Parameter
Symbol
Min
Typ
Max
Unit
VDD, VDDQ
3.0
3.3
3.6
V
Input high voltage
VIH
2.0
3.0
VDD+0.3
V
Input low voltage
VIL
-0.3
0
0.8
V
Note 1
Output high voltage
VOH
2.4
-
-
V
IOH = -2mA
Output low voltage
VOL
-
-
0.4
V
IOL = 2mA
Input leakage current
IIL
-5
-
5
§Ë
Note 2
Output leakage current
IOL
-5
-
5
§Ë
Note 3
Supply voltage
Output Loading Condition
Note
see figure 1
Note : 1. VIL (min) = -1.5V AC(pulse width ¡Â 5ns).
2. Any input 0V ¡Â VIN ¡Â VDD + 0.3V, all other pins are not under test = 0V.
3. Dout is disabled, 0V¡Â VOUT ¡Â VDD.
CAPACITANCE
(VDD/VDDQ = 3.3V, TA = 25¡É, f = 1MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0 ~ A9)
CIN1
-
4
pF
Input capacitance
(CLK, CKE, CS, RAS, CAS, WE, DSF & DQM)
CIN2
-
4
pF
Data input/output capacitance (DQ0 ~ DQ31)
COUT
-
5
pF
Symbol
Value
Unit
Decoupling Capacitance between VDD and VSS
CDC1
0.1 + 0.01
uF
Decoupling Capacitance between VDDQ and VSSQ
CDC2
0.1 + 0.01
uF
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Parameter
Note : 1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70¡É VIH(min)/VIL(max)=2.0V/0.8V)
Parameter
Operating Current
(One Bank Active)
Symbol
ICC1
Test Condition
Speed
CAS
Latency
-8
-10
-12
3
180
160
140
2
160
140
120
Burst Length =1
tRC¡ÃtRC(min), tCC¡ÃtCC(min)
IOL = 0 mA
ICC2P
CKE¡ÂVIL(max), tCC = 15ns
2
2
2
ICC2PS
CKE¡ÂVIL(max), CLK¡ÂVIL(max), tCC = ¡Ä
2
2
2
ICC2N
CKE¡ÃVIH(min), CS¡ÃVIH(min), tCC = 15ns
Input signals are changed one time during 30ns
45
45
45
ICC2NS
CKE¡ÃVIH(min), CLK¡ÂVIL(max), tCC = ¡Ä
Input signals are stable
20
20
20
Active Standby Current
in power-down mode
ICC3P
CKE¡ÂVIL(max), tCC = 15ns
4
4
4
ICC3PS
CKE¡ÂVIL(max), CLK¡ÂVIL(max), tCC = ¡Ä
3.5
3.5
3.5
Active Standby Current
in non power-down mode
(One Bank Active)
ICC3N
CKE¡ÃVIH(min), CS¡ÃVIH(min), tCC = 15ns
Input signals are changed one time during 30ns
55
55
55
ICC3NS
CKE¡ÃVIH(min), CLK¡ÂVIL(max), tCC = ¡Ä
Input signals are stable
Operating Current
(Burst Mode)
ICC4
IOL = 0 mA, Page Burst
All bank Activated, tCCD = tCCD(min)
Refresh Current
ICC5
Precharge Standby Current in power-down mode
Precharge Standby Current
in non power-down mode
tRC¡ÃtRC(min)
Self Refresh Current
ICC6
CKE¡Â0.2V
Operating Current
(One Bank Block Write)
ICC7
tCC¡ÃtCC(min), IOL=0mA, tBWC(min)
Unit
Note
mA
1
mA
mA
mA
mA
35
35
35
3
200
180
160
2
180
160
140
3
140
120
100
2
130
110
90
1
1
1
mA
170
150
130
mA
mA
1, 2
mA
3
4
Note : 1. Measured with outputs open.
2. Assumes minimum column address update cycle tCCD(min).
3. Refresh period is 16ms.
4. Assumes minimum column address update cycle tBWC(min).
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
AC OPERATING TEST CONDITIONS (VDD = 3.3V¡¾0.3V, TA = 0 to 70¡É)
Parameter
Value
AC input levels
VIH/VIL = 2.4V / 0.4V
Input timing measurement reference level
1.4V
Input rise and fall time(See note 3)
tR/tF=1ns/ 1ns
Output timing measurement reference level
1.4V
Output load condition
See Fig. 2
VREF=1.4V
3.3V
1200§Ù
50§Ù
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
Output
Z0=50§Ù
30pF
870§Ù
30pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
-8
Symbol
Min
CLK cycle time
CAS Latency=3
tCC
CAS Latency=2
CLK to valid
output delay
Output data
hold time
CAS Latency=3
Max
1000
12
tSAC
CAS Latency=2
CAS Latency=3
8
-10
tOH
CAS Latency=2
Min
10
-12
Max
1000
13
Min
12
Unit
Note
ns
1
ns
1, 2
Max
1000
15
-
7
-
7
-
9
-
10
-
11
-
12
3
3
3
ns
3
3
3
ns
2
CLK high pulse width
tCH
3
3.5
4
ns
3
CLK low pulse width
tCL
3
3.5
4
ns
3
Input setup time
tSS
2.5
3
3
ns
3
Input hold time
tSH
1
1
1.5
ns
3
CLK to output in Low-Z
tSLZ
1
1
1
ns
2
CLK to output
in Hi-Z
CAS latency=3
CAS latency=2
tSHZ
-
7
-
7
-
9
-
10
-
11
-
12
ns
* All AC parameters are measured from half to half.
Note : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Version
Symbol
-8
-10
-12
Unit
Note
Row active to row active delay
tRRD(min)
16
20
24
ns
1
RAS to CAS delay
tRCD(min)
16
20
24
ns
1
Row precharge time
tRP(min)
24
26
30
ns
1
tRAS(min)
48
50
60
ns
1
Row active time
tRAS(max)
100
Row cycle time
tRC(min)
ns
1
Last data in to new col. address delay
tCDL(min)
1
CLK
2
Last data in to row precharge
tRDL(min)
1
CLK
2
Block write data-in to PRE command delay
tBPL(min)
16
20
24
ns
Block write data-in to Active(REF)
command period(Auto precharge)
tBAL(min)
40
46
54
ns
Last data in to burst stop
tBDL(min)
1
CLK
2
Col. address to col. address delay
tCCD(min)
1
CLK
3
Block write cycle time
tBWC(min)
ns
1, 4
CLK
5
Number of valid output data
80
16
80
us
20
CAS Latency=3
2
CAS Latency=2
1
90
24
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change except block write cycle.
4. This parameter means minimum CAS to CAS delay at block write cycle only.
5. In case of row precharge interrupt, auto precharge and read burst stop.
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE
KM4132G271A-8
(Unit : number of clock)
CAS
Latency
tRC
tRAS
tRP
tRRD
tRCD
tCCD
tCDL
tRDL
tBWC
80ns
48ns
24ns
16ns
16ns
8ns
8ns
8ns
16ns
125MHz (8.0ns)
3
10
6
3
2
2
1
1
1
2
100MHz (10.0ns)
3
8
5
3
2
2
1
1
1
2
83MHz (12.0ns)
2
7
4
2
2
2
1
1
1
2
75MHz (13.4ns)
2
6
4
2
2
2
1
1
1
2
66MHz (15.0ns)
2
6
4
2
2
2
1
1
1
2
50MHz(20ns)
2
4
3
2
1
1
1
1
1
1
Frequency
KM4132G271A-10
(Unit : number of clock)
CAS
Latency
tRC
tRAS
tRP
tRRD
tRCD
tCCD
tCDL
tRDL
tBWC
80ns
50ns
26ns
20ns
20ns
10ns
10ns
10ns
20ns
100MHz (10.0ns)
3
8
5
3
2
2
1
1
1
2
83MHz (12.0ns)
3
7
5
3
2
2
1
1
1
2
71MHz (14.0ns)
2
6
4
2
2
2
1
1
1
2
66MHz (15.0ns)
2
6
4
2
2
2
1
1
1
2
50MHz (20.0ns)
2
4
3
2
1
1
1
1
1
1
40MHz(25ns)
2
4
2
2
1
1
1
1
1
1
Frequency
KM4132G271A-12
(Unit : number of clock)
CAS
Latency
tRC
tRAS
tRP
tRRD
tRCD
tCCD
tCDL
tRDL
tBWC
90ns
60ns
30ns
24ns
24ns
12ns
12ns
12ns
24ns
83MHz (12.0ns)
3
8
5
3
2
2
1
1
1
2
66MHz (15.0ns)
2
6
4
2
2
2
1
1
1
2
55MHz (18.2ns)
2
5
4
2
2
2
1
1
1
2
50MHz (20.0ns)
2
5
3
2
2
2
1
1
1
2
40MHz (25.0ns)
2
4
3
2
1
1
1
1
1
1
33MHz(30.0ns)
2
3
2
1
1
1
1
1
1
1
Frequency
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
SIMPLIFIED TRUTH TABLE
COMMAND
Register
CKEn-1 CKEn
Mode Register Set
H
X
CS
RAS
CAS
WE
L
L
L
L
Special Mode Register Set
Refresh
Auto Refresh
H
Bank Active
& Row Addr.
Exit
Write Per Bit Disable
X
L
H
OP CODE
L
L
L
H
L
H
X
Write &
Auto Precharge Disable
Column Address
Auto Precharge Enable
H
Block Write &
Column Addr.
H
X
X
3
L
H
H
H
H
X
X
X
L
L
H
H
X
X
3
L
X
V
L
H
L
H
L
X
L
H
L
L
L
X
L
H
L
L
H
X
V
Entry
H
X
L
H
H
L
L
X
H
X
L
L
H
L
L
X
H
L
Exit
L
H
Entry
H
L
Precharge Power Down Mode
Exit
L
Column
Address
V
L
Column
Address
V
L
Column
Address
H
Both Banks
Clock Suspend or
Active Power Down
Row Address
L
DQM
H
No Operation Command
H
H
L
H
H
H
H
X
X
X
X
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
V
H
X
X
X
X
X
L
H
H
H
H
X
X
X
X
V
L
X
H
4
4, 6
4, 5
4,5,6,9
4, 5
4,5,6,9
7
X
X
X
X
X
X
X
X
X
X
4, 5
4,5,9
Auto Precharge Enable
Bank Selection
3
X
H
X
1, 2
3
X
H
X
Note
1,2,7
H
H
Burst Stop
A7~ A0
L
Read &
Auto Precharge Disable
Column Address
Auto Precharge Enable
Precharge
H
Write Per Bit Enable
Auto Precharge Disable
L
A8
H
Entry
Self
Refresh
DSF DQM A9
X
X
V
X
X
X
8
(V=Valid, X=Don't Care, H=Logic High, L=Logic Low)
Note : 1. OP Code : Operand Code
A0 ~ A9 : Program keys. (@MRS)
A5, A6 : LMR or LCR select. (@SMRS)
Color register exists only one per DQi which both banks share.
So dose Mask Register.
Color or mask is loaded into chip through DQ pin.
2. MRS can be issued only at both banks precharge state.
SMRS can be issued only if DQ's are idle.
A new command can be issued at the next clock of MRS/SMRS.
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
SIMPLIFIED TRUTH TABLE
3. Auto refresh functions as same as CBR refresh of DRAM.
The automatical precharge without Row precharge command is meant by "Auto".
Auto/Self refresh can be issued only at both precharge state.
4. A9 : Bank select address.
If "Low" at read, (block) write, Row active and precharge, bank A is selected.
If "High" at read, (block) write, Row active and precharge, bank B is selected.
If A8 is "High" at Row precharge, A9 is ignored and both banks are selected.
5. It is determined at Row active cycle.
whether Normal/Block write operates in write per bit mode or not.
For A bank write, at A bank Row active, for B bank write, at B bank Row active.
Terminology : Write per bit =I/O mask
(Block) Write with write per bit mode=Masked(Block) Write
6. During burst read or write with auto precharge, new read/(block) write command cannot be issued.
Another bank read/(block) write command can be issued at tRP after the end of burst.
7. Burst stop command is valid only at full page burst length.
8. DQM sampled at positive going edge of a CLK.
masks the data-in at the very CLK(Write DQM latency is 0)
but makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)
9. Graphic features added to SDRAM's original features.
If DSF is tied to low, graphic functions are disabled and chip operates as a 8M SDRAM with 32 DQ's.
SGRAM vs SDRAM
SDRAM Function
DSF
SGRAM
Function
MRS
L
MRS
Bank Active
Write
H
L
H
L
H
SMRS
Bank Active
with
Write per bit
Disable
Bank Active
with
Write per bit
Enable
Normal
Write
Block
Write
If DSF is low, SGRAM functionality is identical to SDRAM functionality.
SGRAM can be used as an unified memory by the appropriate DSF control
--> SGRAM=Graphic Memory + Main Memory
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address
Function
A9
A8
W.B.L
A7
A6
A5
TM
A4
CAS Latency
A3
A2
BT
A1
A0
Burst Length
(Note 1)
Test Mode
CAS Latency
Burst Type
Burst Length
A8
A7
Type
A6
A5
A4
Latency
A3
Type
A2
A1
A0
BT=0
BT=1
0
0
Mode Register Set
0
0
0
Reserved
0
Sequential
0
0
0
1
Reserved
0
1
0
0
1
-
1
Interleave
0
0
1
2
Reserved
1
0
Vendor
Use
Only
0
1
0
2
0
1
0
4
4
1
0
1
1
3
0
1
1
8
8
Write Burst Length
1
0
0
Reserved
1
0
0
Reserved
Reserved
1
A9
Length
1
0
1
Reserved
1
0
1
Reserved
Reserved
0
Burst
1
1
0
Reserved
1
1
0
Reserved
Reserved
1
Single Bit
1
1
1
Reserved
1
1
1
256(Full)
Reserved
(Note 2)
Special Mode Register Programmed with SMRS
Address
Function
A9
A8
A7
X
A6
A5
LC
LM
Load Color
A4
A3
A2
A1
A0
X
Load Mask
A6
Function
A5
Function
0
Disable
0
Disable
1
Enable
1
Enable
(Note 3)
POWER UP SEQUENCE
1. Apply power and start clock, Attempt to maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200§Á.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 may be changed.
The device is now ready for normal operation.
Note : 1. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.
2. The full column burst(256bit) is available only at Sequential mode of burst type.
3. If LC and LM both high(1), data of mask and color register will be unknown.
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
BURST SEQUENCE (BURST LENGTH = 4)
Initial address
Sequential
Interleave
A1
A0
0
0
0
1
2
3
0
1
2
3
0
1
1
2
3
0
1
0
3
2
1
0
2
3
0
1
2
3
0
1
1
1
3
0
1
2
3
2
1
0
BURST SEQUENCE (BURST LENGTH = 8)
Initial address
Sequential
Interleave
A2
A1
A0
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
0
1
1
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
1
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
1
0
1
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
1
1
0
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
1
1
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
PIXEL to DQ MAPPING(at BLOCK WRITE)
Column address
3 Byte
2 Byte
1 Byte
0 Byte
A2
A1
A0
I/O31 - I/O24
I/O23 - I/O16
I/O15 - I/O8
I/O7 - I/O0
0
0
0
DQ24
DQ16
DQ8
DQ0
0
0
1
DQ25
DQ17
DQ9
DQ1
0
1
0
DQ26
DQ18
DQ10
DQ2
0
1
1
DQ27
DQ19
DQ11
DQ3
1
0
0
DQ28
DQ20
DQ12
DQ4
1
0
1
DQ29
DQ21
DQ13
DQ5
1
1
0
DQ30
DQ22
DQ14
DQ6
1
1
1
DQ31
DQ23
DQ15
DQ7
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
DEVICE OPERATIONS
CLOCK (CLK)
POWER-UP
The clock input is used as the reference for all SGRAM operations. All operations are synchronized to the positive going edge
of the clock. The clock transitions must be monotonic between
VIL and VIH. During operation with CKE high all inputs are
assumed to be in valid state (low or high) for the duration of setup and hold time around positive edge of the clock for proper
functionality and ICC specifications.
The following sequence is recommended for POWER UP
1. Power must be applied to either CKE and DQM inputs to pull
them high and other pins are NOP condition at the inputs
before or along with VDD(and VDDQ) supply.
The clock signal must also be asserted at the same time.
2. After VDD reaches the desired voltage, a minimum pause of
200 microseconds is required with inputs in NOP condition.
3. Both banks must be precharged now.
4. Perform a minimum of 2 Auto refresh cycles to stabilize the
internal circuitry.
5. Perform a MODE REGISTER SET cycle to program the CAS
latency, burst length and burst type as the default value of
mode register is undefined.
At the end of one clock cycle from the mode register set
cycle, the device is ready for operation.
When the above sequence is used for Power-up, all the outputs will be in high impedance state. The high impedance of
outputs is not guaranteed in any other power-up sequence.
cf.) Sequence of 4 & 5 may be changed.
CLOCK ENABLE (CKE)
The clock enable(CKE) gates the clock onto SGRAM. If CKE
goes low synchronously with clock (set-up and hold time same
as other inputs), the internal clock is suspended from the next
clock cycle and the state of output and burst address is frozen
as long as the CKE remains low. All other inputs are ignored
from the next clock cycle after CKE goes low. When both banks
are in the idle state and CKE goes low synchronously with clock,
the SGRAM enters the power down mode from the next clock
cycle. The SGRAM remains in the power down mode ignoring
the other inputs as long as CKE remains low. The power down
exit is synchronous as the internal clock is suspended. When
CKE goes high at least "tSS + 1CLOCK" before the high going
edge of the clock, then the SGRAM becomes active from the
same clock edge accepting all the input commands.
MODE REGISTER SET (MRS)
The mode register stores the data for controlling the various
BANK SELECT (A9)
This SGRAM is organized as two independent banks of 131,072
words x 32 bits memory arrays. The A9 inputs is latched at the
time of assertion of RAS and CAS to select the bank to be used
for the operation. When A9 is asserted low, bank A is selected.
When A9 is asserted high, bank B is selected. The bank select
A9 is latched at bank activate, read, write mode register set and
precharge operations.
ADDRESS INPUT (A0 ~ A8)
The 17 address bits required to decode the 131,072 word locations are multiplexed into 9 address input pins(A0~A8). The 9 bit
row address is latched along with RAS and A9 during bank activate command. The 8 bit column address is latched along with
CAS, WE and A9 during read or write command.
operating modes of SGRAM. It programs the CAS latency,
addressing mode, burst length, test mode and various vendor
specific options to make SGRAM useful for variety of different
applications. The default value of the mode register is not
defined, therefore the mode register must be written after power
up to operate the SGRAM. The mode register is written by
asserting low on CS, RAS, CAS, WE and DSF (The SGRAM
should be in active mode with CKE already high prior to writing
the mode register). The state of address pins A0 ~ A8 and A9 in
the same cycle as CS, RAS, CAS, WE and DSF going low is the
data written in the mode register. One clock cycle is required to
complete the write in the mode register. The mode register contents can be changed using the same command and clock cycle
requirements during operation as long as both banks are in the
NOP and DEVICE DESELECT
idle state. The mode register is divided into various fields
When RAS, CAS and WE are high, the SGRAM performs no
operation (NOP). NOP does not initiate any new operation, but
is needed to complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc.
The device deselect is also a NOP and is entered by asserting
CS high. CS high disables the command decoder so that RAS,
CAS, WE, DSF and all the address inputs are ignored.
depending on functionality. The burst length field uses A0 ~ A2,
burst type uses A3, addressing mode uses A4 ~ A6, A7 ~ A8 are
used for vendor specific options or test mode. And the write
burst length is programmed using A9. A7 ~ A8 must be set to low
for normal SGRAM operation. Refer to table for specific codes
for various burst length, addressing modes and CAS latencies.
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
DEVICE OPERATIONS
BANK ACTIVATE
cycles in adjacent addresses depending on burst length and
The bank activate command is used to select a random row in
an idle bank. By asserting low on RAS and CS with desired row
and bank addresses, a row access is initiated. The read or write
operation can occur after a time delay of tRCD(min) from the time
of bank activation. tRCD(min) is an internal timing parameter of
SGRAM, therefore it is dependent on operating clock frequency.
The minimum number of clock cycles required between bank
activate and read or write command should be calculated by
dividing tRCD(min) with cycle time of the clock and then rounding
off the result to the next higher integer. The SGRAM has two
internal banks on the same chip and shares part of the internal
circuitry to reduce chip area, therefore it restricts the activation
of both banks immediately. Also the noise generated during
sensing of each bank of SGRAM is high requiring some time for
power supplies to recover before the other bank can be sensed
reliably. tRRD(min) specifies the minimum time required between
activating different banks. The number of clock cycles required
between different bank activation must be calculated similar to
tRCD specification. The minimum time required for the bank to be
active to initiate sensing and restoring the complete row of
dynamic cells is determined by tRAS(min) specification before a
precharge command to that active bank can be asserted. The
maximum time any bank can be in the active state is determined
by tRAS(max). The number of cycles for both tRAS(min) and
tRAS(max) can be calculated similar to tRCD specification.
burst sequence. By asserting low on CS, CAS and WE with valid
column address, a write burst is initiated. The data inputs are
provided for the initial address in the same clock cycle as the
burst write command. The input buffer is deselected at the end
of the burst length, even though the internal writing may not
have been completed yet. The writing can not complete to burst
length. The burst write can be terminated by issuing a burst
read and DQM for blocking data inputs or burst write in the same
or the other active bank. The burst stop command is valid only at
full page burst length where the writing continues at the end of
burst and the burst is wrap around. The write burst can also be
terminated by using DQM for blocking data and precharging the
bank " tRDL" after the last data input to be written into the active
row. See DQM OPERATION also.
BURST READ
The burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. The
burst read command is issued by asserting low on CS and CAS
with WE being high on the positive edge of the clock. The bank
must be active for at least tRCD(min) before the burst read command is issued. The first output appears CAS latency number of
clock cycles after the issue of burst read command. The burst
length, burst sequence and latency from the burst read command is determined by the mode register which is already programmed. The burst read can be initiated on any column
address of the active row. The address wraps around if the initial
address does not start from a boundary such that number of outputs from each I/O are equal to the burst length programmed in
the mode register. The output goes into high-impedance at the
end of the burst, unless a new burst read was initiated to keep
the data output gapless. The burst read can be terminated by
issuing another burst read or burst write in the same bank or the
other active bank or a precharge command to the same bank.
The burst stop command is valid only at full page burst length
where the output dose not go into high impedance at the end of
burst and the burst is wrap around..
BURST WRITE
The burst write command is similar to burst read command, and
is used to write data into the SGRAM on consecutive clock
DQM OPERATION
The DQM is used to mask input and output operations. It works
similar to OE during read operation and inhibits writing during
write operation. The read latency is two cycles from DQM and
zero cycle for write, which means DQM masking occurs two
cycles later in the read cycle and occurs in the same cycle during write cycle. DQM operation is synchronous with the clock,
therefore the masking occurs for a complete cycle. The DQM
signal is important during burst interrupts of write with read or
precharge in the SGRAM. Due to asynchronous nature of the
internal write, the DQM operation is critical to avoid unwanted or
incomplete writes when the complete burst write is not required.
DQM is also used for device selection, byte selection and bus
control in a memory system. DQM0 controls DQ0 to DQ7,
DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23,
DQM3 controls DQ24 to DQ31. DQM masks the DQ's by a byte
regardless that the corresponding DQ's are in a state of WPB
masking or Pixel masking. Please refer to DQM timing diagram
also.
PRECHARGE
The precharge operation is performed on an active bank by
asserting low on CS, RAS, WE and A8 with valid A9 of the bank
to be precharged. The precharge command can be asserted
anytime after tRAS(min) is satisfied from the bank activate command in the desired bank. "tRP" is defined as the minimum time
required to precharge a bank. The minimum number of clock
cycles required to complete row precharge is calculated by
dividing "tRP" with clock cycle time and rounding up to the next
higher integer. Care should be taken to make sure that burst
write is completed or DQM is used to inhibit writing before precharge command is asserted. The maximum time any bank can
be active is specified by tRAS(max). Therefore, each bank has to
be precharged within tRAS(max) from the bank activate command. At the end of precharge, the bank enters the idle state
and is ready to be activated again.
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
DEVICE OPERATIONS (Continued)
Entry to Power Down, Auto refresh, Self refresh and Mode register Set etc. is possible only when both banks are in idle state.
AUTO PRECHARGE
The precharge operation can also be performed by using auto
precharge. The SGRAM internally generates the timing to satisfy
tRAS(min) and "tRP" for the programmed burst length and CAS
latency. The auto precharge command is issued at the same
time as burst read or burst write by asserting high on A8. If burst
read or burst write command is issued with low on A8, the bank
is left active until a new command is asserted. Once auto precharge command is given, no new commands are possible to
that particular bank until the bank achieves idle state.
BOTH BANKS PRECHARGE
Both banks can be precharged at the same time by using Precharge all command. Asserting low on CS, RAS, and WE with
high on A8 after both banks have satisfied tRAS(min) requirement, performs precharge on both banks. At the end of tRP after
performing precharge all, both banks are in idle state.
AUTO REFRESH
The storage cells of SGRAM need to be refreshed every 16ms
SELF REFRESH
The self refresh is another refresh mode available in the
SGRAM. The self refresh is the preferred refresh mode for data
retention and low power operation of SGRAM. In self refresh
mode, the SGRAM disables the internal clock and all the input
buffers except CKE. The refresh addressing and timing is internally generated to reduce power consumption.
The self refresh mode is entered from all banks idle state by
asserting low on CS, RAS, CAS and CKE with high on WE.
Once the self refresh mode is entered, only CKE state being low
matters, all the other inputs including clock are ignored to remain
in the self refresh.
The self refresh is exited by restarting the external clock and
then asserting high on CKE. This must be followed by NOP's
for a minimum time of "tRC" before the SGRAM reaches idle
state to begin normal operation. If the system uses burst auto
refresh during normal operation, it is recommended to use burst
1024 auto refresh cycles immediately after exiting self refresh.
DEFINE SPECIAL FUNCTION(DSF)
The DSF controls the graphic applications of SGRAM. If DSF is
tied to low, SGRAM functions as 128K x 32 x2 Bank SDRAM.
SGRAM can be used as an unified memory by the appropriate
DSF command. All the graphic function mode can be entered
only by setting DSF high when issuing commands which otherwise would be normal SDRAM commands.
to maintain data. An auto refresh cycle accomplishes refresh of
a single row of storage cells. The internal counter increments
automatically on every auto refresh cycle to refresh all the rows.
An auto refresh command is issued by asserting low on CS,RAS
SDRAM functions such as RAS Active, Write, and WCBR
change to SGRAM functions such as RAS Active with WPB,
Block Write and SWCBR respectively. See the sessions below
for the graphic functions that DSF controls.
and CAS with high on CKE and WE. The auto refresh command
can only be asserted with both banks being in idle state and the
SPECIAL MODE REGISTER SET(SMRS)
device is not in power down mode (CKE is high in the previous
There are two kinds of special mode registers in SGRAM.One is
color register and the other is mask register. Those usage will be
explained at "WRITE PER BIT" and "BLOCK WRITE" session.
When A5 and DSF goes high in the same cycle as CS, RAS,
CAS and WE going low, load mask register(LMR) process is
executed and the mask registers are filled with the masks for
associated DQ's through DQ pins. And when A6 and DSF goes
high in the same cycle as CS, RAS, CAS and WE going low,
load color register(LCR) process is executed and the color register is filled with color data for associated DQ's through the DQ
pins. If both A5 and A6 are high at SMRS, data of mask and color
cycle is required to complete the write in the mask register and
the color register at LMR and LCR respectively. The next clock
of LMR or LCR, a new commands can be issued. SMRS, compared with MRS, can be issued at the active state under the condition that DQ's are idle. As in write operation, SMRS accepts
the data needed through DQ pins. Therefore it should be
attended not to induce bus contention. The more detailed materials can be obtained by referring corresponding timing diagram.
cycle). The time required to complete the auto refresh operation
is specified by "tRC(min)". The minimum number of clock cycles
required can be calculated by driving "tRC" with clock cycle time
and them rounding up to the next higher integer. The auto
refresh command must be followed by NOP's until the auto
refresh operation is completed. Both banks will be in the idle
state at the end of auto refresh operation. The auto refresh is the
preferred refresh mode when the SGRAM is being used for normal data transactions. The auto refresh cycle can be performed
once in 15.6§Á or a burst of 1024 auto refresh cycles once in
16ms.
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
DEVICE OPERATIONS (Continued)
WRITE PER BIT
Timing Diagram to lllustrate tBWC
Write per bit(i.e. I/O mask mode) for SGRAM is a function that
selectively masks bits of data being written to the devices. The
mask is stored in an internal register and applied to each bit of
data written when enabled. Bank active command with
DSF=High enabled write per bit for associated bank. Bank active
command with DSF=Low disables write per bit for the associated bank. The mask used for write per bit operations is stored
in the mask register accessed by SWCBR(Special Mode Register Set Command). When a mask bit=1, the associated data bit
is written when a write command is executed and write per bit
has been enabled for the bank being written. When a mask
bit=0, the associated data bit is unaltered when a write command is executed and the write per bit has been enabled for the
bank being written. No additional timing conditions are required
for write per bit operations. Write per bit writes can be either single write, burst writes or block writes. DQM masking is the same
for write per bit and non-WPB write.
1. 1 CLK Cycle Block Write(tBWC¡ÂtCC)
0
1
CLOCK
HIGH
CKE
CS
RAS
CAS
WE
DSF
BLOCK WRITE
Block write is a feature allowing the simultaneous writing of
consecutive 8 columns of data within a RAM device during a single access cycle. During block write the data to be written comes
from an internal "color" register and DQ I/O pins are used for
independent column selection. The block of column to be written
is aligned on 8 column boundaries and is defined by the column
address with the 3 LSB's ignored. Write command with DSF=1
enables block write for the associated bank. A write command
with DSF=0 enables normal write for the associated bank. The
block width is 8 column where column="n" bits for by "n" part.
The color register is the same width as the data port of the
chip.It is written via a SWCBR where data present on the DQ pin
is to be coupled into the internal color register. The color register
provides the data masked by the DQ column select, WPB
mask(If enabled), and DQM byte mask. Column data masking(Pixel masking) is provided on an individual column basis for
each byte of data. The column mask is driven on the DQ pins
during a block write command. The DQ column mask function is
segmented on a per bit basis(i.e. DQ[0:7] provides the column
mask for data bits[0:7], DQ[8:15] provides the column mask for
data bits[8:15], DQ0 masks column[0] for data bits[0:7], DQ9
masks column [1] for data bits [8:15], etc). Block writes are
always non-burst, independent of the burst length that has been
programmed into the mode register. Back to back block writes
are allowed provided that the specified block write cycle
time(tBWC) is satisfied. If write per bit was enabled by the bank
active command with DSF=1, then write per bit masking of the
color register data is enabled.
If write per bit was disabled by a bank active command with
DSF=0, the write per bit masking of the color register data is disabled. DQM masking provides independent data byte masking
during block write exactly the same as it does during normal
write operations, except that the control is extended to the consecutive 8 columns of the block write.
2
1 CLK BW
2. 2 CLK Cycle Block Write(tBWC>tCC)
0
1
2
3
4
CLOCK
CKE
HIGH
CS
RAS
CAS
WE
DSF
2 CLK BW
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
SUMMARY OF 1M Byte SGRAM BASIC FEATURES AND BENEFITS
Features
128K x 32 x 2 SGRAM
Interface
Synchronous
Bank
Pseudo-infinite row length by on-chip interleaving operation.
Hidden row activation and precharge.
2 ea
Page Depth / 1 Row
Total Page Depth
Burst Length(Read)
Burst Length(Write)
256 bit
High speed vertical and horizontal drawing.
1024 bytes
High speed vertical and horizontal drawing.
1, 2, 4, 8 Full Page
Programmable burst of 1, 2, ,4, 8 and full page transfer per column
addresses.
1, 2, 4, 8 Full Page
Programmable burst of 1, 2, ,4, 8 and full page transfer per column
addresses.
BRSW
Burst Type
Switch to burst length of 1 at write without MRS.
Sequential & Interleave
CAS Latency
2, 3
Block Write
Benefits
Better interaction between memory and system without wait-state of
asynchronous DRAM.
High speed vertical and horizontal drawing.
High operating frequency allows performance gain for SCROLL, FILL,
and BitBLT.
Compatible with Intel and Motorola CPU based system.
Programmable CAS latency.
8 Columns
High speed FILL, CLEAR, Text with color registers.
Maximum 32 byte data transfers(e.g. for 8bpp : 32 pixels) with plane and
byte masking functions.
Color Register
1 ea.
A and B bank share.
Mask Register
1 ea.
Write-per-bit capability(bit plane masking). A and B banks share.
DQM0-3
Mask function
Byte masking(pixel masking for 8bpp system) for data-out/in
Write per bit
Pixel Mask at Block Write
Each bit of the mask register directly controls a corresponding bit plane.
Byte masking(pixel masking for 8bpp system) for color by DQi
BASIC FEATURE AND FUNCTION DESCRIPTIONS
1. CLOCK Suspend
1) Clock Suspended During Write (BL=4)
2) Clock Suspended During Read (BL=4)
CLK
CMD
WR
RD
CKE
Masked by CKE
Masked by CKE
Internal
CLK
DQ(CL2)
D0
D1
D2
D3
DQ(CL3)
D0
D1
D2
D3
Not Written
Q0
D
Q01
Q2
Q3
Q0
Q1
Q2
Q3
Suspended Dout
Note : CKE to CLK disable/enable=1 clock
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
2. DQM Operation
1) Write Mask (BL=4)
2) Read Mask (BL=4)
CLK
CMD
WR
RD
DQMi
Note 1
Masked by DQM
DQ(CL2)
D0
DQ(CL3)
D0
D1
D3
D1
Q0
Masked by DQM
Hi-Z
Hi-Z
D3
DQM to Data-in Mask = 0CLK
3) DQM with Clock Suspended (Full Page Read)
Q2
Q3
Q1
Q2
Q3
DQM to Data-out Mask = 2CLK
Note2
CLK
CMD
RD
CKE
DQM
DQ(CL2)
DQ(CL3)
Q0
Hi-Z
Hi-Z
Q2
Q1
Hi-Z
Hi-Z
Q4
Q3
Hi-Z
Hi-Z
Q6
Q7
Q8
Q5
Q6
Q7
*Note : 1. There are 4 DQMi(i=0~3).
Each DQMi masks 8 DQi's.(1 Byte, 1 Pixel for 8 bpp)
2. DQM makes data out Hi-Z after 2 clocks which should masked by CKE " L".
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
3. CAS Interrupt (I)
1) Read interrupted by Read (BL=4) Note 1
CLK
CMD
RD
RD
ADD
A
B
DQ(CL2)
QA0
DQ(CL3)
QB0
QB1
QB2
QB3
QA0
QB0
QB1
QB2
QB3
tCCD
Note 2
2) Write interrupted by(Block) Write (BL=2)
3) Write interrupted by Read (BL=2)
CLK
CMD
WR
WR
tCCD
ADD
WR
tCCD
Note 2
A
B
DA0
DB0
BW
C
WR
RD
tCCD
Note 2
D
A
Note 2
B
Note 4
DQ
DB1
DC0 Pixel
tCDL
tCDL
Note 3
Note 3
DQ(CL2)
DA0
DQ(CL3)
DA0
QB0
QB1
QB0
QB1
tCDL
Note 3
4) Block Write to Block Write
(b) tCC ¡Ã tBWC
(a) tCC < tBWC
Note 5
CLK
CMD
BW
NOP
BW
BW
BW
B
A
B
Note 7
ADD
A
X
Note 4
DQ
Pixel
Pixel
Note 4
Pixel Pixel
tBWC
tBWC
Note 6
Note 6
*Note : 1. By " Interrupt ", It is possible to stop burst read/write by external command before the end of burst.
By "CAS Interrupt", to stop burst read/write by CAS access ; read, write and block write.
2. tCCD : CAS to CAS delay. (=1CLK)
3. tCDL : Last data in to new column address delay. (=1CLK)
4. Pixel :Pixel mask.
5. tCC : Clock cycle time.
6. tBWC : Block write minimum cycle time.
7. Other Bank can be active or precharge.
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
4. CAS Interrupt (II) : Read Interrupted by Write & DQM
(1) CL=2, BL=4
CLK
i) CMD
RD
WR
DQM
D0
DQ
ii) CMD
RD
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
WR
DQM
Hi-Z
DQ
iii) CMD
D0
RD
WR
DQM
Hi-Z
DQ
iv) CMD
D0
RD
WR
DQM
DQ
Q0
Hi-Z
Note 1
D0
D3
(2) CL=3, BL=4
CLK
i) CMD
RD
WR
DQM
D0
DQ
ii) CMD
RD
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
WR
DQM
D0
DQ
iii) CMD
RD
WR
DQM
D0
DQ
iv) CMD
RD
WR
DQM
Hi-Z
DQ
v) CMD
D0
RD
WR
DQM
DQ
Q0
Hi-Z
Note 2
D0
D3
*Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.
2. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
5. Write Interrupted by Precharge & DQM
CLK
Note 2
CMD
WR
PRE
Note 1
DQM
DQ
D0
D1
D2
D3
Masked by DQM
*Note : 1. To inhibit invalid write, DQM should be issued.
2. This precharge command and burst write command should be of the same bank, otherwise it is not precharge
interrupt but only another bank precharge of dual banks operation.
6. Precharge
1) Normal Write (BL=4)
2) Block Write
CLK
CLK
CMD
WR
DQ
D0
CMD
PRE
D1
D2
BW
DQ
D3
PRE
Pixel
tRDL
tBPL
Note 1
Note 1
3) Read (BL=4)
CLK
CMD
RD
PRE
DQ(CL2)
Q0
DQ(CL3)
Note 2
Q1
Q2
Q3
Q0
Q1
Q2
1
Q3
2
7. Auto Precharge
1) Normal Write (BL=4)
2) Block Write
CLK
CLK
CMD
WR
DQ
D0
D1
D2
D3
CMD
BW
DQ
(CL 2, 3)
Pixel
Note 3
Auto Precharge Starts
3) Read (BL=4)
DQ(CL2)
DQ(CL3)
tBAL
Note 3
Auto Precharge Starts
CLK
CMD
tRP
tBPL
RD
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Note 3
Auto Precharge Starts
*Note : 1. tBPL : Block write data-in to PRE command delay
2. Number of valid output data after Row Precharge : 1, 2 for CAS Latency =2, 3 respectively.
3. The row active command of the precharge bank can be issued after t RP from this point.
The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
8. Burst Stop & Precharge Interrupt
1) Write Interrupted by Precharge (BL=4)
2) Write Burst Stop (Full Page Only)
CLK
CLK
CMD
WR
PRE
CMD
WR
DQ
D0
STOP
DQM
DQ
D0
D1
D2
tRDL
D3
D2
tBDL
Note 1
3) Read Interrupted by Precharge (BL=4)
4) Read Burst Stop (Full Page Only)
CLK
CMD
D1
CLK
RD
PRE
CMD
RD
STOP
Note 3
DQ(CL2)
Q0
DQ(CL3)
Q1
Q0
1
Note 3
DQ(CL2)
Q1
2
Q0
DQ(CL3)
Q1
Q0
1
Q1
2
9. MRS & SMRS
1) Mode Register Set
2) Special Mode Register Set
CLK
CLK
Note 4
CMD
MRS ACT
PRE
tRP
1CLK
CMD
SMRS ACT SMRS SMRS BW
1CLK
1CLK
1CLK
1CLK
*Note : 1. tRDL : 1 CLK, Last Data in to Row Precharge.
2. tBDL : 1 CLK, Last Data in to Burst Stop Delay.
3. Number of valid output data after Row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectiviely.
4. PRE : Both banks precharge if necessary.
MRS can be issued only at all bank precharge state.
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
10. Clock Suspend Exit & Power Down Exit
1) Clock Suspend (=Active Power Down) Exit
2) Power Down (=Precharge Power Down) Exit
CLK
CLK
CKE
Internal
CLK
tSS
CKE
tSS
Internal
CLK
Note 1
CMD
Note 2
CMD
RD
NOP ACT
11. Auto Refresh & Self Refresh
1) Auto Refresh Note 3
CLK
¡ó
Note 4
CMD
Note 5
PRE
AR
CMD
¡ó
CKE
¡ó
tRP
tRC
¡ó
2) Self Refresh Note 6
¡ó
CLK
¡ó
Note 4
CMD
PRE
SR
CMD
¡ó
CKE
¡ó
tRP
¡ó
¡ó
tRC
*Note : 1. Active power down : one or more bank active state.
2. Precharge power down : both bank precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
No precharge commands are required after Auto Refresh command.
During tRC from auto refresh command, any other command can not be accepted.
4. Before executing auto/self refresh command, both banks must be idle state.
5. (S)MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh mode, refresh interval and refresh operation are perfomed internally.
After self refresh entry, self refresh mode is kept while CKE is LOW.
During self refresh mode, all inputs expect CKE will be don't cared, and outputs will be in Hi-Z state.
During tRC from self refresh exit command, any other command can not be accepted.
Before/After self refresh mode, burst auto refresh cycle (1K cycles) is recommended.
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
12. About Burst Type Control
Sequential Counting
At MRS A 3 = "0". See the BURST SEQUENCE TABLE. (BL=4,8)
BL=1, 2, 4, 8 and full page wrap around.
Interleave Counting
At MRS A 3 = "1". See the BURST SEQUENCE TABLE. (BL=4,8)
BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting
Basic
MODE
PseudoDecrement Sequential
Counting
At MRS A 3 = "1".(See to Interleave Counting Mode)
Starting Address LSB 3 bits A 0-2 should be "000" or "111".@BL=8.
-- if LSB="000" : Increment Counting.
-- if LSB="111" : Decrement Counting.
For Example,(Assume Addresses except LSB 3 bits are all 0, BL=8)
-- @ write, LSB="000", Accessed Column in order 0-1-2-3-4-5-6-7
-- @ read, LSB="111", Accessed Column in order 7-6-5-4-3-2-1-0
At BL=4, same applications are possible. As above example, at Interleave Counting mode,
by confining starting address to some values, Pseudo-Decrement Counting Mode can be
realized. See the BURST SEQUENCE TABLE carefully.
PseudoBinary Counting
At MRS A 3 = "0".(See to Sequential Counting Mode)
A 0-2 = "111".(See to Full Page Mode)
Using Full Page Mode and Burst Stop Command, Binary Counting Mode can be realized.
-- @ Sequential Counting, Accessed Column in order 3-4-5-6-7-1-2-3(BL=8)
-- @ Pseudo-Binary Counting,
Accessed Column in order 3-4-5-6-7-8-9-10(Burst Stop command)
Note. The next column address of 256 is 0.
PseudoMODE
Random
MODE
Random column Access
tCCD = 1 CLK
Every cycle Read/Write Command with random column address can realize
Random Column Access.
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
13. About Burst Length Control
Basic
MODE
1
At MRS A 2,1,0 = "000".
At auto precharge, t RAS should not be violated.
2
At MRS A 2,1,0 = "001".
At auto precharge, t RAS should not be violated.
4
At MRS A 2,1,0 = "010".
8
At MRS A 2,1,0 = "011".
Full Page
BRSW
Special
MODE
Block Write
Random
MODE
Burst Stop
RAS Interrupt
(Interrupted by Precharge)
Interrupt
MODE
CAS Interrupt
At MRS A 2,1,0 = "111".
Wrap around mode(Infinite burst length)should be stopped by burst stop,
RAS interrupt or CAS interrupt.
At MRS A 9 = "1".
Read burst =1, 2, 4, 8, full page/write Burst =1
At auto precharge of write, t RAS should not be violated.
8 Column Block Write. LSB A0-2 are ignored. Burst length=1.
tBWC should not be violated.
At auto precharge, t RAS should not be violated.
tBDL= 1, Valid DQ after burst stop is 1, 2 for CL=2, 3 respectively
Using burst stop command, it is possible only at full page burst length.
Before the end of burst, Row precharge command of the same bank
stops read/write burst with Row precharge.
tRDL= 1 with DQM, valid DQ after burst stop is 1, 2 for CL= 2, 3 respectively
During read/write burst with auto precharge, RAS interrupt cannot be issued.
Before the end of burst, new read/write stops read/write burst and starts new
read/write burst or block write.
During read/write burst with auto precharge, CAS interrupt can not be issued.
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
14. Mask Functions
1) Normal Write
I/O masking : By Mask at Write Per Bit Mode, the selected bit planes keep the original data.
If bit plane 0, 3, 7, 9, 15, 22, 24, and 31 keep the original value.
i) STEP
¨ç SMRS(LMR) :Load mask[31-0]="0111, 1110, 1011, 0111, 1111, 1101, 0111, 0110"
¨è Row Active with DSF "H" :Write Per Bit Mode Enable
¨é Perform Normal Write.
i) ILLUSTRATION
I/O(=DQ)
31
External Data-in
24
11111111
23
16
11111111
15
8
00000000
7
0
00000000
DQMi
DQM3=0
DQM2=0
DQM1=0
DQM0=1
Mask Register
01111110
10110110
11111101
01110110
Before Write
00000000
00000000
11111111
11111111
After Write
01111110
10110110
00000010
11111111
Note 1
2) Block Write
Pixel masking : By Pixel Data issued through DQ pin, the selected pixels keep the original data.
See PIXEL TO DQ MAPPING TABLE.
If Pixel 0, 4, 9, 13, 18, 22, 27 and 31 keep the original white color.
Assume 8bpp,
White = "0000,0000", Red="1010,0011", Green = "1110,0001", Yellow = "0000,1111", Blue = "1100,0011"
i) STEP
¨ç SMRS(LCR) :Load color(for 8bpp, through x32 DQ color0-3 are loaded into color registers)
Load(color3, color2, color1, color0) = (Blue, Green, Yellow, Red)
= "1100,0011, 1110, 0001, 0000, 1111, 1010, 0011"
¨è Row Active with DSF "L" : I/O Mask by Write Per Bit Mode Disable
¨é Block write with DQ[31-0] = "0111, 0111, 1011, 1011, 1101, 1101, 1110, 1110"
i) ILLUSTRATION
I/O(=DQ)
31
24
23
16
15
8
7
0
DQMi
DQM3=0
DQM2=0
DQM1=0
DQM0=1
Color Register
Color3=Blue
Color2=Green
Color1=Yellow
Color0=Red
000
White DQ 24=H
White DQ 16=H
White DQ 8=H
White DQ 0=L
001
White DQ 25=H
White DQ 17=H
White DQ 9=L
White DQ 1=H
010
White DQ 26=H
White DQ 18=L
White DQ 10=H
White DQ 2=H
011
White DQ 27=L
White DQ 19=H
White DQ 11=H
White DQ 3=H
100
White DQ 28=H
White DQ 20=H
White DQ 12=H
White DQ 4=L
101
White DQ 29=H
White DQ 21=H
White DQ 13=L
White DQ 5=H
110
White DQ 30=H
White DQ 22=L
White DQ 14=H
White DQ 6=H
111
White DQ 31=L
White DQ 23=H
White DQ 15=H
White DQ 7=H
000
Blue
Green
Yellow
White
001
Blue
Green
White
White
010
Blue
White
Yellow
White
011
White
Green
Yellow
White
100
Blue
Green
Yellow
White
101
Blue
Green
White
White
Before
Block
Write
&
DQ
(Pixel
data)
After
Block
Write
110
Blue
White
Yellow
White
111
White
Green
Yellow
White
Note 2
*Note : 1. DQM byte masking.
2. At normal write, ONE column is selected among columns decorded by A 2-0(000-111).
At block write, instead of ignored address A 2-0, DQ0-31 control each pixel.
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
(Continued)
Pixel and I/O masking : By Mask at Write Per Bit Mode, the selected bit planes keep the original data.
By Pixel Data issued through DQ pin, the selected pixels keep the original data.
See PIXEL TO DQ MAPPING TABLE.
Assume 8bpp,
White = "0000,0000", Red="1010,0011", Green ="1110,0001", Yellow ="0000,1111", Blue ="1100,0011"
i) STEP
¨ç SMRS(LCR) : Load color(for 8bpp, through x 32 DQ color0-3 are loaded into color registers)
Load(color3, color2, color1, color0) = (Blue, Green, Yellow, Red)
= "1100,0011,1110,0001,0000,1111,1010,0011"
¨è SMRS(LMR ): Load mask. Mask[31-0] ="1111,1111,1101,1101, 0100,0010,0111,0110"
--> Byte 3 : No I/O Masking ; Byte 2 : I/O Masking ; Byte 1 : I/O and Pixel Masking ; Byte 0 : DQM Byte Maskin g
¨é Row Active with DSF "H" : I/O Mask by Write Per Bit Mode Enable
¨ê Block Write with DQ[31-0] = "0111,0111,1111,1111,0101,0101,1110,1110"
(Pixel Mask)
i) ILLUSTRATION
I/O(=DQ)
31
Color Register
24
Blue
11000011
23
16
Green
11100001
15
8
Yellow
00001111
7
0
Red
10100011
DQMi
DQM3=0
DQM2=0
DQM1=0
DQM0=1
Mask Register
11111111
11011101
01000010
01110110
Before Write
Yellow
00001111
Yellow
00001111
Green
11100001
White
00000000
After Write
Blue
11000011
Blue
11000011
Red
10100011
White
00000000
31
23
15
7
Note 1
I/O(=DQ)
24
16
8
0
DQMi
DQM3=0
DQM2=0
DQM1=0
DQM0=1
Color Register
Color3=Blue
Color2=Green
Color1=Yellow
Color0=Red
000
Yellow DQ 24=H
Yellow DQ 16=H
Green DQ 8=H
White DQ 0=L
001
Yellow DQ 25=H
Yellow DQ 17=H
Green DQ 9=L
White DQ 1=H
010
Yellow DQ 26=H
Yellow DQ 18=H
Green DQ 10=H
White DQ 2=H
011
Yellow DQ 27=L
Yellow DQ 19=H
Green DQ 11=L
White DQ 3=H
100
Yellow DQ 28=H
Yellow DQ 20=H
Green DQ 12=H
White DQ 4=L
101
Yellow DQ 29=H
Yellow DQ 21=H
Green DQ 13=L
White DQ 5=H
110
Yellow DQ 30=H
Yellow DQ 22=H
Green DQ 14=H
White DQ 6=H
111
Yellow DQ 31=L
Yellow DQ 23=H
Green DQ 15=L
White DQ 7=H
Before
Block
Write
&
DQ
(Pixel
data)
After
Block
Write
000
Blue
Blue
Red
White
001
Blue
Blue
Green
White
010
Blue
Blue
Red
White
011
Yellow
Blue
Green
White
100
Blue
Blue
Red
White
101
Blue
Blue
Green
White
110
Blue
Blue
Red
White
111
Yellow
Blue
Green
White
Note 2
Note 1
PIXEL MASK
I/O MASK
PIXEL & I/O MASK
BYTE MASK
*Note : 1. DQM byte masking.
2. At normal write, ONE column is selected among columns decorded by A 2-0(000-111).
At block write, instead of ignored address A 2-0, DQ0-31 control each pixel.
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
Power On Sequence & Auto Refresh
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High level is necessary
¡ó
¡ó
CS
tRP
tRC
RAS
CAS
ADDR
BA0
BA1
A8/AP
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
ADDRESS KEY
RAa
RAa
High-Z
DQ
WE
DQM
High level is necessary
Precharge
(All Banks)
Auto Refresh
Auto Refresh
Mode Register Set
Row Active
(A-Bank)
: Don't care
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
Single Bit Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length=1
tCH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
tCL
tCC
HIGH
CKE
tRAS
tRC
*Note 1
tSH
CS
tRCD
tRP
tSS
tSH
RAS
tCCD
tSS
tSH
CAS
tSS
tSH
ADDR
Ra
tSS
Ca
Cb
Cc
Rb
tSH
tSS
*Note 2
*Note 2,3
*Note 2,3
A9
BS
BS
BS
A8
Ra
*Note 3
*Note 2,3 *Note 4
BS
*Note 3
*Note 2
BS
BS
*Note 3 *Note 4
Rb
tSH
WE
tSS
*Note 5
*Note 6
*Note 5
*Note 3
DSF
tSS
tSH
tSS
tSH
DQM
tRAC
tSH
tSAC
Qa
DQ
tSLZ
Db
Qc
tSS
tOH
tSHZ
Row Active
(Write per Bit
Enable or Disable)
Read
Write
or
Block Write
Read
Precharge
Row Active
(Write per Bit
Enable or
Disable)
: Don't care
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
*Note : 1. All input can be don't care when CS is high at the CLK high going edge.
2. Bank active & read/write are controlled by A 9.
A9
Active & Read/Write
0
Bank A
1
Bank B
3. Enable and disable auto precharge function are controlled by A 8 in read/write command.
A8
A9
0
1
Operation
0
Disable auto precharge, leave bank A active at end of burst.
1
Disable auto precharge, leave bank B active at end of burst.
0
Enable auto precharge, precharge bank A at end of burst.
1
Enable auto precharge, precharge bank B at end of burst.
4. A8 and A 9 control bank precharge when precharge command is asserted.
A8
A9
Precharge
0
0
Bank A
0
1
Bank B
1
X
Both Bank
5. Enable and disable Write-per Bit function are controlled by DSF in Row Active command.
A9
0
1
DSF
Operation
L
Bank A row active, disable write per bit function for bank A
H
Bank A row active, enable write per bit function for bank A
L
Bank B row active, disable write per bit function for bank B
H
Bank B row active, enable write per bit function for bank B
6. Block write/normal write is controlled by DSF.
DSF
Operation
Minimum cycle time
L
Normal write
H
Block write
tCCD
tBWC
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
Read & Write Cycle at Same Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
*Note 1
tRC
CS
tRCD
RAS
*Note 2
CAS
ADDR
Ra
Ca0
Cb0
Rb
A9
A8
Ra
Rb
WE
DSF
DQM
tOH
DQ
CL=2
Qa0
tRAC
*Note 3
Qa1
Qa2
Qa3
tSAC
Db0
tSHZ
Db1
Db2
Db3
tRDL
*Note 4
tOH
CL=3
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
tRAC
*Note 3
Row Active
(A-Bank)
Read
(A-Bank)
tSAC
Precharge
(A-Bank)
tSHZ
tRDL
*Note 4
Row Active
(A-Bank)
Db3
Write
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note : 1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] valid output data available after Row
enters precharge. Last valid output will be Hi-Z after tSHZ from the clcok.
3. Access time from Row address. tCC *(tRCD + CAS latency - 1) + tSAC
4. Ouput will be Hi-Z after the end of burst. (1, 2, 4, & 8)
At Full page bit burst, burst is wrap-around.
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
Page Read & Write Cycle at Same Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
tRCD
RAS
CAS
ADDR
Ra
Ca0
Cb0
Cc0
Cd0
A9
A8
Ra
tRDL
tCDL
WE
*Note 2
DSF
*Note 1
*Note 3
DQM
DQ
CL=2
Qa0
CL=3
Row Active
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Qa1
Qb0
Qb1
Dc0
Dc1
Dd0
Dd1
Qa0
Qa1
Qb0
Dc0
Dc1
Dd0
Dd1
Write
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write
command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
Block Write cycle(with Auto Precharge)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
*Note 4
ADDR
Ra
CAa
CAb
RBa
CBa
CBb
Pixel
Mask
Pixel
Mask
A9
A8
RAa
RBa
WE
DSF
*Note 2
tBWC
DQM
*Note 3
*Note 1
Pixel
Mask
DQ
Row Active with
Write-per-Bit
Enable
(A-Bank)
Pixel
Mask
Masked
Block Write
(A-Bank)
Row Active
(B-Bank)
Masked
Block Write with
Auto Precharge
(A-Bank)
Block Write with
Auto Precharge
(B-Bank)
Block Write
(B-Bank)
: Don't care
*Note : 1. Column Mask(DQi=L : Mask, DQi=H :Non Mask)
2. tBWC : Block Write Cycle time
tBWC > tCC :Two CLK Cycle Block Write
tBWC ¡Â tCC :One CLK Cycle Block Write
3. At two Cycle Block Write, second cycle should be in NOP.
Other Bank can be active or precharge.
4. At Block Write, CA 0~2 are ignored.
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
SMRS and Block/Normal Write @ Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
CS
RAS
CAS
*Note 1
RBa
CBa
CAa
RBa
CBa
RAa
CAa
RBa
CBa
A6
RAa
CAa
RBa
CBa
A8
RAa
A0-2
RAa
A3,4,7
RAa
A5
RBa
A9
WE
DSF
DQM
DQ
Color
I/O
Mask
Load Color
Register
Load Mask
Register
Row Active
with WPB*
Enable
(A-Bank)
Pixel
Mask
Masked
Block Write
(A-Bank)
I/O
Mask
Color
DBa0 DBa1 DBa2 DBa3
Row Active Load Color
with WPB*
Register
Enable
Masked Write
(B-Bank)
with Auto
Load Mask Register
Precharge
(B-Bank)
WPB* : Write-Per-Bit
: Don't care
*Note : 1. At the next clock of special mode set command, new command is possible.
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
Page Read Cycle at Different Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
*Note 1
CS
RAS
*Note 2
CAS
ADDR
RAa
RBb
CAa
CBb
CAc
CBd
CAe
A9
A8
RAa
RBb
WE
LOW
DSF
DQM
DQ
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1
CL=2
CL=3
QAa0 QAa1 QAa2 QAa3
Row Active
(A-Bank)
Row Active
(B-Bank)
Read
(B-Bank)
QBd0 QBd1 QAe0 QAe1
QBb0 QBb1 QBb2 QBb3 QAc0 QAc1
Read
(A-Bank)
Read
(B-Bank)
QBd0 QBd1 QAe0 QAe1
Read
(A-Bank)
Precharge
(A-Bank)
Read
(A-Bank)
: Don't care
*Note : 1. CS can be don't care when RAS, CAS and WE are high at the clock high going edge.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
Page Write Cycle at Different Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
Key
CAa
CBb
RBb
CAc
CBd
A9
A8
RAa
RBb
tCDL
WE
DSF
DQM
DQ
Mask
DAa0 DAa1 DAa2
Load Mask
Register
Row Active
(B-Bank)
Row Active with
Write-Per-Bit
enable
(A-Bank)
Masked Write
(A-Bank)
DAa3
DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DAc2
Write
(B-Bank)
Masked Write
with auto
precharge
(A-Bank)
DAc3
DBd0 DBd1 DBd2 DBd3
Write with auto
Precharge
(B-Bank)
: Don't care
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
Read & Write Cycle at Different Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
CAa
RBb
CBb
RAc
CAc
A9
A8
RAa
RBb
RAc
tCDL
*Note 1
WE
DSF
DQM
DQ
QAa0 QAa1 QAa2 QAa3
CL=2
CL=3
QAa0 QAa1 QAa2 QAa3
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(B-Bank)
DBb0 DBb1 DBb2 DBb3
QAc0
DBb0 DBb1 DBb2 DBb3
Write
(B-Bank)
QAc1 QAc2
QAc0
QAc1
Read
(A-Bank)
Row Active
(A-Bank)
: Don't care
*Note : 1. tCDL should be met to complete write.
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
Read & Write Cycle with Auto Precharge @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
Ra
Rb
Ra
Rb
Ca
Cb
A9
A8
WE
DSF
DQM
DQ
CL=2
Qa0
CL=3
Row Active
(A-Bank)
Read with
Auto Precharge
(A-Bank)
Qa1
Qa2
Qa3
Qa0
Qa1
Qa2
Qa3
Auto Precharge
Start Point
(A-Bank)
Db0
Db1
Db2
Db3
Db0
Db1
Db2
Db3
Write with
Auto Precharge
(B-Bank)
Auto Precharge
Start Point
(B-Bank)
Row Active
(B-Bank)
: Don't care
*Note : 1. tRCD should be controlled to meet minimum tRAS before internal precharge start.
(In the case of Burst Length=1 & 2, BRSW mode and Block write)
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
Read Interrupted by Precharge Command & Read Burst Stop Cycle (@Full page Only)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
CAa
CAb
*Note 1
*Note 1
A9
A8
RAa
WE
DSF
DQM
1
1
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
*Note 2
DQ
CL=2
CL=3
Row Active
(A-Bank)
Read
(A-Bank)
2
2
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
Burst Stop
Read
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.
2. About the valid DQ's after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the label 1, 2 on them.
But at burst write, Burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of "Full page write burst stop cycle".
3. Burst stop is valid at full page mode.
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
Write Interrupted by Precharge Command & Write Burst Stop Cycle (@ Full page Only)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
CAa
CAb
*Note 1
*Note 1
A9
A8
RAa
tRDL
tBDL
WE
DSF
*Note 3
DQM
*Note 2
DAa0 DAa1 DAa2 DAa3 DAa4
DQ
Row Active
(A-Bank)
Write
(A-Bank)
Burst Stop
DAb0 DAb1 DAb2 DAb3 DAb4
DAb5
Write
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.
2. Data-in at the cycle of burst stop command cannot be written into the corresponding memory cell.
It is defined by AC parameter of tBDL(=1CLK).
3. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell.
It is defined by AC parameter of
tRDL(=1CLK).
DQM at write interrupted by precharge command is needed to ensure
tRDL of 1CLK.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
4. Burst stop is valid only at full page burst length.
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
Burst Read Single bit Write Cycle @Burst Length=2, BRSW
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
*Note 1
HIGH
CKE
CS
RAS
*Note 2
CAS
ADDR
RAa
CAa
RBb
CAb
RAc
CBc
CAd
A9
A8
RAa
RBb
RAc
WE
DSF
DQM
DQ
CL=2
DAa0
CL=3
DAa0
Row Active
(A-Bank)
QAb0 QAb1
QAb0 QAb1
Row Active
(B-Bank)
Write
(A-Bank)
Read with
Auto Precharge
(A-Bank)
QAd0 QAd1
DBc0
QAd0 QAd1
DBc0
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Write with
Auto Precharge
(B-Bank)
: Don't care
*Note :
1. BRSW mode is enabled by setting A 9 "High" at MRS (Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to "1" regardless of programed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that
tRAS should not be violated.
Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command,
the next cycle starts the precharge.
3. WPB function is also possible at BRSW mode.
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
Clock suspension & DQM operation cycle @CAS Latency=2, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS
RAS
CAS
ADDR
Ra
Ca
Cb
Cc
A9
A8
Ra
WE
DSF
*Note 1
DQM
DQ
Qa0
Qa1
Qa2
Qb0
Qa3
tSHZ
Row Active
Read
Clock
Suspension
Read
Qb1
Dc0
Dc2
tSHZ
Write
DQM
Read DQM
Write
Clock
Suspension
: Don't care
*Note : 1. DQM needed to prevent bus contention.
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
Active/Precharge Power Down Mode @CAS Lantency=2, Burst Length=4
0
1
2
3
CLOCK
¡ó
¡ó
tSS
4
5
6
7
9
10
11
12
13
14
15
16
17
18
19
¡ó
*Note 2
tSS
tSS
*Note 1
CKE
8
tSS
¡ó
*Note 3
¡ó
¡ó
CS
¡ó
RAS
CAS
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
ADDR
¡ó
A9
DSF
DQM
DQ
Precharge
Power-down
Entry
¡ó
¡ó
¡ó
¡ó
¡ó
WE
¡ó
¡ó
¡ó
A8
Ra
Ra
Ca
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
Qa0
Read
Precharge
Power-down
Exit
Qa1
Qa2
Precharge
Row Active
Active
Power-down
Entry
*Note :
Active
Power-down
Exit
1. All banks should be in idle state prior to entering precharge power down mode.
: Don't care
2. CKE should be set high at least "1CLK + tSS" prior to Row active command.
3. Cannot violate minimum refresh specification. (16ms)
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
Self Refresh Entry & Exit Cycle
0
1
2
3
CLOCK
*Note 2
4
5
6
¡ó
7
¡ó
8
9
10
11
12
13
15
16
17
18
19
¡ó
*Note 4
tRCmin.
tSS
*Note 1
*Note 3
CKE
14
¡ó
*Note 6
¡ó
tSS
¡ó
CS
*Note 5
¡ó
¡ó
RAS
*Note 7
CAS
ADDR
A9
A8
WE
DSF
DQM
Hi-Z
DQ
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
Self Refresh Entry
*Note :
Hi-Z
*Note 7
¡ó
Self Refresh Exit
Auto Refresh
TO ENTER SELF REFRESH MODE
: Don't care
1. CS, RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in self refresh mode as long as CKE stays "Low".
cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum tRC is required after CKE going high to complete self refresh exit.
7. 1K cycle of burst auto refresh is required before self refresh entry and after self refresh exit
if the system uses burst refresh.
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
Mode Register Set Cycle
0
1
2
3
4
5
Auto Refresh Cycle
6
7
8
9
10
11
12
13
14
CLOCK
15
16
17
18
19
¡ó
HIGH
CKE
¡ó
HIGH
¡ó
CS
*Note 2
tRC
RAS
¡ó
¡ó
¡ó
*Note 1
¡ó
CAS
¡ó
*Note 3
ADDR
Key
¡ó
Ra
¡ó
¡ó
WE
¡ó
¡ó
DSF
¡ó
¡ó
DQM
¡ó
DQ
Hi-Z
MRS New
Command
Hi-Z
¡ó
Auto Refresh
New Command
: Don't care
* Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
*Note :
1. CS, RAS, CAS, & WE activation and DSF of low at the same clock cycle with address key will set internal
mode register.
2. Minimum 1 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
FUNCTION TRUTH TABLE(TABLE 1)
Current
State
IDLE
Row
Active
Read
Write
CS
RAS
CAS
WE
DSF
BA
(A9)
ADDR
ACTION
NOTE
H
X
X
X
X
X
X
NOP
L
H
H
H
X
X
X
NOP
L
H
H
L
X
X
X
ILLEGAL
2
L
H
L
X
X
BA
CA
ILLEGAL
2
L
L
H
H
L
BA
RA
Row Active ; Latch Row Address ; Non-IO Mask
L
L
H
H
H
BA
RA
Row Active ; Latch Row Address ; IO Mask
L
L
H
L
L
BA
PA
NOP
L
L
H
L
H
X
X
ILLEGAL
L
L
L
H
L
X
X
Auto Refresh or Self Refresh
L
L
L
H
H
X
X
ILLEGAL
L
L
L
L
L
OP Code
Mode Register Access
5
L
L
L
L
H
OP Code
Special Mode Register Access
6
H
X
X
X
X
X
X
NOP
L
H
H
H
X
X
X
NOP
L
H
H
L
X
X
X
ILLEGAL
4
5
2
L
H
L
H
L
BA
CA,AP
L
H
L
H
H
X
X
Begin Read ; Latch CA ; Determine AP
L
H
L
L
L
BA
CA,AP
Begin Write ;Latch CA ; Determine AP
L
H
L
L
H
BA
CA,AP
Block Write ;Latch CA ; Determine AP
L
L
H
H
X
BA
RA
ILLEGAL
ILLEGAL
L
L
H
L
L
BA
PA
Precharge
L
L
H
L
H
X
X
ILLEGAL
L
L
L
H
X
X
X
ILLEGAL
L
L
L
L
L
X
X
ILLEGAL
L
L
L
L
H
OP Code
2
Special Mode Register Access
H
X
X
X
X
X
X
NOP(Continue Burst to End --> Row Active)
L
H
H
H
X
X
X
NOP(Continue Burst to End --> Row Active)
L
H
H
L
L
X
X
Term burst --> Row active
L
H
H
L
H
X
X
ILLEGAL
L
H
L
H
L
BA
CA,AP
L
H
L
H
H
X
X
Term burst ; Begin Read ; Latch CA ; Determine AP
6
3
ILLEGAL
L
H
L
L
L
BA
CA,AP
Term burst ; Begin Write ; Latch CA ; Determine AP
3
L
H
L
L
H
BA
CA.AP
Term burst ; Block Write ; Latch CA ; Determine AP
3
L
L
H
H
X
BA
RA
ILLEGAL
2
L
L
H
L
L
BA
PA
Term Burst ; Precharge timing for Reads
3
L
L
H
L
H
X
X
ILLEGAL
L
L
L
X
X
X
X
ILLEGAL
H
X
X
X
X
X
X
NOP(Continue Burst to End --> Row Active)
L
H
H
H
X
X
X
NOP(Continue Burst to End --> Row Active)
L
H
H
L
L
X
X
Term burst --> Row active
L
H
H
L
H
X
X
ILLEGAL
L
H
L
H
L
BA
CA,AP
L
H
L
H
H
X
X
Term burst ; Begin Read ; Latch CA ; Determine AP
3
ILLEGAL
L
H
L
L
L
BA
CA,AP
Term burst ; Begin Write ; Latch CA ; Determine AP
3
L
H
L
L
H
BA
CA,AP
Term burst ; Block Write ; Latch CA ; Determine AP
3
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
FUNCTION TRUTH TABLE(TABLE 1, Continued)
Current
State
Write
Read with
Auto
Precharge
Write with
Auto
Precharge
Precharging
Block
Write
Recovering
Row
Activating
Refreshing
CS
RAS
CAS
WE
DSF
BA
(A9)
ADDR
L
L
H
H
X
BA
RA
ILLEGAL
2
L
L
H
L
L
BA
PA
Term Burst : Precharge timing for Writes
3
L
L
H
L
H
X
X
ILLEGAL
ACTION
NOTE
L
L
L
X
X
X
X
ILLEGAL
H
X
X
X
X
X
X
NOP(Continue Burst to End --> Precharge)
L
H
H
H
X
X
X
NOP(Continue Burst to End --> Precharge)
L
H
H
L
X
X
X
ILLEGAL
L
H
L
H
X
BA
CA,AP
ILLEGAL
2
L
H
L
L
X
BA
CA,AP
ILLEGAL
2
L
L
H
X
X
BA
RA,PA
ILLEGAL
L
L
L
X
X
X
X
ILLEGAL
2
H
X
X
X
X
X
X
NOP(Continue Burst to End --> Precharge)
L
H
H
H
X
X
X
NOP(Continue Burst to End --> Precharge)
L
H
H
L
X
X
X
ILLEGAL
L
H
L
H
X
BA
CA,AP
ILLEGAL
2
L
H
L
L
X
BA
CA,AP
ILLEGAL
2
L
L
H
X
X
BA
RA,PA
ILLEGAL
L
L
L
X
X
X
X
ILLEGAL
H
X
X
X
X
X
X
NOP --> Idle after tRP
L
H
H
H
X
X
X
L
H
H
L
X
X
X
NOP --> Idle after tRP
ILLEGAL
L
H
L
X
X
BA
CA,AP
ILLEGAL
2
L
L
H
H
X
BA
RA
ILLEGAL
2
L
L
H
L
X
BA
PA
2
L
L
L
X
X
X
X
NOP --> Idle after tRP
ILLEGAL
H
X
X
X
X
X
X
NOP --> Row Active after
L
H
H
H
X
X
X
NOP --> Row Active after
ILLEGAL
2
4
tBWC
tBWC
L
H
H
L
X
X
X
L
H
L
X
X
BA
CA,AP
ILLEGAL
2
L
L
H
H
X
BA
RA
ILLEGAL
2
L
L
H
L
X
BA
PA
Term Block Write : Precharge timing for Block Write
2
L
L
L
X
X
X
X
ILLEGAL
2
H
X
X
X
X
X
X
NOP --> Row Active after
L
H
H
H
X
X
X
NOP --> Row Active after
ILLEGAL
tRCD
tRCD
L
H
H
L
X
X
X
L
H
L
X
X
BA
CA,AP
ILLEGAL
2
L
L
H
H
X
BA
RA
ILLEGAL
2
L
L
H
L
X
BA
PA
ILLEGAL
2
L
L
L
X
X
X
X
ILLEGAL
2
H
X
X
X
X
X
X
NOP --> Idle after tRC
L
H
H
X
X
X
X
L
H
L
X
X
X
X
NOP --> Idle after tRC
ILLEGAL
L
L
H
X
X
X
X
ILLEGAL
L
L
L
X
X
X
X
ILLEGAL
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
FUNCTION TRUTH TABLE (TABLE 1, Continued)
ABBREVIATIONS :
RA = Row Address(A 0~A8)
NOP = No Operation Command
BA = Bank Address(A 9)
CA = Column Address(A 0~A7)
PA = Precharge All(A 8)
AP = Auto Precharge(A 8)
*Note : 1. All entries assume that CKE was active(High) during the preceding clock cycle and the current clock cycle.
2. Illegal to bank in specified state ; Function may be legal in the bank indicated by BA, depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA(and PA).
5. Illegal if any banks is not idle.
6. Legal only if all banks are in idle or row active state.
FUNCTION TRUTH TABLE for CKE(TABLE 2)
Current
State
CKE
n-1
Self
Refresh
Both
Bank
Precharge
Power
Down
All
Banks
Idle
Any State
other than
Listed
Above
CKE
n
CS
RAS
CAS
WE
DSF
ADDR
ACTION
NOTE
H
X
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
X
Exit Self Refresh --> ABI after tRC
7
L
H
L
H
H
H
X
X
Exit Self Refresh --> ABI after tRC
7
L
H
L
H
H
L
X
X
ILLEGAL
L
H
L
H
L
X
X
X
ILLEGAL
L
H
L
L
X
X
X
X
ILLEGAL
NOP(Maintain Self Refresh)
L
L
X
X
X
X
X
X
H
X
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
X
Exit Power Down --> ABI
8
L
H
L
H
H
H
X
X
Exit Power Down --> ABI
8
L
H
L
H
H
L
X
X
ILLEGAL
L
H
L
H
L
X
X
X
ILLEGAL
L
H
L
L
X
X
X
X
ILLEGAL
L
L
X
X
X
X
X
X
NOP(Maintain Power Down Mode)
H
H
X
X
X
X
X
X
Refer to Table 1
H
L
H
X
X
X
X
X
Enter Power Down
9
H
L
L
H
H
H
X
X
Enter Power Down
9
H
L
L
H
H
L
X
X
ILLEGAL
H
L
L
H
L
X
X
X
ILLEGAL
H
L
L
L
H
X
X
X
ILLEGAL
H
L
L
L
L
H
L
X
Enter Self Refresh
H
L
L
L
L
L
X
X
ILLEGAL
NOP
9
L
L
X
X
X
X
X
X
H
H
X
X
X
X
X
X
Refer to Operations in Table 1
H
L
X
X
X
X
X
X
Begin Clock Suspend next cycle
10
L
H
X
X
X
X
X
X
Exit Clock Suspend next cycle
10
L
L
X
X
X
X
X
X
Maintain clock Suspend
ABBREVIATIONS : ABI = All Banks Idle
*Note : 7. After CKE's low to high transition to exist self refresh mode. And a time of tRC(min) has to be elapse after CKE's low to high
transition to issue a new command.
8. CKE low to high transition is asynchronous as if restarts internal clock.
A minimum setup time " tSS + one clock" must be satisfied before any command other than exit.
9. Power-down and self refresh can be entered only from the all banks idle state.
10. Must be a legal command.
Rev.0 (August 1997)
KM4132G271A
CMOS SGRAM
PACKAGE DIMENSIONS
Dimensions in Millimeters
0 ~ 7¡Æ
17.20 ¡¾ 0.20
14.00 ¡¾ 0.10
#100
#1
23.20 ¡¾ 0.20
0.575
20.00 ¡¾ 0.10
0.825
0.30 ¡¾ 0.08
0.13 MAX
0.09~0.20
0.65
1.00 ¡¾ 0.10
1.40 MAX
0.10 MAX
0.05 MIN
0.80 ¡¾ 0.20
Rev.0 (August 1997)