SAMSUNG KMM5322204C2W

DRAM MODULE
KMM5322204C2W/C2WG
2Mx32 DRAM SIMM
(1MX16 Base)
Revision 0.0
November 1997
-1-
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5322204C2W/C2WG
Revision History
Version 0.0 (November 1997)
• Changed module PCB from 6-Layer to 4-Layer.
• Changed Module Part No. from KMM5322204CW/CWG to KMM5322204C2W/C2WG caused by PCB revision .
-2-
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5322204C2W/C2WG
KMM5322204C2W/C2WG Fast Page Mode with Extended Data Out
2M x 32 DRAM SIMM using 1Mx16 , 1K Refresh, 5V
GENERAL DESCRIPTION
FEATURES
The Samsung KMM5322204C2W is a 2Mx32bits
Dynamic
RAM
Samsung
high
density
memory
module.
The
• Part Identification
- KMM5322204C2W(1024 cycles/16ms Ref, SOJ, Solder)
KMM5322204C2W consists of four CMOS 1Mx16bits DRAMs
- KMM5322204C2WG(1024 cycles/16ms Ref, SOJ, Gold)
in 42-pin SOJ package mounted on a 72-pin glass-epoxy sub-
• Fast Page Mode with Extended Data Out
strate. A 0.1 or 0.22uF decoupling capacitor is mounted on the
• CAS-before-RAS refresh capability
printed circuit board for each DRAM. The KMM5322204C2W is
• RAS-only and Hidden refresh capability
a Single In-line Memory Module with edge connections and is
• TTL compatible inputs and outputs
intended for mounting into 72 pin edge connector sockets.
• Single +5V±10% power supply
PERFORMANCE RANGE
• JEDEC standard PDPin & pinout
Speed
tRAC
tCAC
tRC
tHPC
-5
50ns
15ns
90ns
25ns
-6
60ns
15ns
110ns
30ns
• PCB : Height(750mil), double sided component
PIN CONFIGURATIONS
PIN NAMES
Pin
Symbol
Pin
Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VSS
DQ0
DQ16
DQ1
DQ17
DQ2
DQ18
DQ3
DQ19
Vcc
NC
A0
A1
A2
A3
A4
A5
A6
NC
DQ4
DQ20
DQ5
DQ21
DQ6
DQ22
DQ7
DQ23
A7
NC
Vcc
A8
A9
RAS1
RAS0
NC
NC
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
NC
NC
Vss
CAS0
CAS2
CAS3
CAS1
RAS0
RAS1
NC
W
NC
DQ8
DQ24
DQ9
DQ25
DQ10
DQ26
DQ11
DQ27
DQ12
DQ28
Vcc
DQ29
DQ13
DQ30
DQ14
DQ31
DQ15
NC
PD1
PD2
PD3
PD4
NC
Vss
Pin Name
Function
A0 - A9
Address Inputs
DQ0 - DQ31
Data In/Out
W
Read/Write Enable
RAS0 , RAS1
Row Address Strobe
CAS0 - CAS3
Column Address Strobe
PD1 -PD4
Presence Detect
Vcc
Power(+5V)
Vss
Ground
NC
No Connection
Res
Reserved Pin
PRESENCE DETECT PINS (Optional)
Pin
50NS
60NS
PD1
PD2
PD3
PD4
NC
NC
Vss
Vss
NC
NC
NC
NC
* Pin connection changing available
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
-3-
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5322204C2W/C2WG
FUNCTIONAL BLOCK DIAGRAM
DQ0-DQ15
RAS0
RAS
CAS0
LCAS
U0
CAS1
UCAS
OE
A0-A9
W
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U2
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15 A0-A9
RAS
RAS1
LCAS
CAS0
UCAS
CAS1
OE
W
DQ16-DQ31
RAS
CAS2
LCAS
U1
CAS3
UCAS
OE
A0-A9
W
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U3
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15 A0-A9
RAS
LCAS
CAS2
UCAS
CAS3
OE
W
A0-A9
W
Vcc
.1 or .22uF Capacitor
for each DRAM
To all DRAMs
Vss
-4-
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5322204C2W/C2WG
ABSOLUTE MAXIMUM RATINGS *
Item
Voltage on any pin relative to V SS
Voltage on V CC supply relative to V SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
Symbol
Rating
Unit
VIN , VOUT
VCC
Tstg
Pd
IOS
-1 to +7.0
-1 to +7.0
-55 to +150
4
50
V
V
°C
W
mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for in tended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70°C)
Item
Symbol
Min
Typ
Max
Unit
VCC
VSS
VIH
VIL
4.5
0
2.4
5.0
0
-
5.5
0
V
V
V
V
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
-1.0*2
VCC +1*1
0.8
*1 : VCC +2.0V/20ns, Pulse width is measured at VCC .
*2 : -2.0V/20ns, Pulse width is measured at VSS .
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted)
ICC1
ICC2
ICC3
ICC4
ICC5
ICC6
II(L)
IO(L)
VOH
VOL
Symbol
Speed
ICC1
KMM5322204C2W/C2WG
Unit
Min
Max
-5
-6
-
304
284
mA
mA
ICC2
Don′t care
-
8
mA
ICC3
-5
-6
-
304
284
mA
mA
ICC4
-5
-6
-
244
224
mA
mA
ICC5
Don′t care
-
4
mA
ICC6
-5
-6
-
304
284
mA
mA
II(L)
IO(L)
Don′t care
-20
-10
20
10
uA
uA
VOH
VOL
Don′t care
2.4
-
0.4
V
V
: Operating Current * ( RAS, CAS, Address cycling @ tRC =min)
: Standby Current ( RAS=CAS=W=VIH )
: RAS Only Refresh Current * ( CAS=VIH, RAS cycling @ tRC =min)
: EDO Mode Current * ( RAS=VIL, CAS cycling : tHPC =min)
: Standby Current ( RAS=CAS=W=Vcc-0.2V)
: CAS-Before-RAS Refresh Current * ( RAS and CAS cycling @ tRC =min)
: Input Leakage Current (Any input 0 ≤VIN≤Vcc+0.5V, all other pins not under test=0 V)
: Output Leakage Current(Data Out is disabled, 0V ≤VOUT ≤Vcc)
: Output High Voltage Level (I OH = -5mA)
: Output Low Voltage Level (I OL = 4.2mA)
* NOTE : ICC1 , ICC3 , ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In I CC1 and ICC3 , address can be changed maximum once while RAS=VIL. In I CC4 ,
address can be changed maximum once within one EDO mode cycle, tHPC .
-5-
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5322204C2W/C2WG
CAPACITANCE (TA = 25°C, VCC=5V, f = 1MHz)
Item
Input capacitance[A0-A9]
Input capacitance[ W]
Input capacitance[ RAS0 , RAS1]
Input capacitance[ CAS0 - CAS3]
Input/Output capacitance[DQ0-31]
Symbol
Min
Max
Unit
CIN1
CIN2
CIN3
CIN4
CDQ1
-
44
48
40
29
29
pF
pF
pF
pF
pF
AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=5.0V±10%. See notes 1,2.)
Test condition : Vih/Vil=2.4/0.8V, V oh/Vol=2.0/0.8V, Output loading CL=100pF
Parameter
Random read or write cycle time
Access time from RAS
Access time from CAS
Access time from column address
CAS to output in Low-Z
Output buffer turn-off delay from CAS
Transition time(rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in set-up time
Data-in hold time
Refresh period
Write command set-up time
CAS setup time(CAS-before-RAS refresh)
CAS hold time(CAS-before-RAS refresh)
RAS precharge to CAS hold time
Access time from CAS precharge
Symbol
tRC
tRAC
tCAC
tAA
tCLZ
tCEZ
tT
tRP
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWP
tRWL
tCWL
tDS
tDH
tREF
tWCS
tCSR
tCHR
tRPC
tCPA
-5
Min
-6
Max
90
Min
Max
110
Unit
Note
ns
50
60
ns
3,4,10
15
17
ns
3,4,5
25
30
ns
3,10
ns
3
3
3
3
13
3
15
ns
6,11,12
2
50
2
50
ns
2
30
50
40
10K
13
60
ns
10K
17
40
ns
ns
50
ns
8
10K
10
10K
ns
13
20
37
20
45
ns
4
15
25
15
30
ns
10
5
5
ns
0
0
ns
10
10
ns
0
0
ns
8
10
ns
25
30
ns
0
0
ns
0
0
ns
8
0
0
ns
8
10
10
ns
10
10
ns
13
15
ns
13
10
ns
0
0
ns
9
8
10
ns
9
16
16
ms
0
0
ns
5
5
ns
10
10
ns
5
5
30
-6-
7
ns
35
ns
3
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5322204C2W/C2WG
AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=5.0V±10%. See notes 1,2.)
Test condition : Vih/Vil=2.4/0.8V, V oh /Vol=2.0/0.8V, Output loading CL=100pF
Parameter
Hyper page mode cycle time
CAS precharge time(Hyper page cycle)
RAS pulse width(Hyper page cycle)
RAS hold time from CAS precharge
W to RAS precharge time(C-B-R refresh)
W to RAS hold time(C-B-R refresh)
Output data hold time
Output buffer turn off delay from RAS
Output buffer turn off delay from W
W to data delay
W pulse width (Hyper Page Cycle)
Symbol
-5
Min
-6
Max
25
tHPC
tCP
tRASP
tRHCP
tWRP
tWRH
tDOH
tREZ
tWEZ
tWED
tWPE
Min
Max
30
8
10
50
200K
60
Unit
Note
ns
13
ns
200K
ns
30
35
ns
10
10
ns
10
10
ns
5
5
ns
3
13
3
15
ns
6,11,12
3
13
3
15
ns
6,11
15
15
ns
5
5
ns
NOTES
1. An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
2. VIH(min) and V IL(max) are reference levels for measuring
timing of input signals. Transition times are measured
between V IH(min) and V IL(max) and are assumed to be 5ns
for all inputs.
3. Measured with a load equivalent to 2 TTL loads and 100pF.
4. Operation within the tRCD (max) limit insures that tRAC (max)
can be met. tRCD (max) is specified as a reference point only.
If tRCD is greater than the specified tRCD (max) limit, then
access time is controlled exclusively by tCAC .
5. Assumes that tRCD ≥tRCD (max).
6. This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to V OH or
VOL .
8. Either tRCH or tRRH must be satisfied for a read cycle.
9. These parameter are referenced to the CAS leading edge in
early write cycles and to the W leading edge in read-write
cycles.
10. Operation within the tRAD (max) limit insures that tRAC (max)
can be met. tRAD (max) is specified as reference point only. If
tRAD is greater than the specified tRAD (max) limit, then
access time is controlled by tAA .
11. tCEZ (max), tREZ (max), tWEZ (max) and tOEZ (max) define the
time at which the output achieves the open circuit condition
and are not referenced to output voltage level.
12. If RAS goes to high before CAS high going, the open circuit
condtion of the output is achieved by CAS high going. If CAS
goes to high before RAS high going, the open circuit condition of the output is achieved by RAS high going.
13. tASC ≥tCP min
7. tWCS is non-restrictive operating parameter. It is included in
the data sheet as electrical characteristic s only. If
tWCS ≥tWCS (min), the cycle is an early write cycle and the
data out pin will remain high impedance for the duration of
the cycle.
-7-
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5322204C2W/C2WG
READ CYCLE
tRC
tRAS
RAS
VIL -
tCSH
tCRP
CAS
tRP
VIH -
tRCD
tCRP
tRSH
VIH -
tCAS
VIL -
tRAD
tASR
A
VIH VIL -
tRAH
tRAL
tASC
tCAH
ROW
ADDRESS
COLUMN
ADDRESS
tRCH
tRCS
W
tRRH
VIH VIL -
tWEZ
tAA
tCEZ
DQ
VOH VOL -
tRAC
tCAC
tCLZ
OPEN
tREZ
DATA-OUT
Don′t care
Undefined
-8-
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5322204C2W/C2WG
WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
RAS
tRP
VIH VIL -
tCSH
tCRP
CAS
tRSH
VIH -
VIH VIL -
tCRP
tCAS
VIL -
tRAD
tASR
A
tRCD
tRAH
tASC
ROW
ADDRESS
tRAL
tCAH
COLUMN
ADDRESS
tCWL
tRWL
tWCS
W
VIH VIL -
tDS
DQ
tWCH
tWP
VIH VIL -
tDH
DATA-IN
Don′t care
Undefined
-9-
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5322204C2W/C2WG
HYPER PAGE READ CYCLE
tRP
tRASP
RAS
VIH VIL -
¡ó
tCSH
tCRP
CAS
VIL -
tHPC
tCP
tCAS
VIL -
tHPC
tCP
tCAS
tCP
tCAS
tCAS
tRAD
tASR
A
tRCD
VIH -
VIH -
tRHCP
tHPC
tRAH tASC
ROW
ADDR
tCAH
tASC
COLUMN
ADDRESS
tCAH
COLUMN
ADDRESS
tASC
tCAH
COLUMN
ADDR
tASC
tCAH
tREZ
COLUMN
ADDRESS
tRRH
tRCS
W
tRCH
VIH VIL -
tCAC
tAA
tCPA
tAA
tCAC
tDOH
tRAC
DQ
VOH VOL -
VALID
DATA-OUT
tCAC
tAA
tCPA
tDOH
VALID
DATA-OUT
tCPA
tCAC
tAA
tDOH
VALID
DATA-OUT
VALID
DATA-OUT
tCLZ
Don′t care
Undefined
- 10 -
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5322204C2W/C2WG
HYPER PAGE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRP
tRASP
RAS
VIH -
tRHCP
VIL -
¡ó
tHPC
tCRP
CAS
tRCD
tHPC
VIH -
tCAS
VIL -
tRSH
tCP
tCP
tCAS
tCAS
tRAD
¡ó
tCSH
tASR
A
VIH VIL -
tRAH
tASC
tCAH
VIH -
tCAH
ROW
ADDR.
COLUMN
ADDRESS
COLUMN
ADDRESS
tWCH
tWCS
¡ó
tCAH
tWP
tWP
COLUMN
ADDRESS
tWCS
tWCH
¡ó
tWCH
tWP
VIL -
tCWL
tDS
DQ
tASC
¡ó
tWCS
W
tASC
VIH VIL -
tDH
tCWL
tDS
tCWL
tRWL
tDH
tDS
tDH
¡ó
VALID
DATA-IN
VALID
DATA-IN
¡ó
VALID
DATA-IN
Don′t care
Undefined
- 11 -
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5322204C2W/C2WG
RAS - ONLY REFRESH CYCLE*
NOTE : W, OE, DIN = Don't care
DOUT = OPEN
tRC
RAS
VIH -
tRP
tRAS
VIL -
tRPC
tCRP
CAS
VIH VIL -
tASR
A
tCRP
VIH VIL -
tRAH
ROW
ADDR
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE , A = Don't care
tRC
tRP
RAS
VIH VIL -
tRPC
tCP
CAS
tRAS
VIH -
tRPC
tCSR
tCHR
VIL -
tWRP
W
tRP
tWRH
VIH VIL -
tCEZ
DQ
VOH -
OPEN
VOL -
Don′t care
Undefined
* In RAS-only refresh cycle of 64Mb A-dile & B-die, when CAS signal transits from Low to High, the valid data may be cut off.
- 12 -
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5322204C2W/C2WG
HIDDEN REFRESH CYCLE ( READ )
tRC
RAS
tRAS
VIH -
tRP
tRAS
VIL -
tCRP
CAS
tRC
tRP
tRCD
tRSH
tCHR
VIH VIL -
tRAD
tASR
A
VIH VIL -
tRAH
tASC
ROW
ADDRESS
tCAH
COLUMN
ADDRESS
tRCS
W
tRRH
tWRH
tWRP
VIH VIL -
tAA
tCEZ
tCAC
tREZ
tWEZ
tCLZ
tRAC
DQ
VOH VOL -
DATA-OUT
OPEN
Don′t care
Undefined
- 13 -
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5322204C2W/C2WG
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
tRC
RAS
tRAS
VIH -
tRP
tRAS
VIL -
tCRP
CAS
tRC
tRP
tRCD
tRSH
tCHR
VIH VIL -
tRAD
tASR
A
VIH VIL -
tRAH
tASC
ROW
ADDRESS
tCAH
COLUMN
ADDRESS
tWRP
tWCS
W
VIH VIL -
VIH VIL -
tWCH
tWP
tDS
DQ
tWRH
tDH
DATA-IN
Don′t care
Undefined
- 14 -
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5322204C2W/C2WG
CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
tRP
RAS
CAS
VIH -
tRAS
VIL VIH -
tCPT
tCSR
tRSH
tCAS
tCHR
VIL -
tRAL
tASC
A
VIH -
W
COLUMN
ADDRESS
VIL -
READ CYCLE
tCAH
tWRP
tWRH
tRRH
tAA
tRCS
tRCH
tCAC
VIH VIL -
tWEZ
DQ
tCLZ
VOH -
DATA-OUT
VOL -
WRITE CYCLE
W
tCEZ
tREZ
VIH -
tWRP
tRWL
tWRH
tCWL
tWCS
VIL -
tWCH
tWP
tDS
DQ
tDH
VIH DATA-IN
VIL -
Don′t care
Undefined
NOTE : This timing diagram is applied to all devices besides 64M DRAM based modules.
- 15 -
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5322204C2W/C2WG
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Don′t care
tRP
RAS
VIL -
tRPS
tRPC
tRPC
tCP
CAS
tRASS
VIH -
VIH -
tCHS
tCSR
VIL -
tCEZ
DQ
W
VOH -
OPEN
VOL -
VIH VIL -
tWRP
tWRH
TEST MODE IN CYCLE
NOTE : OE , A = Don′t care
tRC
tRP
RAS
tRP
tRAS
VIH VIL -
tRPC
tRPC
tCP
CAS
tCSR
VIH -
tWTS
W
tCHR
VIL -
tWTH
VIH VIL -
tCEZ
DQ
VOH -
OPEN
VOL -
Don′t care
Undefined
- 16 -
Rev. 0.0 (Nov. 1997)
DRAM MODULE
KMM5322204C2W/C2WG
PACKAGE DIMENSIONS
Units : Inches (millimeters)
4.250(107.95)
3.984(101.19)
.133(3.38)
.125 DIA±.002(3.18±.051)
R.062(1.57)
.400(10.16)
.750(19.05)
.250(6.35)
.080(2.03)
R.062±.004(R1.57±.10)
.250(6.35)
.250(6.35)
.125(3.17)
MIN
3.750(95.25)
( Front view )
( Back view )
Gold & Solder Plating Lead
.350(8.89)
MAX
.100(2.54)
.010(.25)MAX
MIN
.050(1.27)
.041±.004(1.04±.10)
.054(1.37)
.047(1.19)
.225(5.71)
MIN
Tolerances : ±.005(.13) unless otherwise specified
NOTE : The used device is 1Mx16 DRAM
DRAM Part No. : KMM5322204C2W/C2WG -- KM416C1204CJ (400 mil)
Revision History
Rev 0.0 : Nov. 1997
- 17 -
Rev. 0.0 (Nov. 1997)