SAMSUNG KMM53616004BK

DRAM MODULE
KMM53616004BK/BKG
KMM53616004BK/BKG EDO Mode
16M x 36 DRAM SIMM Using 16Mx4 & 16Mx1, 4K Refresh, 5V
GENERAL DESCRIPTION
FEATURES
The Samsung KMM53616004B is a 16Mx36bits Dynamic
RAM high density memory module. The Samsung
KMM53616004B consists of eight CMOS 16Mx4bits DRAMs
and four CMOS 16Mx1bit DRAMs in SOJ packages mounted
on a 72-pin glass-epoxy substrate. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for
each DRAM. The KMM53616004B is a Single In-line Memory
Module with edge connections and is intended for mounting
into 72 pin edge connector sockets.
• Part Identification
- KMM53616004BK(4K cycles/64ms Ref, SOJ, Solder)
- KMM53616004BKG(4K cycles/64ms Ref, SOJ, Gold)
• Hyper Page Mode Operation
• CAS-before-RAS & Hidden Refresh capability
• RAS-only refresh capability
• TTL compatible inputs and outputs
• Single +5V±10% power supply
• JEDEC standard PDpin & pinout
PERFORMANCE RANGE
• PCB : Height(1250mil), double sided component
Speed
tRAC
tCAC
tRC
tHPC
-5
50ns
13ns
84ns
20ns
-6
60ns
15ns
104ns
25ns
PIN CONFIGURATIONS
Pin
Symbol
Pin
Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VSS
DQ0
DQ18
DQ1
DQ19
DQ2
DQ20
DQ3
DQ21
Vcc
NC
A0
A1
A2
A3
A4
A5
A6
A10
DQ4
DQ22
DQ5
DQ23
DQ6
DQ24
DQ7
DQ25
A7
A11
Vcc
A8
A9
NC
RAS2
DQ26
DQ8
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
DQ17
DQ35
Vss
CAS0
CAS2
CAS3
CAS1
RAS0
NC
NC
W
NC
DQ9
DQ27
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
DQ13
DQ31
Vcc
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16
NC
PD1
PD2
PD3
PD4
NC
Vss
PIN NAMES
Pin Name
Function
A0 - A11
Address Inputs
DQ0 - DQ35
Data In/Out
W
Read/Write Enable
RAS0, RAS2
Row Address Strobe
CAS0 - CAS3
Column Address Strobe
PD1 -PD4
Presence Detect
Vcc
Power(+5V)
Vss
Ground
NC
No Connection
PRESENCE DETECT PINS (Optional)
Pin
50NS
60NS
PD1
PD2
PD3
PD4
Vss
NC
Vss
Vss
Vss
NC
NC
NC
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
DRAM MODULE
KMM53616004BK/BKG
FUNCTIONAL BLOCK DIAGRAM
CAS0
RAS0
CAS
RAS
OE
DQ1
DQ2
DQ3
W A0-A11 DQ4
DQ0
DQ1
DQ2
DQ3
CAS
RAS
OE
DQ1
DQ2
DQ3
W A0-A11 DQ4
DQ4
DQ5
DQ6
DQ7
U0
U1
U2
CAS
W
A0-A11
RAS
CAS1
DQ1
DQ2
DQ3
W A0-A11 DQ4
DQ9
DQ10
DQ11
DQ12
CAS
RAS
OE
DQ1
DQ2
U4
DQ3
W A0-A11 DQ4
DQ13
DQ12
DQ15
DQ16
U3
D
Q
DQ17
CAS
RAS
OE
DQ1
DQ2
DQ3
W A0-A11 DQ4
DQ18
DQ19
DQ20
DQ21
CAS
RAS
OE
DQ1
DQ2
DQ3
W A0-A11 DQ4
DQ22
DQ23
DQ24
DQ25
U6
U7
U8
CAS
RAS W A0-A11
CAS3
DQ8
CAS
RAS
OE
U5
CAS
RAS W A0-A11
CAS2
RAS2
D
Q
D
Q
DQ26
CAS
RAS
OE
DQ1
DQ2
U9
DQ3
W A0-A11 DQ4
DQ27
DQ28
DQ29
DQ30
CAS
RAS
OE
DQ1
DQ2
DQ3
W A0-A11 DQ4
DQ31
DQ32
DQ33
DQ34
U10
U11
CAS
RAS W A0-A11
D
Q
DQ35
W
A0-A11
Vcc
0.1 or 0.22uF Capacitor
for each DRAM
Vss
To all DRAMs
DRAM MODULE
KMM53616004BK/BKG
ABSOLUTE MAXIMUM RATINGS *
Item
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
Power Dissipation
Short Circuit Output Current
Symbol
Rating
Unit
VIN, VOUT
VCC
Tstg
Pd
IOS
-1 to +7.0
-1 to +7.0
-55 to +125
12
50
V
V
°C
W
mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to V SS, TA = 0 to 70°C)
Item
Symbol
Min
Typ
Max
Unit
VCC
VSS
VIH
VIL
4.5
0
2.4
5.0
0
-
5.5
0
VCC*1
0.8
V
V
V
V
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
-1.0*2
*1 : VCC+2.0V at pulse width≤20ns, which is measured at VCC.
*2 : -2.0V at pulse width≤20ns, whcih is measured at VSS.
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted)
Symbol
Speed
ICC1
KMM53616004BK/BKG
Unit
Min
Max
-5
-6
-
1320
1200
mA
mA
ICC2
Don′t care
-
24
mA
ICC3
-5
-6
-
1320
1200
mA
mA
ICC4
-5
-6
-
1200
1080
mA
mA
ICC5
Don′t care
-
12
mA
ICC6
-5
-6
-
1320
1200
mA
mA
II(L)
IO(L)
Don′t care
-10
-5
10
5
uA
uA
VOH
VOL
Don′t care
2.4
-
0.4
V
V
ICC1 : Operating Current * (RAS, CAS, Address cycling @tRC=min)
ICC2 : Standby Current (RAS=CAS=W=VIH)
ICC3 : RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min)
ICC4 : Hyper Page Mode Current * (RAS=VIL, CAS cycling : tHPC=min)
ICC5 : Standby Current (RAS=CAS=W=Vcc-0.2V)
ICC6 : CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min)
I(IL) : Input Leakage Current (Any input 0≤VIN≤Vcc+0.5V, all other pins not under test=0 V)
I(OL) : Output Leakage Current(Data Out is disabled, 0V≤VOUT≤Vcc)
VOH : Output High Voltage Level (IOH = -5mA)
VOL : Output Low Voltage Level (IOL = 4.2mA)
* NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one EDO mode cycle time, tHPC.
DRAM MODULE
KMM53616004BK/BKG
CAPACITANCE (TA = 25°C, VCC=5V, f = 1MHz)
Item
Symbol
Input capacitance[A0-A11]
Input capacitance[W]
Input capacitance[RAS0, RAS2]
Input capacitance[CAS0 - CAS3]
Input/Output capacitance[DQ0-35]
CIN1
CIN2
CIN3
CIN4
CDQ
Min
Max
Unit
-
70
94
52
31
17
pF
pF
pF
pF
pF
AC CHARACTERISTICS (0°C≤TA≤70°C, Vcc=5.0V±10%. See notes 1,2.)
Test condition : Vih/Vil=2.4/0.4V, Voh/Vol=2.0/0.8V, output loading CL=100pF
Parameter
Random read or write cycle time
Access time from RAS
Access time from CAS
Access time from column address
CAS to output in Low-Z
Output buffer turn-off delay from CAS
Transition time(rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold referenced to CAS
Read command hold referenced to RAS
Write command set-up time
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data set-up time
Data hold time
Refresh period
CAS setup time (CAS-before-RAS refresh)
CAS hold time (CAS-before-RAS refresh)
RAS to CAS precharge time
Access time from CAS precharge
Symbol
tRC
tRAC
tCAC
tAA
tCLZ
tCEZ
tT
tRP
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCS
tWCH
tWP
tRWL
tCWL
tDS
tDH
tREF
tCSR
tCHR
tRPC
tCPA
-5
Min
-6
Max
84
Min
Max
104
Unit
Note
ns
50
60
ns
3,4,10
13
15
ns
3,4,5
30
ns
3,10
ns
3
25
3
3
3
13
3
13
ns
6,12
1
50
1
50
ns
2
30
50
40
10K
13
60
ns
10K
15
38
ns
ns
45
ns
8
10K
10
10K
ns
4
20
37
20
45
ns
9
15
25
15
30
ns
5
5
ns
0
0
ns
10
10
ns
0
0
ns
8
10
ns
25
30
ns
0
0
ns
0
0
ns
8
0
0
ns
8
7
0
0
ns
10
10
ns
10
10
ns
13
15
ns
8
10
ns
0
0
ns
9
ns
9
8
10
64
64
ms
5
5
ns
10
10
ns
5
5
ns
28
35
ns
3
DRAM MODULE
KMM53616004BK/BKG
AC CHARACTERISTICS (0°C≤TA≤70°C, Vcc=5.0V±10%. See notes 1,2.)
Test condition : Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V, output loading CL=100pF
Parameter
Hyper page mode cycle time
CAS precharge time (Hyper page cycle)
RAS pulse width (Hyper page cycle)
RAS hold time from CAS precharge
W to RAS precharge time(C-B-R refresh)
W to RAS hold time(C-B-R refresh)
Output data hold time
Output buffer turn off delay from RAS
Output buffer turn off delay from W
W to data delay
W pulse width
Symbol
tHPC
tCP
tRASP
tRHCP
tWRP
tWRH
tDOH
tREZ
tWEZ
tWED
tWPE
-5
Min
-6
Max
Min
Max
Unit
Note
11
20
25
ns
8
10
ns
50
200K
60
200K
ns
30
35
ns
10
10
ns
10
10
ns
5
5
ns
3
13
3
15
ns
6,12
3
13
3
15
ns
6
15
15
ns
5
5
ns
NOTES
1. An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and
are assumed to be 5ns for all inputs.
3. Measured with a load equivalent to 2 TTL loads and 100pF.
4. Operation within the tRCD(max) limit insures that tRAC(max)
can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then
access time is controlled exclusively by tCAC.
5. Assumes that tRCD≥tRCD(max).
6. This parameter defines the time at which theoutput achieves
the open circuit and is not referenced for VOH or VOL
7. tWCS is non-restrictive operating parameter. It is included in
the data sheet as electrical characteristics only. If
tWCS≥tWCS(min), the cycle is an early write cycle and the
data out pin will remain high impedance for the duration of
the cycle.
8. Either tRCH or tRRH must be satisfied for a read cycle.
9. These parameters are referenced to the CAS leading edge in
early write cycles.
10. Operation within the tRAD(max) limit insures that tRAC(max)
can be met. tRAD(max) is specified as reference point only. If
tRAD is greater than the specified tRAD(max) limit access time
is controlled by tAA.
11. tASC≥6ns, Assume tT=2.0ns.
12. If RAS goes high before CAS high going, the open circuit
condition of the output is achieved by CAS high going. If CAS
goes high before RAS high going , the open circuit condition
of the output is achieved by RAS going.
DRAM MODULE
KMM53616004BK/BKG
READ CYCLE
tRC
tRAS
RAS
VIL -
tCSH
tCRP
CAS
tRP
VIH -
tRCD
tCRP
tRSH
VIH -
tCAS
VIL -
tRAD
tASR
A
VIH VIL -
tRAH
tRAL
tASC
tCAH
COLUMN
ADDRESS
ROW
ADDRESS
tRCH
tRCS
W
tRRH
VIH VIL -
tWEZ
tCEZ
tAA
OE
VIH -
tOEZ
tOEA
VIL -
tOLZ
DQ
VOH VOL -
tRAC
OPEN
tCAC
tCLZ
tREZ
DATA-OUT
Don′t care
Undefined
DRAM MODULE
KMM53616004BK/BKG
WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
RAS
tRP
VIH VIL -
tCSH
tCRP
CAS
tRSH
VIH VIL -
VIH VIL -
tCRP
tCAS
tRAD
tASR
A
tRCD
tRAH
tASC
tRAL
tCAH
COLUMN
ADDRESS
ROW
ADDRESS
tCWL
tRWL
tWCS
W
OE
VIH VIL -
VIH VIL -
tDS
DQ
tWCH
tWP
VIH VIL -
tDH
DATA-IN
Don′t care
Undefined
DRAM MODULE
KMM53616004BK/BKG
WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : D OUT = OPEN
tRC
tRAS
RAS
VIL -
tCSH
tCRP
CAS
tRP
VIH -
tRCD
tRSH
tCAS
VIH -
tCRP
VIL -
tRAD
tRAL
tASR
A
VIH VIL -
tRAH
ROW
ADDRESS
tASC
tCAH
COLUMN
ADDRESS
tCWL
tRWL
W
OE
tWP
VIH VIL -
VIH VIL -
tOED
tDS
DQ
VIH -
tOEH
tDH
DATA-IN
VIL -
Don′t care
Undefined
DRAM MODULE
KMM53616004BK/BKG
READ - MODIFY - WRITE CYCLE
tRWC
tRAS
RAS
VIL -
tCRP
CAS
tRP
VIH -
tRCD
tRSH
VIH -
tCAS
VIL -
tRAD
tASR
tRAH
tASC
tCAH
tCSH
A
VIH VIL -
ROW
ADDR
COLUMN
ADDRESS
tAWD
tRWL
tCWD
W
tCWL
VIH -
tWP
VIL -
tRWD
OE
tOEA
VIH VIL -
tOLZ
tCLZ
tCAC
tAA
DQ
VI/OH VI/OL -
tOED
tOEZ
tRAC
VALID
DATA-OUT
tDS
tDH
VALID
DATA-IN
Don′t care
Undefined
DRAM MODULE
KMM53616004BK/BKG
HYPER PAGE READ CYCLE
tRP
tRASP
RAS
VIH VIL -
¡ó
tCSH
tCRP
CAS
VIL -
tHPC
tCP
tCAS
VIL -
tHPC
tCP
tCAS
tCP
tCAS
tCAS
tRAD
tASR
A
tRCD
VIH -
VIH -
tRHCP
tHPC
tRAH tASC
ROW
ADDR
tCAH
tASC
COLUMN
ADDRESS
tCAH
COLUMN
ADDRESS
tASC
tCAH
COLUMN
ADDR
tASC
tCAH
tREZ
COLUMN
ADDRESS
tRRH
tRCS
W
tRCH
VIH VIL -
tCAC
tAA
tCPA
tCAC
tAA
OE
VIH -
tCAC
tAA
tCPA
tOCH
tOEA
tCHO
tOEP
tOEA
VIL -
tOEP
tCAC
tDOH
tRAC
DQ
tCPA
tCAC
tAA
VOH VOL -
VALID
DATA-OUT
tOLZ
tCLZ
tOEZ
tOEA
tOEZ
tOEZ
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
Don′t care
Undefined
DRAM MODULE
KMM53616004BK/BKG
HYPER PAGE WRITE CYCLE ( EARLY WRITE )
NOTE : D OUT = OPEN
tRP
tRASP
RAS
VIH -
tRHCP
VIL -
¡ó
tHPC
tCRP
CAS
tRCD
tHPC
tCP
VIH -
tCAS
VIL -
tRSH
tCP
tCAS
tCAS
tRAD
¡ó
tCSH
tASR
A
VIH VIL -
tRAH
tASC
tCAH
VIH -
ROW
ADDR.
COLUMN
ADDRESS
COLUMN
ADDRESS
tWCH
tWCS
tWP
tCAH
¡ó
COLUMN
ADDRESS
tWCS
¡ó
tWCH
tWP
VIL -
tCWL
VIL -
VIH VIL -
tCWL
tRWL
¡ó
VIH -
¡ó
tDS
DQ
tASC
tWCH
tWP
tCWL
OE
tCAH
¡ó
tWCS
W
tASC
tDH
tDS
tDH
tDS
tDH
¡ó
VALID
DATA-IN
VALID
DATA-IN
¡ó
VALID
DATA-IN
Don′t care
Undefined
DRAM MODULE
KMM53616004BK/BKG
HYPER PAGE READ-MODIFY-WRITE CYCLE
RAS
tCSH
tHPRWC
tRCD
tCAS
VIL -
VIH VIL -
tCAS
tRAD
tRAH
ROW
ADDR
tRAL
tCAH
tASC
tCAH
tASC
COL.
ADDR
COL.
ADDR
tRCS
W
tCRP
tCP
VIH -
tASR
A
tRSH
VIL -
tCRP
CAS
tRWL
tCWL
tCWL
VIH -
tWP
VIL -
tWP
tCWD
tCWD
tAWD
tRWD
OE
tRP
tRASP
VIH -
VIH -
tAWD
tCPWD
tOEA
tOEA
VIL -
tOED
tOED
tCAC
tAA
tDH
tOEZ
tCAC
tAA
tDS
tDH
tOEZ
tDS
tRAC
DQ
VI/OH VI/OL -
tCLZ
tCLZ
tOLZ
VALID
DATA-OUT
VALID
DATA-IN
tOLZ
VALID
DATA-OUT
VALID
DATA-IN
Don′t care
Undefined
DRAM MODULE
KMM53616004BK/BKG
HYPER PAGE READ AND WRITE MIXED CYCLE
tRP
tRASP
RAS
VIH -
READ(tCAC)
READ(tCPA)
tHPC
tHPC
tCP
tCP
CAS
VIH VIL -
VIH VIL -
tCAS
tRAD
tASR
A
tRAH
tASC
ROW
ADDR
tCAH
COLUMN
ADDRESS
tRCS
W
READ(tAA)
WRITE
VIL -
tCAS
tRCS
tCAH
tASC
COLUMN
ADDRESS
tRCH
tCAS
tCAS
tCAH
tASC
tHPC
tCP
COL.
ADDR
tRCH
tASC
tCAH
COL.
ADDR
tWCH
tRCH
tWCS
VIH VIL -
tWPE
tCLZ
tWED
tCPA
OE
VIH VIL -
tOEA
tCAC
tAA
DQ
VI/OH VI/OL -
tWEZ
tDH
tWEZ
tDS
VALID
VALID
DATA-IN
tREZ
tAA
tRAC
VALID
DATA-OUT
DATA-OUT
VALID
DATA-OUT
Don′t care
Undefined
DRAM MODULE
KMM53616004BK/BKG
RAS - ONLY REFRESH CYCLE*
NOTE : W, OE, DIN = Don′t care
DOUT = OPEN
tRC
RAS
VIH -
tRP
tRAS
VIL -
tRPC
tCRP
CAS
VIH VIL -
tASR
A
tCRP
VIH VIL -
tRAH
ROW
ADDR
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE , A = Don′t care
tRC
tRP
RAS
VIH VIL -
tRPC
tCP
CAS
tRAS
VIH -
tRPC
tCSR
tCHR
VIL -
tWRP
W
tRP
tWRH
VIH VIL -
tCEZ
DQ
VOH VOL -
OPEN
Don′t care
Undefined
* In RAS-only refresh cycle of 64Mb A-dile & B-die, when CAS signal transits from Low to High, the valid data may be cut off.
DRAM MODULE
KMM53616004BK/BKG
HIDDEN REFRESH CYCLE ( READ )
tRC
RAS
tRAS
VIH -
tRP
tRAS
VIL -
tCRP
CAS
tRC
tRP
tRCD
tRSH
tCHR
VIH VIL -
tRAD
tASR
A
VIH VIL -
tRAH
tASC
ROW
ADDRESS
tCAH
COLUMN
ADDRESS
tRCS
W
tRRH
tWRH
tWRP
VIH VIL -
tAA
OE
VIH -
tOEA
VIL -
tCEZ
tOLZ
tCAC
tREZ
tWEZ
tCLZ
tRAC
DQ
VOH VOL -
OPEN
tOEZ
DATA-OUT
Don′t care
Undefined
DRAM MODULE
KMM53616004BK/BKG
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
tRC
RAS
tRAS
VIH -
tRP
tRAS
VIL -
tCRP
CAS
tRC
tRP
tRCD
tRSH
tCHR
VIH VIL -
tRAD
tASR
A
VIH VIL -
tRAH
tASC
ROW
ADDRESS
tCAH
COLUMN
ADDRESS
tWRH
tWRP
tWCS
W
OE
VIH VIL -
VIH VIL -
tDS
DQ
tWCH
tWP
VIH VIL -
tDH
DATA-IN
Don′t care
Undefined
DRAM MODULE
KMM53616004BK/BKG
CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
tRP
RAS
CAS
VIH -
tRAS
VIL VIH -
tCPT
tCSR
tRSH
tCAS
tCHR
VIL -
tRAL
tASC
A
VIH VIL -
READ CYCLE
W
OE
tWRP
tWRH
tRRH
tAA
tRCS
tRCH
tCAC
VIH VIL VIH VIL -
tOEA
tCLZ
VOH -
DQ
tCAH
COLUMN
ADDRESS
tOEZ
DATA-OUT
VOL -
WRITE CYCLE
W
tCEZ
tREZ
tWRP
tRWL
tWRH
tCWL
VIH -
tWCS
tWCH
VIL -
tWP
OE
VIH VIL -
tDS
DQ
tDH
VIH DATA-IN
VIL -
READ-MODIFY-WRITE
tWRP
W
tWRH
tAWD
tRCS
tCWL
tCWD
VIH -
tRWL
tWP
tCAC
VIL -
tAA
tOEA
OE
VIH -
tOED
VIL -
tCLZ
DQ
tOEZ
tDH
tDS
VI/OH VI/OL VALID
DATA-OUT
VALID
DATA-IN
NOTE : This timing diagram is applied to all devices besides 64M DRAM based modules.
Don′t care
Undefined
tWEZ
DRAM MODULE
KMM53616004BK/BKG
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Don′t care
tRP
RAS
VIL -
tRPS
tRPC
tRPC
tCP
CAS
tRASS
VIH -
VIH -
tCHS
tCSR
VIL -
tCEZ
DQ
W
VOH -
OPEN
VOL -
VIH VIL -
tWRP
tWRH
TEST MODE IN CYCLE
NOTE : OE , A = Don′t care
tRC
tRP
RAS
tRP
tRAS
VIH VIL -
tRPC
tRPC
tCP
CAS
tCSR
VIH -
tWTS
W
tCHR
VIL -
tWTH
VIH VIL -
tCEZ
DQ
VOH VOL -
OPEN
Don′t care
Undefined
DRAM MODULE
KMM53616004BK/BKG
PACKAGE DIMENSIONS
Units : Inches (millimeters)
4.250(107.95)
3.984(101.19)
.133(3.38)
.125 DIA±.002(3.18 ±.051)
R.062(1.57)
.400(10.16)
1.250(31.75)
.250(6.35)
.080(2.03)
.250(6.35)
R.062±.004(R1.57 ±.10)
.125(3.17)
MIN
.250(6.35)
3.750(95.25)
( Front view )
.350(8.89)
MAX
.054(1.37)
.047(1.19)
( Back view )
Gold/Solder Plating Lead
.100(2.54)
.010(.25)MAX
MIN
.050(1.27)
.041±.004(1.04 ±.10)
Tolerances :±.005(.13) unless otherwise specified
NOTE : The used device is 16Mx4 DRAM & 16Mx1 DRAM, SOJ
DRAM Part No. : KMM53616004BK/BKG -- KM44C16104BK
KM41C16004CK