SAMSUNG KM48V8004C

KM48V8004C,KM48V8104C
CMOS DRAM
8M x 8bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 8,388,608 x 8 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random
access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -5 or -6), power consumption(Normal
or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh
capabilities. Furthermore, Self-refresh operation is available in L-version. This 8Mx8 EDO Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability.
• Extended Data Out Mode operation
FEATURES
• CAS-before-RAS refresh capability
• Part Identification
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
- KM48V8004C/C-L(3.3V, 8K Ref.)
- KM48V8104C/C-L(3.3V, 4K Ref.)
• Fast parallel test mode capability
• LVTTL(3.3V) compatible inputs and outputs
• Active Power Dissipation
• Early Write or output enable controlled write
Unit : mW
• JEDEC Standard pinout
Speed
8K
4K
• Available in Plastic SOJ and TSOP(II) packages
-45
324
432
• +3.3V±0.3V power supply
-5
288
396
-6
252
360
• Refresh Cycles
Refresh
cycle
KM48V8004C*
8K
KM48V8104C
FUNCTIONAL BLOCK DIAGRAM
Refresh time
Normal
L-ver
64ms
128ms
4K
RAS
CAS
W
* Access mode & RAS only refresh mode
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)
CAS-before-RAS & Hidden refresh mode
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
¡Ü
Control
Clocks
Refresh Timer
Performance Range:
Speed
tRAC
tCAC
tRC
tHPC
-45
45ns
12ns
74ns
17ns
-5
50ns
13ns
84ns
20ns
-6
60ns
15ns
104ns
25ns
Row Decoder
Refresh Control
Refresh Counter
A0~A12
(A0~A11)*1
Row Address Buffer
A0~A9
(A0~A10)*1
Col. Address Buffer
Vcc
Vss
VBB Generator
Memory Array
8,388,608 x 8
Cells
Column Decoder
Note) *1 : 4K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
Sense Amps & I/O
Part
NO.
Data in
Buffer
DQ0
to
DQ7
Data out
Buffer
OE
KM48V8004C,KM48V8104C
CMOS DRAM
PIN CONFIGURATION (Top Views)
•KM48V80(1)04CS
•KM48V80(1)04CK
VCC
DQ0
DQ1
DQ2
DQ3
N.C
VCC
W
RAS
A0
A1
A2
A3
A4
A5
VCC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSS
DQ7
DQ6
DQ5
DQ4
VSS
CAS
OE
A12(N.C)*
A11
A10
A9
A8
A7
A6
VSS
VCC
DQ0
DQ1
DQ2
DQ3
N.C
VCC
W
RAS
A0
A1
A2
A3
A4
A5
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
(S : 400mil TSOP(II))
(K : 400mil SOJ)
* (N.C) : N.C for 4K Refresh product
Pin Name
Pin Function
A0 - A12
Address Inputs(8K Product)
A0 - A11
Address Inputs(4K Product)
DQ0 - 7
Data In/Out
VSS
Ground
RAS
Row Address Strobe
CAS
Column Address Strobe
W
Read/Write Input
OE
Data Output Enable
VCC
Power(+3.3V)
N.C
No Connection
VSS
DQ7
DQ6
DQ5
DQ4
VSS
CAS
OE
A12(N.C)*
A11
A10
A9
A8
A7
A6
VSS
KM48V8004C,KM48V8104C
CMOS DRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Units
VIN,VOUT
-0.5 to +4.6
V
Voltage on VCC supply relative to VSS
VCC
-0.5 to +4.6
V
Storage Temperature
Tstg
-55 to +150
°C
Power Dissipation
PD
1
W
Short Circuit Output Current
IOS
50
mA
Voltage on any pin relative to VSS
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, T A= 0 to 70°C)
Parameter
Symbol
Min
Typ
Max
Units
Supply Voltage
VCC
3.0
3.3
3.6
V
Ground
VSS
0
0
0
V
Input High Voltage
VIH
2.0
-
VCC+0.3*1
V
Input Low Voltage
VIL
-0.3*2
-
0.8
V
*1 : VCC+1.3V at pulse width≤15ns which is measured at VCC
*2 : -1.3 at pulse width≤15ns which is measured at VSS
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Parameter
Symbol
Min
Max
Units
Input Leakage Current (Any input 0≤VIN≤VCC+0.3V,
all other pins not under test=0 Volt)
II(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0V≤VOUT≤VCC)
IO(L)
-5
5
uA
Output High Voltage Level(IOH=-2mA)
VOH
2.4
-
V
Output Low Voltage Level(IOL=2mA)
VOL
-
0.4
V
KM48V8004C,KM48V8104C
CMOS DRAM
DC AND OPERATING CHARACTERISTICS (Continued)
Symbol
Power
Max
Speed
Units
KM48V8004C
KM48V8104C
ICC1
Don′t care
-45
-5
-6
90
80
70
120
110
100
mA
mA
mA
ICC2
Normal
L
Don′t care
1
1
1
1
mA
mA
ICC3
Don′t care
-45
-5
-6
90
80
70
120
110
100
mA
mA
mA
ICC4
Don′t care
-45
-5
-6
100
90
80
100
90
80
mA
mA
mA
ICC5
Normal
L
Don′t care
500
200
500
200
uA
uA
ICC6
Don′t care
-45
-5
-6
120
110
100
120
110
100
mA
mA
mA
ICC7
L
Don′t care
350
350
uA
ICCS
L
Don′t care
350
350
uA
ICC1* : Operating Current (RAS and CAS, Address cycling @tRC=min.)
ICC2 : Standby Current (RAS=CAS=W=VIH)
ICC3* : RAS-only Refresh Current (CAS=VIH, RAS cycling @tRC=min.)
ICC4* : Extended Data Out Mode Current (RAS=VIL, CAS, Address cycling @tHPC=min.)
ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V)
ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min)
ICC7 : Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=CAS-before-RAS cycling or 0.2V
W, OE=VIH, Address=Don′t care, DQ=Open, TRC=31.25us
ICCS : Self Refresh Current
RAS=CAS=0.2V, W=OE=A0 ~ A12(A11)=VCC-0.2V or 0.2V, DQ0 ~ DQ7=VCC-0.2V, 0.2V or Open
*Note : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one EDO mode cycle time, tHPC.
KM48V8004C,KM48V8104C
CMOS DRAM
CAPACITANCE (TA=25°C, VCC=3.3V, f=1MHz)
Parameter
Symbol
Min
Max
Units
Input capacitance [A0 ~ A12]
CIN1
-
5
pF
Input capacitance [RAS, CAS, W, OE]
CIN2
-
7
pF
Output capacitance [DQ0 - DQ7]
CDQ
-
7
pF
AC CHARACTERISTICS (0°C≤TA≤70°C, See note 2)
Test condition : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V
Parameter
-45
Symbol
Min
-5
Max
Min
-6
Max
Min
Units
Note
Max
Random read or write cycle time
tRC
74
84
104
ns
Read-modify-write cycle time
tRWC
101
113
138
ns
Access time from RAS
tRAC
45
50
60
ns
3,4,10
Access time from CAS
tCAC
12
13
15
ns
3,4,5
Access time from column address
tAA
23
25
30
ns
3,10
CAS to output in Low-Z
tCLZ
3
ns
3
Output buffer turn-off delay from CAS
tCEZ
3
ns
6,13
OE to output in Low-Z
tOLZ
3
ns
3
Transition time (rise and fall)
tT
1
ns
2
RAS precharge time
tRP
25
RAS pulse width
tRAS
45
RAS hold time
tRSH
8
8
10
ns
CAS hold time
tCSH
35
38
40
ns
CAS pulse width
tCAS
7
5K
8
10K
10
10K
ns
14
RAS to CAS delay time
tRCD
11
33
11
37
14
45
ns
4
RAS to column address delay time
tRAD
9
22
9
25
12
30
ns
10
CAS to RAS precharge time
tCRP
5
5
5
ns
Row address set-up time
tASR
0
0
0
ns
Row address hold time
tRAH
7
7
10
ns
Column address set-up time
tASC
0
0
0
ns
Column address hold time
tCAH
7
7
10
ns
Column address to RAS lead time
tRAL
23
25
30
ns
Read command set-up time
tRCS
0
0
0
ns
Read command hold time referenced to CAS
tRCH
0
0
0
ns
8
Read command hold time referenced to RAS
tRRH
0
0
0
ns
8
Write command hold time
tWCH
7
7
10
ns
Write command pulse width
tWP
6
7
10
ns
Write command to RAS lead time
tRWL
8
8
10
ns
Write command to CAS lead time
tCWL
7
7
10
ns
Data set-up time
tDS
0
0
0
ns
3
13
3
3
13
3
50
1
50
13
3
50
30
10K
3
1
50
40
10K
60
ns
10K
ns
9
KM48V8004C,KM48V8104C
CMOS DRAM
AC CHARACTERISTICS (Continued)
Parameter
-45
Symbol
Min
-5
Max
7
Min
-6
Max
7
Min
Units
Note
ns
9
Max
Data hold time
tDH
Refresh period (Normal)
tREF
64
64
64
ms
Refresh period (L-ver)
tREF
128
128
128
ms
Write command set-up time
tWCS
0
0
0
ns
7
CAS to W delay time
tCWD
24
27
32
ns
7
RAS to W delay time
tRWD
57
64
77
ns
7
Column address to W delay time
tAWD
35
39
47
ns
7
CAS set-up time (CAS -before-RAS refresh)
tCSR
5
5
5
ns
CAS hold time (CAS -before-RAS refresh)
tCHR
10
10
10
ns
RAS to CAS precharge time
tRPC
5
5
5
ns
Access time from CAS precharge
tCPA
Hyper Page cycle time
tHPC
17
20
Hyper Page read-modify-write cycle time
tHPRWC
47
CAS precharge time (Hyper page cycle)
tCP
6.5
RAS pulse width (Hyper page cycle)
tRASP
45
RAS hold time from CAS precharge
tRHCP
24
OE access time
tOEA
OE to data delay
tOED
8
10
13
ns
CAS precharge to W delay time
tCPWD
36
41
52
ns
Output buffer turn off delay time from OE
tOEZ
3
OE command hold time
tOEH
5
5
5
ns
Write command set-up time (Test mode in)
tWTS
10
10
10
ns
11
Write command hold time (Test mode in)
tWTH
10
10
10
ns
11
W to RAS precharge time (C-B-R refresh)
tWRP
10
10
10
ns
W to RAS hold time (C-B-R refresh)
tWRH
10
10
10
ns
Output data hold time
tDOH
4
5
5
ns
Output buffer turn off delay from RAS
tREZ
3
13
3
13
3
13
ns
6,13
Output buffer turn off delay from W
tWEZ
3
13
3
13
3
13
ns
6
W to data delay
tWED
8
15
15
ns
OE to CAS hold time
tOCH
5
5
5
ns
CAS hold time to OE
tCHO
5
5
5
ns
OE precharge time
tOEP
5
5
5
ns
W pulse width (Hyper Page Cycle)
tWPE
5
5
5
ns
RAS pulse width (C-B-R self refresh)
tRASS
100
100
100
us
15,16,17
RAS precharge time (C-B-R self refresh)
tRPS
74
90
110
ns
15,16,17
CAS hold time (C-B-R self refresh)
tCHS
-50
-50
-50
ns
15,16,17
24
200K
10
28
ns
3
25
ns
14
47
56
ns
14
7
10
ns
50
200K
30
12
11
35
60
35
13
3
200K
13
ns
15
3
ns
13
ns
ns
3
6
KM48V8004C,KM48V8104C
CMOS DRAM
TEST MODE CYCLE
Parameter
( Note 11 )
-45
Symbol
Min
-5
Max
Min
-6
Max
Min
Units
Note
Max
Random read or write cycle time
tRC
79
89
109
ns
Read-modify-write cycle time
tRWC
110
121
145
ns
Access time from RAS
tRAC
50
55
65
ns
3,4,10,12
Access time from CAS
tCAC
17
18
20
ns
3,4,5,12
Access time from column address
tAA
28
30
35
ns
3,10,12
RAS pulse width
tRAS
50
10K
55
10K
65
10K
ns
CAS pulse width
tCAS
12
10K
13
10K
15
10K
ns
RAS hold time
tRSH
18
18
20
ns
CAS hold time
tCSH
39
43
50
ns
Column Address to RAS lead time
tRAL
28
30
35
ns
CAS to W delay time
tCWD
29
35
39
ns
7
RAS to W delay time
tRWD
62
72
84
ns
7
Column Address to W delay time
tAWD
40
47
54
ns
7
Hyper Page cycle time
tHPC
22
25
30
ns
14
Hyper Page read-modify-write cycle time
tHPRWC
52
53
61
ns
14
RAS pulse width (Hyper page cycle)
tRASP
50
Access time from CAS precharge
tCPA
29
OE access time
tOEA
17
OE to data delay
tOED
13
18
20
ns
OE command hold time
tOEH
13
18
20
ns
200K
55
200K
65
200K
ns
33
40
ns
3
18
20
ns
3
KM48V8004C,KM48V8104C
CMOS DRAM
NOTES
1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition
times are measured between VIH(min) and VIL(max) and are assumed to be 2ns for all inputs.
3. Measured with a load equivalent to 1 TTL load and 100pF.
4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
5. Assumes that tRCD≥tRCD(max).
6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.
7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electric characteristics only. If tWCS≥tWCS(min), the cycles is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If tCWD≥tCWD(min), tRWD≥tRWD(min) and tAWD≥tAWD(min), then the cycle is a read-modify-write cycle
and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the
condition of the data out is indeterminate.
8. Either tRCH or tRRH must be satisfied for a read cycle.
9. This parameters are referenced to the CAS falling edge in early write cycles and to the W falling edge in OE controlled write
cycle and read-modify-write cycles.
10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If
tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
11. These specifications are applied in the test mode.
12. In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
13. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going.
If CAS goes high before RAS high going, the open circuit condition of the output is achieved by RAS high going.
14. tASC≥6ns, Assume tT = 2.0ns, if tASC≤6ns, then tHPC(min) and tCAS(min) must be increased by the value of "6ns-tASC".
15. If tRASS≥100us, then RAS precharge time must use tRPS instead of tRP.
16. For RAS-only-Refresh and Burst CAS-before-RAS refresh mode, 4096 cycles(4K/8K) of burst refresh must be executed
within 64ms before and after self refresh, in order to meet refresh specification.
17. For distributed CAS-before-RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before
and after self refresh in order to meet refresh specification.
KM48V8004C,KM48V8104C
CMOS DRAM
READ CYCLE
tRC
tRAS
RAS
VIL -
tCSH
tCRP
CAS
tRP
VIH -
tRCD
tCRP
tRSH
VIH -
tCAS
VIL -
tRAD
tASR
A
VIH VIL -
tRAH
tRAL
tASC
tCAH
COLUMN
ADDRESS
ROW
ADDRESS
tRCH
tRCS
W
tRRH
VIH VIL -
tWEZ
tCEZ
tAA
OE
VIH -
tOEZ
tOEA
VIL -
tOLZ
DQ0 ~ DQ3(7)
VOH VOL -
tRAC
OPEN
tCAC
tCLZ
tREZ
DATA-OUT
Don′t care
Undefined
KM48V8004C,KM48V8104C
CMOS DRAM
WRITE CYCLE ( EARLY WRITE )
NOTE : D OUT = OPEN
tRC
tRAS
RAS
tRP
VIH VIL -
tCSH
tCRP
CAS
tRSH
VIH -
VIH VIL -
tCRP
tCAS
VIL -
tRAD
tASR
A
tRCD
tRAH
tASC
ROW
ADDRESS
tRAL
tCAH
COLUMN
ADDRESS
tCWL
tRWL
tWCS
W
OE
VIH -
tWCH
tWP
VIL -
VIH VIL -
DQ0 ~ DQ3(7)
VIH VIL -
tDS
tDH
DATA-IN
Don′t care
Undefined
KM48V8004C,KM48V8104C
CMOS DRAM
WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : D OUT = OPEN
tRC
tRAS
RAS
VIL -
tCSH
tCRP
CAS
tRP
VIH -
tRCD
tRSH
tCAS
VIH -
tCRP
VIL -
tRAD
tRAL
tASR
A
VIH VIL -
tRAH
ROW
ADDRESS
tASC
tCAH
COLUMN
ADDRESS
tCWL
tRWL
W
OE
tWP
VIH VIL -
VIH VIL -
DQ0 ~ DQ3(7)
VIH VIL -
tOED
tDS
tOEH
tDH
DATA-IN
Don′t care
Undefined
KM48V8004C,KM48V8104C
CMOS DRAM
READ - MODIFY - WRITE CYCLE
tRWC
tRAS
RAS
VIL -
tCRP
CAS
tRP
VIH -
tRCD
tRSH
VIH -
tCAS
VIL -
tRAD
tASR
tRAH
tASC
tCAH
tCSH
A
VIH VIL -
ROW
ADDR
COLUMN
ADDRESS
tAWD
tRWL
tCWD
W
tCWL
VIH -
tWP
VIL -
tRWD
OE
tOEA
VIH VIL -
DQ0 ~ DQ3(7)
VI/OH VI/OL -
tOLZ
tCLZ
tCAC
tAA
tOED
tOEZ
tRAC
VALID
DATA-OUT
tDS
tDH
VALID
DATA-IN
Don′t care
Undefined
KM48V8004C,KM48V8104C
CMOS DRAM
HYPER PAGE READ CYCLE
tRP
tRASP
RAS
VIH VIL -
¡ó
tRHCP
tCSH
tHPC
tCRP
CAS
VIL -
VIH VIL -
tCP
tCAS
VIH -
tCP
tCAS
tHPC
tCP
tCAS
tCAS
tRAD
tASR
A
tRCD
tHPC
tRAH tASC
ROW
ADDR
tCAH
tASC
COLUMN
ADDRESS
tCAH
tASC
COLUMN
ADDRESS
tCAH
COLUMN
ADDR
tASC
tCAH
tREZ
COLUMN
ADDRESS
tRAL
tRCS
W
tRCH
VIH -
tCAC
VIL -
tAA
tCPA
tAA
tCPA
tOCH
VIH -
tOEA
tCPA
tCAC
tCAC
tAA
OE
tRRH
tAA
tCHO
tOEP
tOEA
VIL -
tOEP
tCAC
DQ0 ~ DQ3(7)
VOH VOL -
tDOH
tRAC
VALID
DATA-OUT
tOLZ
tCLZ
tOEZ
tOEA
tOEZ
tOEZ
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
Don′t care
Undefined
KM48V8004C,KM48V8104C
CMOS DRAM
HYPER PAGE WRITE CYCLE ( EARLY WRITE )
NOTE : D OUT = OPEN
tRP
tRASP
RAS
VIH -
tRHCP
VIL -
¡ó
tHPC
tCRP
CAS
tRCD
tHPC
tCP
VIH -
tCAS
VIL -
tRSH
tCP
tCAS
tCAS
tRAD
¡ó
tCSH
tASR
A
VIH VIL -
tRAH
tASC
tCAH
tASC
tCAH
tASC
tCAH
¡ó
ROW
ADDR.
COLUMN
ADDRESS
COLUMN
ADDRESS
¡ó
COLUMN
ADDRESS
tRAL
tWCS
W
VIH -
tWCH
tWCS
tWP
tWP
¡ó
tWCH
tWP
VIL -
tCWL
OE
tWCS
tWCH
tCWL
¡ó
VIH VIL -
DQ0 ~ DQ3(7)
VIH VIL -
tCWL
tRWL
¡ó
tDS
tDH
tDS
tDH
tDS
tDH
¡ó
VALID
DATA-IN
VALID
DATA-IN
¡ó
VALID
DATA-IN
Don′t care
Undefined
KM48V8004C,KM48V8104C
CMOS DRAM
HYPER PAGE READ-MODIFY-WRITE CYCLE
tRP
tRASP
RAS
VIH -
tCSH
tCRP
CAS
tHPRWC
tRCD
tCAS
VIL -
VIH VIL -
tCAS
tRAD
tRAH
ROW
ADDR
tRAL
tCAH
tASC
tCAH
tASC
COL.
ADDR
COL.
ADDR
tRCS
W
tCRP
tCP
VIH -
tASR
A
tRSH
VIL -
tRWL
tCWL
tCWL
VIH -
tWP
VIL -
tWP
tCWD
tCWD
tAWD
tRWD
OE
VIH -
tAWD
tCPWD
tOEA
tOEA
VIL -
tOED
tOED
tCAC
tAA
DQ0 ~ DQ3(7)
VI/OH VI/OL -
tDH
tOEZ
tCAC
tAA
tDS
tDH
tOEZ
tDS
tRAC
tCLZ
tCLZ
tOLZ
VALID
DATA-OUT
VALID
DATA-IN
tOLZ
VALID
DATA-OUT
VALID
DATA-IN
Don′t care
Undefined
KM48V8004C,KM48V8104C
CMOS DRAM
HYPER PAGE READ AND WRITE MIXED CYCLE
tRP
tRASP
RAS
VIH -
READ( tCAC )
READ( tCPA )
tHPC
VIH -
tCP
VIL -
tASR
A
VIH VIL -
tCAS
tRAD
tRAH
tASC
ROW
ADDR
tCAH
COLUMN
ADDRESS
tCP
tCAS
tCAS
tCAS
tCAH
tASC
tRHCP
tHPC
tHPC
tCP
CAS
READ( tAA)
WRITE
VIL -
tCAH
tASC
COLUMN
ADDRESS
COL.
ADDR
tASC
tCAH
COL.
ADDR
tRAL
tRCS
W
tRCH
tRCS
tRCH
tWCH
tRCH
tWCS
VIH VIL -
tWPE
tCLZ
tWED
tCPA
OE
VIH VIL -
DQ0 ~ DQ3(7)
VI/OH VI/OL -
tOEA
tCAC
tAA
tWEZ
tDH
tWEZ
tREZ
tAA
tDS
tCLZ
tRAC
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
Don′t care
Undefined
KM48V8004C,KM48V8104C
CMOS DRAM
RAS - ONLY REFRESH CYCLE*
NOTE : W, OE, DIN = Don′t care
DOUT = OPEN
tRC
VIH -
RAS
tRP
tRAS
VIL -
tRPC
tCRP
tCRP
VIH -
CAS
VIL -
tASR
VIH -
A
VIL -
tRAH
ROW
ADDR
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE , A = Don′t care
tRC
tRP
RAS
VIH VIL -
tRPC
tCP
CAS
tRAS
VIH -
tRPC
tCSR
tCHR
VIL -
tWRP
W
tRP
tWRH
VIH VIL -
DQ0 ~ DQ3(7)
VOH VOL -
tCEZ
OPEN
Don′t care
Undefined
KM48V8004C,KM48V8104C
CMOS DRAM
HIDDEN REFRESH CYCLE ( READ )
tRC
RAS
tRAS
VIH -
tRCD
tRSH
VIL -
tASR
VIH VIL -
tRAH
tRAL
tASC
ROW
ADDRESS
tCAH
COLUMN
ADDRESS
tWRH
tRCS
W
tCHR
VIH -
tRAD
A
tRP
tRAS
VIL -
tCRP
CAS
tRC
tRP
VIH VIL -
tAA
OE
VIH -
tOEA
VIL -
tCEZ
tOLZ
tCAC
tREZ
tWEZ
tCLZ
DQ0 ~ DQ3(7)
VOH VOL -
tRAC
OPEN
tOEZ
DATA-OUT
Don′t care
Undefined
* In Hidden refresh cycle of 64Mb A-dile & B-die, when CAS signal transits from Low to High, the valid data may be cut off.
KM48V8004C,KM48V8104C
CMOS DRAM
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : D OUT = OPEN
tRC
RAS
tRAS
VIH -
tRCD
tRSH
tCHR
VIH VIL -
tRAD
tASR
A
tRP
tRAS
VIL -
tCRP
CAS
tRC
tRP
VIH VIL -
tRAH
tASC
ROW
ADDRESS
tRAL
tCAH
COLUMN
ADDRESS
tWRH
tWRP
tWCS
W
OE
VIH -
tWCH
tWP
VIL -
VIH VIL -
tDS
DQ0 ~ DQ3(7)
VIH VIL -
tDH
DATA-IN
Don′t care
Undefined
KM48V8004C,KM48V8104C
CMOS DRAM
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Don′t care
tRP
RAS
VIL -
tRPC
VIH -
tCHS
tCSR
VIL -
DQ0 ~ DQ3(7)
VOH -
tCEZ
OPEN
VOL -
W
tRPS
tRPC
tCP
CAS
tRASS
VIH -
VIH VIL -
tWRP
tWRH
TEST MODE IN CYCLE
NOTE : OE , A = Don′t care
tRC
tRP
RAS
tRP
tRAS
VIH VIL -
tRPC
tRPC
tCP
CAS
tCSR
VIH -
tWTS
W
tCHR
VIL -
tWTH
VIH VIL -
DQ0 ~ DQ3(7)
VOH VOL -
tOFF
OPEN
Don′t care
Undefined
KM48V8004C,KM48V8104C
CMOS DRAM
PACKAGE DIMENSION
32 SOJ 400mil
Units : Inches (millimeters)
0.360 (9.15)
0.380 (9.65)
0.435 (11.06)
0.445 (11.30)
0.400 (10.16)
#32
0.006 (0.15)
0.012 (0.30)
#1
0.148 (3.76)
MAX
0.027 (0.69)
MIN
0.841 (21.36)
MAX
0.820 (20.84)
0.830 (21.08)
0.0375 (0.95)
0.050 (1.27)
0.026 (0.66)
0.032 (0.81)
0.015 (0.38)
0.021 (0.53)
32 TSOP(II) 400mil
0.455 (11.56)
0.471 (11.96)
0.400 (10.16)
Units : Inches (millimeters)
0.004 (0.10)
0.010 (0.25)
0.841 (21.35)
MAX
0.821 (20.85)
0.829 (21.05)
0.037 (0.95)
0.050 (1.27)
0.047 (1.20)
MAX
0.010 (0.25)
TYP
0.002 (0.05)
MIN
0.012 (0.30)
0.020 (0.50)
0.018 (0.45)
0.030 (0.75)
0~8
O