KS0741 128 SEG / 129 COM DRIVER & CONTROLLER FOR 4 GRAY SCALE STN LCD February 8. 2000. Ver. 1.2 Prepared by: Hyung-Suk, Kim [email protected] Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team. 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741 KS0741 Specification Revision History Version Date 0.0 Preliminary specification (short form) June 8, 1999 0.1 Preliminary specification (full set) July 14, 1999 0.2 Added temporary pin number (page 5,6) July 15, 1999 0.3 0.4 0.5 0.6 0.7 1.0 1.1 1.2 2 Content Removed HPMB, CS2 pins CS1B pin → CSB pin July 30, 1999 VOL Max.: 0.3VDD → 0.2VDD , VOH Min.: 0.7VDD → 0.8VDD (page 59) Removed CLS, OSCCK, OSC2 pins (page 7,8) Read internal status: MF, DS ID is added, ADC is removed (Page 35, 39) Aug. 12, 1999 RESET flag: 0: display ON, 1: display OFF → 0: display OFF, 1: display ON (Page 39) Changed input pin order, add RESETB pin (page 5) Added VR, VEXT pin connection (page 8) VR: When using internal resistors (INTRS = "H"), open this pin VEXT: When using internal voltage regulator, connect to VDD, VSS or open this pin Added test pin connection (page 9) Aug. 30, 1999 TEST1,TEST2: connect to “VDD” TEST3,TEST4,TEST5: connect to “VSS” Changed OSC resistance connection (page8, 23) Between OSC1 and OSC2 → between OSC1 and VDD Removed TEST2, TEST3, TEST4, TEST5, TEST6, TEST7 pins Added COMS, COMS1 for ICON display. Sep. 30, 1999 Added ICON control register ON/OFF instruction. Remove COMS, COMS1 for ICON display. Oct. 4, 1999 Remove ICON control register ON/OFF instruction. Added COMS, COMS1 for ICON display. Added ICON control register ON/OFF instruction. Modified bit settings for partial display command. Jan. 18, 2000 Relaxed VIH and VIL specifications. Modified interface timing specs. Added 6800-mode interface description for data latch with (page 14) C2 CAP value : 0.1 to 0.47uF → 0.47 to 2.0uF (page 34) Added Icon Mode Disabled to the Reset default list. (page 36) Added description of the column address operation. (page 40) Jan. 24, 2000 Added that Display On/Off command has priority over Entire Display On/Off and Reverse Display On/Off. (page 44) Added N-line inversion command description (page 47) The lower limit of VOUT, V0 - V4 : +0.3V → -0.3V (page 60) The upper limit of V1 - V4 : V0 → V0 + 0.3V (page 60) Feb. 8, 2000 KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD CONTENTS INTRODUCTION ................................................................................................................................................. 1 FEATURES ......................................................................................................................................................... 1 BLOCK DIAGRAM .............................................................................................................................................. 3 PAD CONFIGURATION ...................................................................................................................................... 4 PAD Center Coordinates ................................................................................................................................... 6 PIN DESCRIPTION ............................................................................................................................................. 6 POWER SUPPLY..........................................................................................................................................9 LCD DRIVER SUPPLY..................................................................................................................................9 SYSTEM CONTROL ...................................................................................................................................10 MICROPROCESSOR INTERFACE .............................................................................................................11 LCD DRIVER OUTPUTS .............................................................................................................................13 FUNCTIONAL DESCRIPTION........................................................................................................................... 14 MICROPROCESSOR INTERFACE .............................................................................................................14 DISPLAY DATA RAM (DDRAM) ..................................................................................................................18 LCD DISPLAY CIRCUITS............................................................................................................................21 LCD DRIVER CIRCUIT ...............................................................................................................................26 POWER SUPPLY CIRCUITS ......................................................................................................................29 REFERECE CIRCUIT EXAMPLES..............................................................................................................34 RESET CIRCUIT .........................................................................................................................................36 INSTRUCTION DESCRIPTION.......................................................................................................................... 37 SPECIFICATIONS............................................................................................................................................. 60 ABSOLUTE MAXIMUM RATINGS...............................................................................................................60 DC CHARACTERISTICS.............................................................................................................................61 AC CHARACTERISTICS .............................................................................................................................64 REFERENCE APPLICATIONS.......................................................................................................................... 68 MICROPROCESSOR INTERFACE .............................................................................................................68 CONNECTIONS BETWEEN KS0741 AND LCD PANEL..............................................................................70 3 KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD INTRODUCTION The KS0741 is a driver & controller LSI for 4-level gray scale graphic dot-matrix liquid crystal display systems. It contains 128 segment and 129 common driver circuits. This chip is connected directly to a microprocessor, accepts Serial Peripheral Interface(SPI) or 8-bit parallel display data and stores in an on-chip display data RAM of 128 x 129 x 2 bits. It performs display data RAM read/write operation with no external operating clock to minimize power consumption. In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components. FEATURES 4-level (White, Light Gray, Dark Gray, Black) Gray Scale Display with PWM and FRC Methods DDRAM data [2n: 2n+1] 00 01 Gray scale White Light gray (Accessible column address, n = 0, 1, 2, ……, 125, 126, 127) 10 11 Dark gray Dark Driver Output Circuits − 128 segment outputs / 129 common outputs Applicable Duty Ratios − − Duty ratio Applicable LCD bias Maximum display area 1/16 ~ 1/128 (ICON disabled) 1/17 ~ 1/129 (ICON enabled) 1/5 to 1/12 129 × 128 Various partial display Partial window moving & data scrolling On-chip Display Data RAM − − − Capacity: 129 × 128 × 2 = 33,024bits Bit data "1": a dot of display is illuminated. Bit data "0": a dot of display is not illuminated. Microprocessor Interface − − 8-bit parallel bi-directional interface with 6800-series or 8080-series SPI (serial peripheral interface) available (only write operation) On-chip Low Power Analog Circuit − − − − − On-chip oscillator circuit Voltage converter (x3, x4, ×5 or x6) Voltage regulator (temperature coefficient: -0.05%/°C, or external input) On-chip electronic contrast control function (64 steps) Voltage follower (LCD bias : 1/5 to 1/12) Operating Voltage Range − − Supply voltage (VDD): 1.8 to 3.3V LCD driving voltage (VLCD = V0 - VSS): 4.0 to 15.0 V 1 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD Low Power Consumption − − TBD µΑ Max. (operation) TBD µΑ Max. (sleep mode) Package Type − 2 Slim chip for TCP PRELIMINARY SPEC. VER. 1.2 KS0741 KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD BLOCK DIAGRAM COMS1 V/R CIRCUIT COM127 VR INTRS VEXT REF : FRC/PWM FUNCTION CIRCUIT PAGE LINE I/O DISPLAY DATA RAM ADDRESS ADDRESS BUFFER 129 X 128 X 2 = 33,024 Bits CIRCUIT CIRCUIT V0 COM126 129 COMMON DRIVER CIRCUITS DISPLAY LATCH CIRCUIT V/F CIRCUIT COM1 128 SEGMENT DRIVER CIRCUITS COM0 COMS SEG127 SEG126 : SEG125 SEG2 SEG1 SEG0 VDD V0 V1 V2 V3 V4 VSS COMMON OUTPUT CONTROLLER CIRCUIT OSCILLATOR /DISPLAY TIMING CONTROL OSC1 COLUMN ADDRESS CIRCUIT VOUT C1C1+ C2C2+ C3+ C4+ C5+ VCl V/C CIRCUIT INTERNAL POWER STATUS REGISTER INSTRUCTION REGISTER BUS HOLDER INSTRUCTION DECODER SUPPLY MPU INTERFACE (PARALLEL & SERIAL) DB0 DB1 DB2 DB3 DB4 DB5 DB6(SCLK) DB7(SID) RW_WR E_RD RS CSB PS0 PS1 RESETB TEST1 Figure 1. Block Diagram 3 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741 PAD CONFIGURATION ....................... .. 374 375 181 180 Y ….. ….. (0,0) X KS0741 411 144 1 143 ............ . PAD Figure 2. KS0741 Chip Configuration Table 1. KS0741 Pad Dimensions ITEM PAD NO. Chip Size 1 ~ 143 144 ~ 178 183 ~ 372 377 ~ 411 179 ~ 182 373 ~ 376 1 ~ 143 145 ~ 178 377 ~ 410 183 ~ 372 144 179 ~ 180 375 ~ 376 411 181 ~ 182 373 ~ 374 ALL PAD Pad Pitch Bumped pad size Bumped pad height 4 SIZE X Y 10580 UNIT 2520 70 52 80 42 92 70 34 34 70 70 62 62 70 14 (TYP) §- KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD COG Align Key Coordinate 30µm 30µm 30µm 30µm 30µm 30µm 42µm 108µm 42µm 42µm 108µm 108µm 30µm (-4690, -515) 108µm 42µm (-4607, +704.5) 60µm 30µm 30µm 30µm (+4527, +624.5) ILB Align Key Coordinate (+4770, -580) 5 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741 PAD CENTER COORDINATES Table 2. Pad Center Coordinates [Unit: µm] NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 6 Name DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY X -4970 -4900 -4830 -4760 -4690 -4620 -4550 -4480 -4410 -4340 -4270 -4200 -4130 -4060 -3990 -3920 -3850 -3780 -3710 -3640 -3570 -3500 -3430 -3360 -3290 -3220 -3150 -3080 -3010 -2940 -2870 -2800 -2730 -2660 -2590 -2520 -2450 -2380 -2310 -2240 -2170 -2100 -2030 -1960 -1890 -1820 -1750 -1680 -1610 -1540 Y -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 NO. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Name DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY VDD TEST1 VSS PS0 VDD PS1 VSS CSB RESETB VDD RS RW_WR VSS E_RD VDD DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VDD VDD VDD VDD VDD VDD VCI VCI VSS VSS VSS VSS VSS VSS VSS VOUT VOUT C5+ C5+ X -1470 -1400 -1330 -1260 -1190 -1120 -1050 -980 -910 -840 -770 -700 -630 -560 -490 -420 -350 -280 -210 -140 -70 0 70 140 210 280 350 420 490 560 630 700 770 840 910 980 1050 1120 1190 1260 1330 1400 1470 1540 1610 1680 1750 1820 1890 1960 Y -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 NO. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Name C3+ C3+ C1C1C1+ C1+ C2+ C2+ C2C2C4+ C4+ VDD VDD REF VSS VEXT VDD INTRS VSS VSS V4 V4 V3 V3 V2 V2 V1 V1 V0 V0 VR VR VSS VSS VDD OSC1 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY COM63 COM62 COM61 COM60 COM59 COM58 X 2030 2100 2170 2240 2310 2380 2450 2520 2590 2660 2730 2800 2870 2940 3010 3080 3150 3220 3290 3360 3430 3500 3570 3640 3710 3780 3850 3920 3990 4060 4130 4200 4270 4340 4410 4480 4550 4620 4690 4760 4830 4900 4970 5166 5166 5166 5166 5166 5166 5166 Y -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -1145 -964 -898 -846 -794 -742 -690 -638 NO. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Name COM57 COM56 COM55 COM54 COM53 COM52 COM51 COM50 COM49 COM48 COM47 COM46 COM45 COM44 COM43 COM42 COM41 COM40 COM39 COM38 COM37 COM36 COM35 COM34 COM33 COM32 COM31 COM30 DUMMY DUMMY DUMMY DUMMY COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 X 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5166 5060 4980 4914 4862 4810 4758 4706 4654 4602 4550 4498 4446 4394 4342 4290 4238 4186 4134 4082 4030 Y -586 -534 -482 -430 -378 -326 -274 -222 -170 -118 -66 -14 38 90 142 194 246 298 350 402 454 506 558 610 662 714 766 818 884 964 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD Table 2. PAD Center Coordinates (Continued) [unit: µm ] NO. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 Name COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COMS SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 X 3978 3926 3874 3822 3770 3718 3666 3614 3562 3510 3458 3406 3354 3302 3250 3198 3146 3094 3042 2990 2938 2886 2834 2782 2730 2678 2626 2574 2522 2470 2418 2366 2314 2262 2210 2158 2106 2054 2002 1950 1898 1846 1794 1742 1690 1638 1586 1534 1482 1430 Y 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 NO. 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 Name SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 X 1378 1326 1274 1222 1170 1118 1066 1014 962 910 858 806 754 702 650 598 546 494 442 390 338 286 234 182 130 78 26 -26 -78 -130 -182 -234 -286 -338 -390 -442 -494 -546 -598 -650 -702 -754 -806 -858 -910 -962 -1014 -1066 -1118 -1170 Y 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 NO. 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 Name SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 X -1222 -1274 -1326 -1378 -1430 -1482 -1534 -1586 -1638 -1690 -1742 -1794 -1846 -1898 -1950 -2002 -2054 -2106 -2158 -2210 -2262 -2314 -2366 -2418 -2470 -2522 -2574 -2626 -2678 -2730 -2782 -2834 -2886 -2938 -2990 -3042 -3094 -3146 -3198 -3250 -3302 -3354 -3406 -3458 -3510 -3562 -3614 -3666 -3718 -3770 Y 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 NO. 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 Name COM73 COM74 COM75 COM76 COM77 COM78 COM79 COM80 COM81 COM82 COM83 COM84 COM85 COM86 COM87 COM88 COM89 COM90 COM91 COM92 COM93 COM94 DUMMY DUMMY DUMMY DUMMY COM95 COM96 COM97 COM98 COM99 COM100 COM101 COM102 COM103 COM104 COM105 COM106 COM107 COM108 COM109 COM110 COM111 COM112 COM113 COM114 COM115 COM116 COM117 COM118 X -3822 -3874 -3926 -3978 -4030 -4082 -4134 -4186 -4238 -4290 -4342 -4394 -4446 -4498 -4550 -4602 -4654 -4706 -4758 -4810 -4862 -4914 -4980 -5060 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 Y 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 1136 964 884 818 766 714 662 610 558 506 454 402 350 298 246 194 142 90 38 -14 -66 -118 -170 -222 -274 -326 -378 7 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741 Table 2. PAD Center Coordinates (Continued) [unit: µm ] NO. 401 402 403 404 405 406 407 408 409 410 411 8 Name COM119 COM120 COM121 COM122 COM123 COM124 COM125 COM126 COM127 COMS1 DUMMY X -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 -5166 Y -430 -482 -534 -586 -638 -690 -742 -794 -846 -898 -964 NO. Name X Y NO. Name X Y NO. Name X Y KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PIN DESCRIPTION POWER SUPPLY Table 3. Power Supply Pin Description Name I/O VDD Supply Power supply VSS Supply Ground V0 V1 V2 I/O V3 V4 Description LCD driver supply voltages The voltage determined by LCD pixel is impedance-converted by an operational amplifier for application. Voltages should have the following relationship; V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS When the internal power circuit is active, these voltages are generated as following table according to the state of LCD bias. LCD bias V1 V2 V3 V4 1/N bias (N-1) / N x V0 (N-2) / N x V0 (2/N) x V0 (1/N) x V0 NOTE: N = 5 to 12 LCD DRIVER SUPPLY Table 4. LCD Driver Supply Pin Description Name I/O Description C1- O Capacitor 1 negative connection pin for voltage converter C1+ O Capacitor 1 positive connection pin for voltage converter C2- O Capacitor 2 negative connection pin for voltage converter C2+ O Capacitor 2 positive connection pin for voltage converter C3+ O Capacitor 3 positive connection pin for voltage converter C4+ O Capacitor 4 positive connection pin for voltage converter C5+ O Capacitor 5 positive connection pin for voltage converter VOUT I/O Voltage converter input / output pin VCl I VR I REF I VEXT I OSC1 I Voltage converter input voltage pin V0 voltage adjustment pin It is valid only when on-chip resistors are not used (INTRS = "L") When using internal resistors (INTRS = "H"), open this pin Selects the external VREF voltage via the VEXT pin − REF = “H”: using the internal VREF − REF = “L”: using the external VREF Externally input reference voltage (VREF) for the internal voltage regulator It is valid only when REF is "L" When using internal voltage regulator, connect to VDD, VSS or open this pin When using internal clock oscillator, connect a resistor between OSC1 and VDD. 9 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 SYSTEM CONTROL Table 5. System Control Pin Description Name 10 I/O Description INTRS I Internal resistor select pin This pin selects the resistors for adjusting V0 voltage level − INTRS = "H": use the internal resistors. − INTRS = "L": use the external resistors VR pin and external resistive divider control V0 voltage TEST1 O Test pins Don’ t use this pin. − TEST1: Open this pin. KS0741 KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD MICROPROCESSOR INTERFACE Table 6. Microprocessor Interface Pin Description Name I/O RESETB I Description Reset input pin When RESETB is “L”, initialization is executed. Parallel / Serial data input select input PS0 I PS0 Interface mode Data / instruction Data Read / Write Serial clock H Parallel RS DB0 to DB7 E_RD RW_WR - L Serial RS or None SID (DB7) Write only SCLK (DB6) *NOTE: In serial mode, it is impossible to read data from the on-chip RAM. And DB0 to DB5 are high impedance and E_RD and RW_WR must be fixed to either “H” or “L”. PS1 I Microprocessor interface select input pin − PS0 = “H” , PS1 = "H": 6800-series parallel MPU interface − PS0 = “H” , PS1 = "L": 8080-series parallel MPU interface − PS0 = “L” , PS1 = "H": 4 pin-SPI MPU interface − PS0 = “L” , PS1 = "L": 3 pin-SPI MPU interface CSB I RS I RW_WR Chip select input pins Data/instruction I/O is enabled only when CSB is "L". When chip select is non-active, DB0 to DB7 may be high impedance. Register select input pin − RS = "H": DB0 to DB7 are display data − RS = "L": DB0 to DB7 are control data Read / Write execution control pin C68 MPU type RW_WR H 6800-series RW Read / Write control input pin − RW = “H” : read − RW = “L” : write L 8080-series /WR Write enable clock input pin The data on DB0 to DB7 are latched at the rising edge of the /WR signal. I Description 11 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741 Table 7. Microprocessor Interface Pin Description (Continued) Name I/O Description Read / Write execution control pin PS1 E_RD DB0 to DB7 12 I I/O MPU Type E_RD H 6800-series E L 8080-series /RD Description Read / Write control input pin − RW = “H”: When E is “H”, DB0 to DB7 are in an output status. − RW = “L”: The data on DB0 to DB7 are latched at the falling edge of the E signal. Read enable clock input pin When /RD is “L”, DB0 to DB7 are in an output status. 8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data bus. When the serial interface selected (PS0 = "L"); − DB0 to DB5: high impedance − DB6: serial input clock (SCLK) − DB7: serial input data (SID) When chip select is not active, DB0 to DB7 may be high impedance. KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD LCD DRIVER OUTPUTS Table 8. LCD Driver Output Pin Description Name I/O Description LCD segment driver outputs The display data and the M signal control the output voltage of segment driver. SEG0 to SEG127 O Display data M (Internal) H Segment driver output voltage Normal display Reverse display H V0 V2 H L VSS V3 L H V2 V0 L L V3 VSS VSS VSS Power save mode LCD common driver outputs The internal scanning data and M signal control the output voltage of common driver. COM0 to COM127 O Scan data M (Internal) Common driver output voltage H H VSS H L V0 L H V1 L L V4 Power save mode COMS (COMS1) O VSS Common output for the icons The output signals of two pins are same. When not used, these pins should be left open. NOTE: DUMMY – These pins should be opened (floated). 13 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741 FUNCTIONAL DESCRIPTION MICROPROCESSOR INTERFACE Chip Select Input There is CSB pin for chip selection. The KS0741 can interface with an MPU when CSB is "L". When these pins are set to any other combination, RS, E_RD, and RW_WR inputs are disabled and DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset. Parallel / Serial Interface KS0741 has four types of interface with an MPU, which are two serial and two parallel interfaces. This parallel or serial interface is determined by PS pin as shown in table 9. Table 9. Parallel / Serial Interface Mode Type Parallel Serial PS1 H L H L CSB PS0 CSB H CSB L Interface mode 6800-series MPU mode 8080-series MPU mode 4-pin SPI mode 3-pin SPI mode Parallel Interface (PS0 = "H") The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS1 as shown in table 10. The type of data transfer is determined by signals at RS, E_RD and RW_WR as shown in table 11. Table 10. Microprocessor Selection for Parallel Interface PS1 CSB RS E_RD RW_WR DB0 to DB7 MPU bus H CSB RS E RW DB0 to DB7 6800-series L CSB RS /RD /WR DB0 to DB7 8080-series Table 11. Parallel Data Transfer Common 6800-series 8080-series RS E_RD (E) RW_WR (RW) E_RD (/RD) RW_WR (/WR) Description H H H L H Display data read out H H L H L Display data write L H H L H Register status read L H L H L Writes to internal register (instruction) NOTE: When E_RD pin is always pulled high for 6800-series interface, it can be used CSB for enable signal. In this case, interface data is latched at the rising edge of CSB and the type of data transfer is determined by signals at RS, RW_WR as in case of 6800-series mode. 14 KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD Serial Interface (PS0 = "L") When the KS0741 is active(CSB=”L”), serial data (DB7) and serial clock (DB6) inputs are enabled. And not active, the internal 8-bit shift register and the 3-bit counter are reset. The display data/command indication may be controlled either via software or the Register Select(RS) Pin, based on the setting of PS1. When the RS pin is used (PS1 = “H”), data is display data when RS is high, and command data when RS is low. When RS is not used (PS1 = “L”), the LCD Driver will receive command from MCU by default. If messages on the data pin are data rather than command, MCU should send Data Direction command(11101000) to control the data direction and then one more command to define the number of data bytes will be write. After these two continuous commands are send, the following messages will be data rather than command. Serial data can be read on the rising edge of serial clock going into DB6 and processed as 8-bit parallel data on the eighth serial clock. And the DDRAM column address pointer will be increased by one automatically. The next bytes after the display data string is handled as command data. Serial Mode PS0 PS1 CSB RS 4-Pin SPI mode L H CSB Used 3-Pin SPI mode L L CSB Not used 4-pin SPI mode (PS0 = "L" , PS1 = "H") CSB SID DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 SCLK RS Figure 3. 4-pin SPI Timing (RS is used) 15 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741 3-pin SPI mode (PS0 = "L" , PS1 = "L") To write data to the DDRAM, send Data Direction Command in 3-pin SPI mode. Data is latched at the rising edge of SCLK. And the DDRAM column address pointer will be increased by one automatically. CSB 0 23 0 1 7 8 15 0 829 830 831 SCLK 3 Byte (1) 2 Byte (2) (1) SID Page MSB 104 Byte ( LSB Data In DDC No. of DATA (1) Set Page and Column Address. Set Page Address : 1 0 1 1 P3 P2 P1 P0 Set Column Address MSB : 0 0 0 1 0 Y6 Y5 Y4 Set Column Address LSB : 0 0 0 0 Y3 Y2 Y1 Y0 (2) Set DDC(Data Direction Command) and No. of Data Bytes. Set Data Direction Command( For SPI mode Only): 1 1 1 0 1 0 0 0 Set No. of Data Bytes : D7 D6 D5 D4 D3 D2 D1 D0 (3) This figure is example for 104 Data bytes to be transfered . Figure 4. 3-pin SPI Timing (RS is not used) This command is used in 3-pin SPI mode only. It will be two continuous commands, the first byte controls the data direction and informs the LCD driver the second byte will be number of data bytes will be write. After these two commands sending out, the following messages will be data. If data is stopped in transmitting, it is not valid data. New data will be transferred serially with most significant bit first. NOTE: In spite of transmission of data, if CSB will be disable, state terminates abnormally. Next state is initialized. Busy Flag The Busy Flag indicates whether the KS0741 is operating or not. When DB7 is "H" in read status operation, this device is in busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the MPU performance. 16 KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD Data Transfer The KS0741 uses bus holder and internal data bus for data transfer with the MPU. When writing data from the MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in figure 5. And when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure 6. This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. Therefore, the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data. MPU signals RS /W R DB0 to DB7 N D(N) D(N+1) D(N+2) D(N+3) N D(N) D(N+1) D(N+2) D(N+3) Internal signals /W R BUS HOLDER N COLUMN ADDRESS N+1 N+2 N+3 Figure 5. Write Timing MPU signals RS /W R /RD DB0 to DB7 Dummy N D(N) D(N+1) Internal signals /W R /RD BUS HOLDER COLUMN ADDRESS N D(N) N N+1 D(N+1) D(N+2) N+2 N+3 Figure 6. Read Timing 17 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741 DISPLAY DATA RAM (DDRAM) The Display Data RAM stores pixel data for the LCD. It is 129-row (17 page by 8 bits) by 128-column addressable array. Each pixel can be selected when the page and column addresses are specified. The 129 rows are divided into 16 pages of 8 lines and the 17th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page directly through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD common lines. The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD controller operates independently, data can be written into RAM at the same time as data is being displayed without causing the LCD flicker. Page Address Circuit This circuit is for providing a Page Address to Display Data RAM shown in figure 8. It incorporates 4-bit Page Address register changed by only the “Set Page” instruction. Page Address 16 is a special RAM area for the icons and display data DB0 is only valid. Line Address Circuit This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by setting Line Address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip RAM as shown in figure 8. It incorporates 7-bit Line Address register changed by only the initial display line instruction and 7-bit counter circuit. At the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by CL signal and generates the line address for transferring the 128-bit RAM data to the display data latch circuit. When icon is enabled by setting icon control register, display data of icons are not scrolled because the MPU can not access Line Address of icons. 18 KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD Column Address Circuit Column Address Circuit has a 8-bit preset counter that provides Column Address to the Display Data RAM as shown in figure 8. When set Column Address MSB / LSB instruction is issued, 7-bit [Y7:Y1] are set and lowest bit, Y0 is set to “0”. Since this address is increased by 1 each a read or write data instruction, microprocessor can access the display data continuously. However, the counter is not increased and locked if a non-existing address above 7EH. It is unlocked if a column address is set again by set Column Address MSB / LSB instruction. And the column address counter is independent of page address register. ADC select instruction makes it possible to invert the relationship between the Column Address and the segment outputs. It is necessary to rewrite the display data on built-in RAM after issuing ADC select instruction. Refer to the following figure 7. SEG output SEG 0 SEG 1 SEG 2 SEG 3 ... ... SEG 124 SEG 125 SEG 126 SEG 127 Column address [Y7:Y1] 00H 01H 02H 03H ... ... 7CH 7DH 7EH 7FH Internal column address [Y7:Y0] 00 HEX 01 HEX 02 HEX 03 HEX 04 HEX 05 HEX 06 HEX 07 HEX ... ... F8 HEX F9 HEX FA HEX FB HEX FC HEX FD HEX FE HEX FF HEX Display data (ADC = 0) 1 1 1 0 0 0 0 1 ... ... 1 0 1 1 0 0 0 1 0 1 0 0 1 0 1 1 LCD panel display Display data (ADC = 1) LCD panel display ... ... 0 1 0 0 1 1 1 0 ... ... ... ... Figure 7. The Relationship between the Column Address and The Segment Outputs Segment Control Circuit This circuit controls the display data by the display ON / OFF, reverse display ON / OFF and entire display ON / OFF instructions without changing the data in the display data RAM. 19 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD 0 DB2 0 DB1 0 DB0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 KS0741 Line Address Data DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH Page 0 Page 1 Page 2 Page 3 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 60H 61H 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH 80H Page 12 Page 13 Page 14 Page 15 Page 16 (*) COM Output End = 07H Start = 08H 1/121 Duty 0 DB3 1/129 Duty Page Address DB4 PRELIMINARY SPEC. VER. 1.2 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM96 COM97 COM98 COM99 COM100 COM101 COM102 COM103 COM104 COM105 COM106 COM107 COM108 COM109 COM110 COM111 COM112 COM113 COM114 COM115 COM116 COM117 COM118 COM119 COM120 COM121 COM122 COM123 COM124 COM125 COM126 COM127 COMS (*) When ICON control register is set to "1", page address is set to "16". and user can write data for displaying icons. Column Address [Y7:Y1] 00 01 02 03 04 05 7F 7E 7D 7C 7B 7A --------------- 20 SEG127 Figure 8. Display Data RAM Map SEG126 SEG125 SEG124 SEG123 -------- 7A 7B 7C 7D 7E 7F 05 04 03 02 01 00 SEG122 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 LCD Segment Output ADC=0 ADC=1 Initial start line address = 08H KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD LCD DISPLAY CIRCUITS FRC (Frame Rate Control) and PWM (Pulse Width Modulation) Function Circuit The KS0741 incorporates an FRC function and a PWM function circuit to display a 4-level gray scale. The FRC function and PWM utilize liquid crystal characteristics whose transmittance is changed by an effective value of applied voltage. The KS0741 provides four 4-bit palette-registers to assign the desired gray level. These registers are set by the instructions and the RESETB. − Gray Scale Table of 4 FRC (Frame Rate Control) Gray scale level White Light gray Dark gray Black − MSB (DB7 to DB4) LSB (DB3 to DB0) 2nd FR (FR2) 1st FR (FR1) 4th FR (FR4) 3rd FR (FR3) 2nd FR (FR2) 1st FR (FR1) 4th FR (FR4) 3rd FR (FR3) 2nd FR (FR2) 1st FR (FR1) 4th FR (FR4) 3rd FR (FR3) 2nd FR (FR2) 1st FR (FR1) 4th FR (FR4) 3rd FR (FR3) Gray Scale Table of 3 FRC (Frame Rate Control) Gray scale level White Light gray Dark gray Black MSB (DB7 to DB4) LSB (DB3 to DB0) 2nd FR (FR2) 1st FR (FR1) ×××× 3rd FR (FR3) 2nd FR (FR2) 1st FR (FR1) ×××× 3rd FR (FR3) 2nd FR (FR2) 1st FR (FR1) ×××× 3rd FR (FR3) 2nd FR (FR2) 1st FR (FR1) ×××× 3rd FR (FR3) 21 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD − − 22 PRELIMINARY SPEC. VER. 1.2 KS0741 Gray Scale Table of 15 PWM (Pulse Width Modulation) Dec Hex 4-bits PWM (on width) Note 0 00 0000 0 (0/15) Brighter 1 01 0001 1/15 2 02 0010 2/15 3 03 0011 3/15 4 04 0100 4/15 5 05 0101 5/15 6 06 0110 6/15 7 07 0111 7/15 8 08 1000 8/15 9 09 1001 9/15 10 0A 1010 10/15 11 0B 1011 11/15 12 0C 1100 12/15 13 0D 1101 13/15 14 0E 1110 14/15 15 0F 1111 1 (15/15) Darker Gray Scale Table of 12 PWM (Pulse Width Modulation) Dec Hex 4-bits PWM (on width) Note 0 00 0000 0 (0/12) Brighter 1 01 0001 1/12 2 02 0010 2/12 3 03 0011 3/12 4 04 0100 4/12 5 05 0101 5/12 6 06 0110 6/12 7 07 0111 7/12 8 08 1000 8/12 9 09 1001 9/12 10 0A 1010 10/12 11 0B 1011 11/12 12 0C 1100 1 (12/12) 13 0D 1101 0/12 14 0E 1110 0/12 15 0F 1111 0/12 Darker This area is selected to OFF level (0/12 level) KS0741 − PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD Gray Scale Table of 9 PWM (Pulse Width Modulation) Dec Hex 4-bits PWM (on width) Note 0 00 0000 0 (0/9) Brighter 1 01 0001 1/9 2 02 0010 2/9 3 03 0011 3/9 4 04 0100 4/9 5 05 0101 5/9 6 06 0110 6/9 7 07 0111 7/9 8 08 1000 8/9 9 09 1001 1 (9/9) 10 0A 1010 0/9 11 0B 1011 0/9 12 0C 1100 0/9 13 0D 1101 0/9 14 0E 1110 0/9 15 0F 1111 0/9 Darker This area is selected to OFF level (0/9 level) 23 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741 Oscillator This is on-chip Oscillator with external resistor. Its frequency is controlled by external resistor between OSC1 and VDD. This oscillator signal is used in the voltage converter and display timing generation circuit. Display Timing Generator Circuit This circuit generates some signals to be used for displaying LCD. The display clock, CL(internal), generated by oscillation clock, generates the clock for the line counter and the signal for the display data latch. The line address of on-chip RAM is generated in synchronization with the display clock and the display data latch circuit latches the 128-bit display data in synchronization with the display clock. The display data, which is read to the LCD driver, is completely independent of the access to the display data RAM from the microprocessor. The display clock generates an LCD AC signal (M) which enables the LCD driver to make a AC drive waveform, and also generates an internal common timing signal and start signal to the common driver. The frame signal or the line signal changes the M by setting internal instruction. Driving waveform and internal timing signal are shown in Figure 9. 127 128 1 2 3 4 5 6 7 8 9 10 11 12 121 122 123 124 125 126 127 128 1 2 3 4 5 6 CL(Internal) FR(Internal) M(Internal) COM0 V0 V1 V2 V3 V4 VSS COM1 V0 V1 V2 V3 V4 VSS SEGn V0 V1 V2 V3 V4 VSS Figure 9. 2-frame AC Driving Waveform (Duty Ratio = 1/128) 24 KS0741 PRELIMINARY SPEC. VER. 1.2 127 128 1 2 3 4 5 6 7 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD 8 9 10 11 12 119 120 121 122 123 124 125 126 127 128 1 2 3 4 CL(Internal) FR(Internal) M(Internal) COM0 V0 V1 V2 V3 V4 VSS COM1 V0 V1 V2 V3 V4 VSS SEGn V0 V1 V2 V3 V4 VSS Figure 10. N-Line Inversion Driving Waveform (N = 5, Duty Ratio = 1/128) 25 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741 LCD DRIVER CIRCUIT This driver circuit is configured by 129-channel common drivers and 128-channel segment drivers. This LCD panel driver voltage depends on the combination of display data and M signal. VDD COM0 M COM1 VSS COM2 V0 V1 V2 COM0 COM3 COM4 V3 V4 VSS V0 V1 V2 COM5 COM1 COM6 COM7 V3 V4 VSS V0 V1 V2 COM8 COM2 COM9 V0 V1 V2 COM10 SEG0 COM11 COM12 V3 V4 VSS V0 V1 V2 COM13 SEG1 COM14 COM15 S E G 0 S E G 1 S E G 2 S E G 3 S E G 4 V3 V4 VSS V0 V1 V2 SEG2 Figure 11. Segment and Common Timing 26 V3 V4 VSS V3 V4 VSS KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD Partial Display on LCD The KS0741 realizes the Partial Display function on LCD with low-duty driving for saving power consumption and showing the various display duty. To show the various display duty on LCD, LCD driving duty and bias are programmable via the instruction. And, built-in power supply circuits are controlled by the instruction for adjusting the LCD driving voltages -- COM0 -- COM1 -- COM2 -- COM3 -- COM4 -- COM5 -- COM6 -- COM7 -- COM8 -- COM9 -- COM10 -- COM11 -- COM12 -- COM13 -- COM14 -- COM15 -- COM16 -- COM17 -- COM18 -- COM19 -- COM20 -- COM21 -- COM22 -- COM23 Figure 12. Reference Example for Partial Display -- COM0 -- COM1 -- COM2 -- COM3 -- COM4 -- COM5 -- COM6 -- COM7 -- COM8 -- COM9 -- COM10 -- COM11 -- COM12 -- COM13 -- COM14 -- COM15 -- COM16 -- COM17 -- COM18 -- COM19 -- COM20 -- COM21 -- COM22 -- COM23 Figure 13. Partial Display (Partial Display Duty = 16, Initial COM0 = 0) 27 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 -- COM0 -- COM1 -- COM2 -- COM3 -- COM4 -- COM5 -- COM6 -- COM7 -- COM8 -- COM9 -- COM10 -- COM11 -- COM12 -- COM13 -- COM14 -- COM15 -- COM16 -- COM17 -- COM18 -- COM19 -- COM20 -- COM21 -- COM22 -- COM23 Figure 14. Moving Display (Partial Display Duty = 16, Initial COM0 = 8) 28 KS0741 KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD POWER SUPPLY CIRCUITS The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. They are controlled by power control instruction. For details, refers to "Instruction Description". Table 12 shows the referenced combinations in using Power Supply circuits. Table 12. Recommended Power Supply Combinations User setup Power control (VC VR VF) V/C circuits V/R circuits V/F circuits VOUT V0 V1 to V4 Only the internal power supply circuits are used 111 ON ON ON Open Open Open Only the voltage regulator circuits and voltage follower circuits are used 011 OFF ON ON External input Open Open Only the voltage follower circuits are used 001 OFF OFF ON Open External input Open Only the external power supply circuits are used 000 OFF OFF OFF Open External input External input 29 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741 Voltage Converter Circuits These circuits boost up the electric potential between VCI and Vss to 3, 4, 5 or 6 times toward positive side and boosted voltage is outputted from VOUT pin. It is possible to select the lower boosting level in any boosting circuit by “Set DC-DC Step-up” instruction. When the higher level is selected by instruction, VOUT voltage is not valid. [C1 = 1.0 to 4.7 µF] Vss VOUT + Vss C1 VOUT C5+ C5+ C3+ C3+ C1C1+ VOUT = 3 x VCI + C1 C1+ C2+ C2 - + - C1 VCI Vss Figure 15. Three Times Boosting Circuit VOUT + C1 VOUT = 4 x VCI + + C1 C1 C2+ C2 - C4+ Vss C1- + + - VCI C1 Vss C4+ Figure 16. Four Times Boosting Circuit Vss C1 VOUT + C1 VOUT = 6 x VCI VOUT = 5 x VCI C5+ C5+ C1 C3+ C1C1+ + + C3+ C1 C1C1 C1+ C2+ C2 - + - C4+ + C1 VCI C1 Vss 30 + C1 C1 C2+ C2 - Figure 17. Five Times Boosting Circuit + - + - C4+ + + - C1 VCI C1 Vss Figure 18. Six Times Boosting Circuit KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD Voltage Regulator Circuits The function of the internal Voltage Regulator circuits is to determine liquid crystal operating voltage, V0, by adjusting resistors, Ra and Rb, within the range of |V0| < |VOUT|. Because VOUT is the operating voltage of operational-amplifier circuits shown in figure 19, it is necessary to be applied internally or externally. For the Eq. 1, we determine V0 by Ra, Rb and VEV. The Ra and Rb are connected internally or externally by INTRS pin. And VEV called the voltage of electronic volume is determined by Eq. 2, where the parameter α is the value selected by instruction, "Set Reference Voltage Register", within the range 0 to 63. VREF voltage at Ta= 25°C is shown in Table 13. Rb V0 = (1 + ) x VEV [V] ------ (Eq. 1) Ra (63 - α) VEV = (1 - ) x VREF [V] ------ (Eq. 2) 210 Table 13 . VREF Voltage at Ta = 25°C REF Temp. coefficient VREF [ V ] 1 -0.05% / °C 2.1 0 External input VEXT VOUT + V EV V0 - Rb VR Ra VSS GND Figure 19. Internal Voltage Regulator Circuit 31 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741 In Case of Using Internal Resistors, Ra and Rb (INTRS = "H”) When INTRS pin is "H", resistor Ra is connected internally between VR pin and VSS, and Rb is connected between V0 and VR. We determine V0 by two instructions, "Regulator Resistor Select" and "Set Reference Voltage". Table 14. Internal Rb / Ra Ratio depending on 3-bit Data (R2 R1 R0) 3-bit data settings (R2 R1 R0) 1 + (Rb / Ra) 000 001 010 011 100 101 110 111 2.3 3.0 3.7 4.4 5.1 5.8 6.5 7.2 Figure 20 Shows V0 voltage measured by adjusting internal regulator register ratio (Rb / Ra) and 6-bit electronic volume registers for each temperature coefficient at Ta = 25 °C. 16.00 (1, 1, 1) 14.00 (1, 1, 0) (1, 0, 1) 12.00 V0 voltage [V] (1, 0 ,0) 10.00 (0, 1, 1) 8.00 (0, 1, 0) (0, 0, 1) 6.00 (0, 0, 0) 4.00 2.00 0.00 0 8 16 24 32 40 48 56 Electronic volume register (0 to 63) Figure 20. Electronic Volume Level (Temp. Coefficient = -0.05% / °C) 32 63 63 KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD In Case of Using External Resistors, Ra and Rb (INTRS = "L") When INTRS pin is "L", it is necessary to connect external regulator resistor Ra between VR and VSS, and Rb between V0 and VR. Example: For the following requirements 1. LCD driver voltage, V0 = 10V 2. 6-bit reference voltage register = (1, 0, 0, 0, 0, 0) 3. Maximum current flowing Ra, Rb = 1 uA From Eq. 1 Rb 10 = (1 + ) x VEV [V] ------ (Eq. 3) Ra From Eq. 1 (63 - 32) VEV = (1 - ) x 2.1 = 1.79 [V] ------ (Eq. 4) 210 From requirement 3. 10 = 1 [uA] ------ (Eq. 5) Ra + Rb From equations Eq. 3, 4 and 5 Ra = 1.79 [MΩ] Rb = 8.21 [MΩ] Table 15 Shows the Range of V0 depending on the above Requirements. Table 15. The Range of V0 Electronic volume level V0 0 ....... 32 ....... 63 8.21 ....... 10.00 ....... 11.73 Voltage Follower Circuits VLCD voltage (V0) is resistively divided into four voltage levels (V1, V2, V3 and V4), and those output impedance are converted by the Voltage Follower for increasing drive capability. Table 16 shows the relationship between V1 to V4 level and each duty ratio. Table 16. The Relationship Between V1 to V4 Level and Each Duty Ratio LCD bias V1 V2 V3 V4 Remarks 1/N (N-1)/N x V0 (N-2)/N x V0 2/N x V0 1/N x V0 N = 5 to 12 33 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741 REFERENCE CIRCUIT EXAMPLES [C1 = 1.0 to 4.7 [µF], C2 = 0.47 to 2.0 [µF]] When not using internal regulator resistors When using internal regulator resistors V DD INTRS C1 VOUT C5+ C3+ C1 C1+ C2+ C2 C4+ C1 C1 C1 C1 C1 C1 + + + + + C1 C1 C1 Ra C2 C2 C2 C2 C2 V0 V1 V2 V3 V4 V SS VOUT C5+ C3+ C1 C1+ C2+ C2 C4+ C1 C1 VR C2 C2 C2 C2 C2 V SS INTRS + + + + + R b VR V0 V1 V2 V3 V4 V SS Figure 21. When Using all LCD Power Circuits (6-Time V/C: ON, V/R: ON, V/F: ON) [C2 = 0.47 to 2.0 [µF]] When using internal regulator resistors When not using internal regulator resistors V DD External Power Supply C2 C2 C2 C2 C2 V SS - + + + + + INTRS VOUT C5+ C3+ C1C1+ C2+ C2C4+ VR V0 V1 V2 V3 V4 INTRS External Power Supply VOUT C5+ C3+ C1C1+ C2+ C2C4+ VR Ra C2 C2 C2 C2 C2 - + + + + + V SS Rb V0 V1 V2 V3 V4 V SS Figure 22. When Using some LCD Power Circuits (V/C: OFF, V/R: ON, V/F: ON) 34 KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD [C2 = 0.47 to 2.0 [µF]] VDD INTRS External Power Supply C2 C2 C2 C2 C2 - + + + + + VOUT C5+ C3+ C1C1+ C2+ C2C4+ VR V0 V1 V2 V3 V4 VSS Figure 23. When Using some LCD Power Circuits (V/C: OFF, V/R: OFF, V/F: ON) [C2 = 0.47 to 2.0 [µF]] VDD INTRS VOUT C5+ C3+ C1C1+ C2+ C2C4+ VR External Power Supply V0 V1 V2 V3 V4 VSS Figure 24. When Not Using any Internal LCD Power Supply Circuits (V/C: OFF, V/R: OFF, V/F: OFF) 35 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741 RESET CIRCUIT Setting RESETB to “L” or Reset instruction can initialize internal function. When RESETB becomes “L”, following procedure is occurred. Page address: 0 Column address: 0 Read-modify-write: OFF Display ON / OFF: OFF Initial display line: 0 (first) Initial COM0 register: 0 (COM0) Partial display duty ratio: 1/128 Reverse display ON / OFF: OFF (normal) N-line inversion register: 0 (disable) Entire Display ON/OFF: OFF ICON Control register ON/OFF: OFF (ICON disable) Power control register (VC, VR, VF) = (0, 0, 0) DC-DC converter circuit = (0, 0) Regulator resistor select register: (R2, R1, R0) = (0, 0, 0) Contrast Level: 32 LCD bias ratio: 1/12 COM Scan Direction: 0 ADC Select: 0 Oscillator: OFF Power Save Mode: Release Display Data Length register: 0 (for SPI mode) White mode set: OFF White palette register (WG3, WG2, WG1, WG0) = (0, 0, 0, 0) Light gray mode set: OFF Light gray palette register (LG3, LG2, LG1, LG0) = (0, 0, 0, 0) Dark gray mode set: OFF Dark gray palette register (DG3, DG2, DG1, DG0) = (1, 1, 1, 1) Black mode set: OFF Black palette register (BG3, BG2, BG1, BG0) = (1, 1, 1, 1) FRC, PWM mode: 4FRC, 9PWM When RESET instruction is issued, following procedure is occurred. Page address: 0 Column address: 0 Read-modify-write: OFF Initial display line: 0 (First) Regulator resistor select register: (R2, R1, R0) = (0, 0, 0) Contrast Level: 32 Display Data Length register: 0 (for SPI mode) White mode set: OFF White palette register (WG3, WG2, WG1, WG0) = (0, 0, 0, 0) Light gray mode set: OFF Light gray palette register (LG3, LG2, LG1, LG0) = (0, 0, 0, 0) Dark gray mode set: OFF Dark gray palette register (DG3, DG2, DG1, DG0) = (1, 1, 1, 1) Black mode set: OFF Black palette register (BG3, BG2, BG1, BG0) = (1, 1, 1, 1) FRC, PWM mode: 4FRC, 9PWM While RESETB is “L” or reset instruction is executed, no instruction except read status can be accepted. Reset status appears at DB4. After DB4 becomes ”L”, any instruction can be accepted. RESETB must be connected to the reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESETB is essential before used. 36 KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD INSTRUCTION DESCRIPTION Table 17. Instruction Table Instruction RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ×´ : Don’ t care Description Read display data 1 1 Read data Read data from DDRAM Write display data 1 0 Write data Write data into DDRAM Read status 0 1 BUSY ON RES MF2 MF1 MF0 DS1 DS0 ICON control register ON/OFF 0 0 1 0 1 0 0 0 1 ICON Set page address 0 0 1 0 1 1 P3 P2 P1 P0 Set column address MSB 0 0 0 0 0 1 0 Y7 Y6 Y5 Set column address MSB Set column address LSB 0 0 0 0 0 0 Y4 Y3 Y2 Y1 Set column address LSB Set modify-read 0 0 1 1 1 0 0 0 0 0 Set modify-read mode Reset modify-read 0 0 1 1 1 0 1 1 1 0 release modify-read mode Display ON/OFF 0 0 1 0 1 0 1 1 1 D D=0: display OFF D=1: display ON 0 0 0 1 0 0 0 0 ×´ ×´ 0 0 ×´ S6 S5 S4 S3 S2 S1 S0 0 0 0 1 0 0 0 1 ×´ ×´ 0 0 ×´ C6 C5 C4 C3 C2 C1 C0 0 0 0 1 0 0 1 0 ×´ ×´ 0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 0 1 1 ×´ ×´ 0 0 ×´ ×´ ×´ N4 N3 N2 N1 N0 2-byte instruction to set N-line inversion register Release N-line inversion 0 0 1 1 1 0 0 1 0 0 Release N-line Inversion mode Reverse display ON/OFF 0 0 1 0 1 0 0 1 1 REV REV=0: normal display, REV=1: reverse display Entire display ON/OFF 0 0 1 0 1 0 0 1 0 EON EON=0: normal display. EON=1: entire display ON Set initial display line register Set initial COM0 register Set partial display duty ratio Set N-line inversion Read the internal status ICON=0: ICON disable (default) ICON=1: ICON enable & set the page address to 16 Set page address 2-byte instruction to specify the initial display line to realize vertical scrolling 2-byte instruction to specify the initial COM0 to realize window scrolling 2-byte instruction to set partial display duty ratio 37 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741 Table 17. Instruction Table (Continued) Instruction ×´ : Don’ t care Description RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Power control 0 0 0 0 1 0 1 VC VR VF Select DC-DC step-up 0 0 0 1 1 0 0 1 DC1 DC0 Select the step-up of the internal voltage converter Select regulator resistor 0 0 0 0 1 0 0 R2 R1 R0 Select internal resistance ratio of the regulator resistor Set electronic volume register 0 0 1 0 0 0 0 0 0 1 0 0 ×´ ×´ EV5 EV4 EV3 EV2 EV1 EV0 Select LCD bias 0 0 0 1 0 1 0 B2 B1 B0 SHL select 0 0 1 1 0 0 SHL ×´ ×´ ×´ Control power circuit operation 2-byte instruction to specify the Reference voltage Select LCD bias COM bi-directional selection SHL=0: normal direction SHL=1: reverse direction SEG bi-directional selection ADC select 0 0 1 0 1 0 0 0 0 ADC ADC=0: normal direction ADC=1: reverse direction Oscillator on start 0 0 1 0 1 0 1 0 1 1 Set power save mode 0 0 1 0 1 0 1 0 0 P Release power save mode 0 0 1 1 1 0 0 0 0 1 Release power save mode Reset 0 0 1 1 1 0 0 0 1 0 Initialize the internal functions ×´ ×´ 1 1 1 0 1 0 0 0 2-byte instruction to specify the ×´ ×´ D7 D6 D5 D4 D3 D2 D1 D0 NOP 0 0 1 1 1 0 0 0 1 1 No operation Test Instruction 0 0 1 1 1 1 ×´ ×´ ×´ ×´ Don't use this instruction. Set data direction & display data length(DDL) 38 Start the built-in oscillator P=0: normal mode P=1: sleep mode number of data bytes. (SPI Mode) KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD Table 17. Instruction Table (Continued) Instruction RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 Description DB0 FRC(1:3FRC, 0:4FRC) PWM1 PWM0 Set FRC and PWM mode Set white mode and 0 0 1 0 0 1 0 FRC PWM1 PWM0 0 0 1 0 0 0 1 0 0 0 pulse width 0 0 WB3 WB2 WB1 WB0 WA3 WA2 WA1 WA0 Set white mode and 0 0 1 0 0 0 1 0 0 1 0 0 WD3 WD2 WD1 WD0 WC3 WC2 WC1 WC0 0 0 1 0 0 0 1 0 1 0 0 0 LB3 LB2 LB1 LB0 LA3 LA2 LA1 LA0 0 0 1 0 0 0 1 0 1 1 0 0 LD3 LD2 LD1 LD0 LC3 LC2 LC1 LC0 0 0 1 0 0 0 1 1 0 0 0 0 DB3 DB2 DB1 DB0 DA3 DA2 DA1 DA0 0 0 1 0 0 0 1 1 0 1 0 0 DD3 DD2 DD1 DD0 DC3 DC2 DC1 DC0 Set black mode and 0 0 1 0 0 0 1 1 1 0 1st/2nd frame, set pulse width 0 0 BB3 BB2 BB1 BB0 BA3 BA2 BA1 BA0 Set black mode and 0 0 1 0 0 0 1 1 1 1 3rd/4th frame, set pulse width 0 0 BD3 BD2 BD1 BD0 BC3 BC2 BC1 BC0 1st/2nd frame, set 3rd/4th frame, set pulse width Set light gray mode and 1st/2nd frame, set pulse width Set light gray mode and 3rd/4th frame, set pulse width Set dark gray mode and 1st/2nd frame, set pulse width Set dark gray mode and 3rd/4th frame, set pulse width 0 0 0 1 9PWM 9PWM 1 0 12PWM 1 1 15PWM Set white mode and 1st/2nd frame Set white mode and 3rd/4th frame Set light gray mode and 1st/2nd frame Set light gray mode and 3rd/4th frame Set dark gray mode and 1st/2nd frame Set dark gray mode and 3rd/4th frame Set black mode and 1st/2nd frame Set black mode and 3rd/4th frame 39 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741 Read Display Data 8-bit data from Display Data RAM specified by the column address and page address can be read by this instruction. As the column address is increased by 1 automatically after each this instruction, the microprocessor can continuously read data from the addressed page. A dummy read is required after loading an address into the column address register. Display Data cannot be read through the serial interface. RS RW 1 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Read data Write Display Data 8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the column address and page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data to the addressed page. During auto-increment, the column address wraps to 0 after the last column is written RS RW 1 0 DB7 DB6 DB5 DB4 DB3 DB2 DB0 Write data Set Page Address Set Page Address Set Column Address Set Column Address Data Write Dummy Data Read Column = Column + 1 Column = Column + 1 Data Write Continue ? DB1 YES NO Optional Status Data Read Column = Column + 1 Data Read Continue ? YES NO Optional Status Figure 25. Sequence for Writing Display Data 40 Figure 26. Sequence for Reading Display Data KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD Read Status Indicates the internal status of the KS0741 RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 BUSY ON / OFF RES MF2 MF1 MF0 DS1 DS0 Flag Description The device is busy when internal operation or reset. Any instruction is rejected until BUSY goes Low. 0: chip is active, 1: chip is being busy BUSY ON / OFF RESET Indicates display ON / OFF status 0: display OFF, 1: display ON Indicates the initialization is in progress by RESET signal. 0: chip is active, 1: chip is being reset MF Manufacturer ID, MF2 MF1 MF0 = [0 0 0] DS Display size ID, DS1 DS0 = [1 0] ICON control register ON/OFF This instruction makes ICON enable or disable. By default, ICON display is disabled (ICON= 0). When ICON control register is set to “1”, ICON display is enabled and page address is set to “ 16”. Then user can write data for icons. It is impossible to set the page address to “16” by Set Page Address instruction. Therefore, when writing data for icons, ICON control register ON instruction would be used to set the page address to “ 16”. When ICON control register is set to “0”, ICON display is disabled. RS RW DB7 DB6 DB5 0 0 1 0 1 ICON=0: ICON disable (default) ICON=1: ICON enable & set the page address to 16 DB4 DB3 DB2 DB1 DB0 0 0 0 1 ICON 41 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741 Set Page Address Sets the Page Address of display data RAM from the microprocessor into the page address register. Any RAM data bit can be accessed when its Page Address and column address are specified. Along with the column address, the Page Address defines the address of the display RAM to write or read display data. Changing the Page Address doesn't effect to the display status. Set Page Address instruction can not be used to set the page address to “16”. Use ICON control register ON/OFF instruction to set the page address to “ 16”. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 1 P3 P2 P1 P0 P3 P2 P1 P0 Page 0 0 0 0 0 0 0 0 1 1 : : : : : 1 1 1 0 14 1 1 1 1 15 Set Column Address Sets the Column Address of display RAM from the microprocessor into the column address register. Along with the Column Address, the Column Address defines the address of the display RAM to write or read display data. When the microprocessor reads or writes display data to or from display RAM, Column Addresses are automatically increased. Set Column Address MSB RS RW DB7 0 0 0 Set Column Address LSB RS RW DB7 42 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 Y7 Y6 Y5 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Y3 Y2 Y1 0 0 0 0 0 0 Y4 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Column address [Y7:Y1] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : 1 1 1 1 1 1 0 126 1 1 1 1 1 1 1 127 KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD Set Modify-Read This instruction stops the automatic increment of the column address by the read display data instruction, but the column address is still increased by the write display data instruction. And it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. This mode is canceled by the reset Modify-Read instruction. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 0 0 0 0 Reset Modify-Read This instruction cancels the Modify-Read mode, and makes the column address return to its initial value just before the set Modify-Read instruction is started. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 1 1 1 0 Set Page Address Set Column Address (N) Set Modify-read Dummy Read Data Read Data Process Data Write NO Change Completed? YES Reset Modify-read Return Column Address (N) Figure 27. Sequence for Cursor Display 43 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741 Display ON / OFF Turns the display ON or OFF. This command has priority over Entire Display On/Off and Reverse Display On/Off. Commands are accepted while the display is off, but the visual state of the display does not change. RS RW 0 0 DON = 1: display ON DON = 0: display OFF DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 1 0 1 1 1 DON Set Initial Display Line Register Sets the line address of display RAM to determine the initial display line using 2-byte instruction. The RAM display data is displayed at the top of row(COM0) of LCD panel. The 1st Instruction RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 0 0 0 0 × × DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 S2 S1 S0 The 2nd Instruction RS RW 0 0 × S6 S5 S4 S3 S6 S5 S4 S3 S2 S1 S0 Line address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 2 0 0 0 0 0 1 1 3 : : : : : : : : 1 1 1 1 1 0 0 124 1 1 1 1 1 0 1 125 1 1 1 1 1 1 0 126 1 1 1 1 1 1 1 127 Setting Initial Display Line Start 1 st Instruction (2-byte Instruction for Mode Setting) 2 nd Instruction (2-byte Instruction for Register Setting) Setting Iinitial Display Line End Figure 28. The Sequence for Setting the Initial Display Line 44 KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD Set Initial COM0 Register Sets the initial row (COM) of the LCD panel using the 2-byte instruction. By using this instruction, it is possible to realize the window moving without the change of display data. The 1st Instruction RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 0 0 0 1 × × DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 C2 C1 C0 The 2nd Instruction RS RW 0 0 × C6 C5 C4 C3 C6 C5 C4 C3 C2 C1 C0 Initial COM0 0 0 0 0 0 0 0 COM0 0 0 0 0 0 0 1 COM1 0 0 0 0 0 1 0 COM2 0 0 0 0 0 1 1 COM3 : : : : : : : : 1 1 1 1 1 0 0 COM124 1 1 1 1 1 0 1 COM125 1 1 1 1 1 1 0 COM126 1 1 1 1 1 1 1 COM127 Setting Initial COM0 Start 1 st Instruction (Mode Setting) 2 nd Instruction (Initial COM0 Setting) Setting Initial COM0 End Figure 29. Sequence for Setting the Initial COM0 45 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741 Set Partial Display Duty Ratio Sets the duty ratio within range of 16 to 128 (ICON disabled) or 17 to 129 (ICON enabled) to realize partial display by using the 2-byte instruction. The 1st Instruction RS RW 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 0 0 1 0 × × DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D7 D6 D5 D4 D3 D2 D1 D0 0 The 2nd Instruction RS RW 0 0 Selected partial duty ratio (ICON disabled) Selected partial duty ratio (ICON enabled) No operation No operation 0 1/16 1/17 0 1 1/17 1/18 : : : : : 1 1 1 1 1/127 1/128 0 0 0 0 0 1/128 1/129 0 0 0 0 0 1 : : : : : : : No operation No operation 1 1 1 1 1 1 1 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 : : : : : : : : 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 0 0 0 1 0 0 : : : : : 0 1 1 1 1 0 0 1 0 : 1 Setting Partial Display Start 1st Instruction (Mode Setting) 2nd Instruction (Partial Display Duty Setting) Setting Partial Display End Figure 30. Sequence for Setting Partial Display 46 KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD Set N-line Inversion Register Sets the inverted line number within range of 3 to 33 to improve the display quality by controlling the phase of the internal LCD AC signal (M) by using the 2-byte instruction. The DC-bias problem could be occurred if K is even number. So, we recommend customers to set K to be odd number. K : D/N D : The number of display duty ratio (D is selectable by customers) N : N for N-line inversion (N is selectable by customers). The 1st Instruction RS RW 0 0 The 2nd Instruction RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 0 0 1 1 × × DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 N4 N3 N2 N1 N0 0 0 × × × N4 N3 N2 N1 N0 Selected n-line inversion 0 0 0 0 0 0-line inversion (frame inversion) 0 0 0 0 1 3-line inversion 0 0 0 1 0 4-line inversion 0 0 0 1 1 5-line inversion : : : : : : 1 1 1 0 1 31-line inversion 1 1 1 1 0 32-line inversion 1 1 1 1 1 33-line inversion Setting N -L ine In v e r s i o n S tart 1 2 nd st Instruction (M o d e S etting) Instruction (N -L ine In v e r s i o n S etting) Setting N -L ine In v e r s i o n E n d Figure 31. Sequence for N-line Inversion Release N-line Inversion Returns to the frame inversion condition from the n-line inversion condition. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 0 1 0 0 47 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741 Reverse Display ON / OFF Reverses the display status on LCD panel without rewriting the contents of the display data RAM. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 1 1 REV REV DDRAM data = “00” – White DDRAM data = “01” – Light gray DDRAM data = “10” – Dark gray DDRAM data = “11” – Dark 0 (normal) White (“00”) Light gray (“01”) Dark gray (“10”) Dark (“11”) 1 (reverse) Dark (“11”) Dark gray (“10”) Light gray (“01”) White (“00”) Entire Display ON / OFF Forces the whole LCD points to be turned on regardless of the contents of the display data RAM. At this time, the contents of the display data RAM are held. This instruction has priority over the Reverse Display ON / OFF instruction. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 1 0 EON EON DDRAM data = “00” – White DDRAM data = “01” – Light gray DDRAM data = “10” – Dark gray DDRAM data = “11” – Dark 0 (normal) White (“00”) Light gray (“01”) Dark gray (“10”) Dark (“11”) 1 (entire) Dark (“11”) Dark (“11”) Dark (“11”) Dark (“11”) Power Control Selects one of eight power circuit functions by using 3-bit register. An external power supply and part of internal power supply functions can be used simultaneously. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 1 VC VR VF VC VR VF 0 1 Internal voltage converter circuit is OFF Internal voltage converter circuit is ON 0 1 Internal voltage regulator circuit is OFF Internal voltage regulator circuit is ON 0 1 48 Status of internal power supply circuits Internal voltage follower circuit is OFF Internal voltage follower circuit is ON KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD Select DC-DC Step-up Selects one of 4 DC-DC step-up to reduce the power consumption by this instruction. It is very useful to realize the partial display function. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 1 0 0 1 DC1 DC0 DC1 DC0 Selected DC-DC converter circuit 0 0 3 times boosting circuit 0 1 4 times boosting circuit 1 0 5 times boosting circuit 1 1 6 times boosting circuit Select Regulator Resistor Selects resistance ratio of the internal resistor used in the internal voltage regulator. See voltage regulator section in power supply circuit. Refer to the table 14. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 0 R2 R1 R0 R2 R1 R0 1+ (Rb / Ra) 0 0 0 2.3 0 0 1 3.0 0 1 0 3.7 0 1 1 4.4 1 0 0 5.1 1 0 1 5.8 1 1 0 6.5 1 1 1 7.2 49 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741 Set Electronic Volume Register Consist of 2-byte Instructions The 1st instruction set Reference Voltage mode, the 2nd one updates the contents of reference voltage register. After second instruction, Reference Voltage mode is released. The 1st Instruction: Set Reference Voltage Select Mode RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 The 2nd Instruction: Set Reference Voltage Register RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 EV3 EV2 EV1 EV0 0 0 1 0 0 0 0 × × EV5 EV4 EV5 EV4 EV3 EV2 EV1 EV0 Reference voltage parameter (α) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63 Setting Reference Voltage Start 1st Instruction for Mode Setting 2nd Instruction for Register Setting Setting Reference Voltage End Figure 32. Sequence for Setting the Electronic Volume 50 KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD Select LCD Bias Selects LCD bias ratio of the voltage required for driving the LCD. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 0 1 0 B2 B1 B0 B2 B1 B0 LCD bias 0 0 0 1/5 0 0 1 1/6 0 1 0 1/7 0 1 1 1/8 1 0 0 1/9 1 0 1 1/10 1 1 0 1/11 1 1 1 1/12 SHL Select COM output scanning direction is selected by this instruction which determines the LCD driver output status. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 0 0 1 1 0 0 SHL × × SHL = 0: normal direction (COM0 → COM127) SHL = 1: reverse direction (COM127 → COM0) DB0 × × : Don’ t care ADC Select Changes the relationship between RAM column address and segment driver. The direction of segment driver output pins could be reversed by software. This makes IC layout flexible in LCD module assembly. RS RW DB7 DB6 DB5 0 0 1 0 1 ADC = 0: normal direction (SEG0 → SEG127) ADC = 1: reverse direction (SEG127 → SEG0) DB4 DB3 DB2 DB1 DB0 0 0 0 0 ADC 51 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741 Oscillator ON Start This instruction enables the built-in oscillator circuit. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 1 0 1 1 Power Save The KS0741 enters the Power Save status to reduce the power consumption to the static power consumption value and returns to the normal operation status by the following instructions. Set Power Save Mode RS RW DB7 0 0 P = 0: normal mode P = 1: sleep mode 1 Release Power Save Mode RS RW DB7 0 0 1 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 0 1 0 0 P DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 0 0 0 0 1 Set Power Save Mode (Sleep Mode) Sleep Mode Oscillator Circuits: OFF LCD Power Supply Circuits: OFF All COM / SEG Output Level: VSS Consumption Current < 2uA Release Power Save Mode (Sleep Mode) Figure 33. Power Save Routine 52 KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD Reset This instruction Resets initial display line, column address, page address, and common output status select to their initial status, but dose not affect the contents of display data RAM. This instruction cannot initialize the LCD power supply, which is initialized by the RESETB pin. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 0 0 1 0 Set Data Direction & Display Data Length (3-Pin SPI Mode) Consists of 2 bytes instruction. This command is used in 3-Pin SPI mode only(PS0 = ”L” and PS1 = ” L” ). It will be two continuous commands, the first byte control the data direction(write mode only) and inform the LCD driver the second byte will be number of data bytes will be write. When RS is not used, the Display Data Length instruction is used to indicate that a specified number of display data bytes are to be transmitted. The next byte after the display data string is handled as command data. The 1st Instruction: Set Data Direction (Only Write Mode) RS RW DB7 DB6 DB5 DB4 x x 1 1 1 0 The 2nd Instruction: Set Display Data Length (DDL) Register RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 0 DB3 DB2 DB1 DB0 D0 x x D7 D6 D5 D4 D3 D2 D1 D7 D6 D5 D4 D3 D2 D1 D0 Display Data Length 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 2 0 0 0 0 0 0 1 0 3 : : : : : : : : : 1 1 1 1 1 1 0 1 254 1 1 1 1 1 1 1 0 255 1 1 1 1 1 1 1 1 256 RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 0 0 1 1 NOP No operation 53 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741 Test Instruction This instruction is for testing IC. Please do not use it. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 1 × × × × Set PWM & FRC mode Selects 3/4 FRC and 9 / 12 / 15 PWM RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 0 1 0 FRC PWM1 PWM0 FRC PWM1 PWM0 0 1 4FRC 3FRC 0 0 1 1 54 Status of PWM & FRC 0 1 0 1 9PWM 9PWM 12PWM 15PWM KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD Set Gray Scale Mode & Register Consists of 2 bytes instruction. The first byte sets grayscale mode and the second byte updates the contents of gray scale register without issuing any other instruction. − − Set Gray Scale Mode RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 0 0 1 GM2 GM1 GM0 GM2 GM1 GM0 Description 0 0 0 In case of setting white mode and 1st / 2nd frame 0 0 1 In case of setting white mode and 3rd / 4th frame 0 1 0 In case of setting light gray mode and 1st / 2nd frame 0 1 1 In case of setting light gray mode and 3rd / 4th frame 1 0 0 In case of setting dark gray mode and 1st / 2nd frame 1 0 1 In case of setting dark gray mode and 3rd / 4th frame 1 1 0 In case of setting black mode and 1st / 2nd frame 1 1 1 In case of setting black mode and 3rd / 4th frame Set Gray Scale Register RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 GB3 GB2 GB1 GB0 GA3 GA2 GA1 GA0 0 0 GD3 GD2 GD1 GD0 GC3 GC2 GC1 GC0 GA3, GB3, GC3, GD3 GA2, GB2, GC2, GD2 GA1, GB1, GC1, GD1 GA0, GB0, GC0, GD0 Pulse width (9PWM) Pulse width (12PWM) Pulse width (15PWM) 0 0 0 0 0/9 0/12 0/15 0 0 0 1 1/9 1/12 1/15 : : : : : : : 1 0 0 1 9/9 9/12 9/15 1 0 1 0 0/9 10/12 10/15 1 0 1 1 0/9 11/12 11/15 1 1 0 0 0/9 12/12 12/15 1 1 0 1 0/9 0/12 13/15 1 1 1 0 0/9 0/12 14/15 1 1 1 1 0/9 0/12 15/15 ∗ GA3=WA3,LA3,DA3,BA3 GA2=WA2,LA2,DA2,BA2 GA1=WA1,LA1,DA1,BA1 GA0=WA0,LA0,DA0,BA0 GB3=WB3,LB3,DB3,BB3 GA2=WB2,LB2,DB2,BB2 GA1=WB1,LB1,DB1,BB1 GA0=WB0,LB0,DB0,BB0 GC3=WC3,LC3,DC3,BC3 GA2=WC2,LC2,DC2,BC2 GA1=WC1,LC1,DC1,BC1 GA0=WC0,LC0,DC0,BC0 GD3=WD3,LD3,DD3,BD3 GA2=WD2,LD2,DD2,BD2 GA1=WD1,LD1,DD1,BD1 GA0=WD0,LD0,DD0,BD0 55 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 Referential Instruction Setup Flow: Initializing with the built-in Power Supply Circuits User System Setup by External Pins Start of Initialization Power ON (VDD-VSS) Keeping the RESETB Pin = "L" Waiting for Stabilizing the Power RESETB Pin = "H" User Application Setup by Internal Instructions [Display Duty Select] [ADC Select] [SHL Select] [COM0 Register Select] User LCD Power Setup by Internal Instructions [Oscillator ON] [DC-DC Step-up Register Select] [Regulator Resistor Select] [Electronic Volume Register Select] [LCD Bias Register Select] [Gray-scale Select] [Power Control] Waiting for Stabilizing the LCD Power Levels End of Initialization Figure 34. Initializing with the Built-in Power Supply Circuits 56 KS0741 KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD Referential Instruction Setup Flow: Initializing without the built-in Power Supply Circuits User System Setup by External Pins Start of Initialization Power ON (VDD-VSS) Keeping the RESETB Pin = "L" Waiting for Stabilizing the Power RESETB Pin = "H" Set Power Save User Application Setup by Internal Instructions [Display Duty Select] [ADC Select] [SHL Select] [COM0 Register Select] User LCD Power Setup by Internal Instructions [Oscillator ON] Regulator or Follower Register Select [Gray-scale Select] [Power Control] Release Power Save Waiting for Stabilizing the LCD Power Levels End of Initialization Figure 35. Initializing without the Built-in Power Supply Circuits 57 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 Referential Instruction Setup Flow: Data Displaying End of Initialization Display Data RAM Addressing by Instruction [Initial Display Line] [Set Page Address] [Set Column Address] Write Display Data by Instruction [Display Data Write] Turn Display ON / OFF Instruction [Display ON / OFF] End of Data Display Figure 36. Data Displaying Referential Instruction Setup Flow: Power OFF Optional Status Set Power Save by Instruction Power OFF (VDD-VSS) End of Power OFF Figure 37. Power OFF 58 KS0741 KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD Referential Instruction Setup Flow: Partial Duty Changing Start of Partial changing Set Display OFF by Internal [Display ON / OFF] Set Sleep Mode by Internal Instruction [Power Save Mode] Set Partial Duty by Internal Instructions [Partial Display Duty Ratio Select] [Initial Display Line Register] [COM0 Register Select] User LCD Power Setup by Internal Instructions [DC-DC Step-up Register Select] [Regulator Resistor Select] [Electronic Volume Register Select] [LCD Bias Register Select] [Power Control] [Gray-scale Select] Waiting for Discharging the LCD Power Levels Release Power Save Waiting for Stabilizing the LCD Power Levels Write Display Data & Display ON by Internal Instruction [Display Data Write] [Display ON / OFF] End of Partial Changing Figure 38. Partial Duty Changing 59 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741 SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Table 18. Absolute Maximum Ratings Parameter Rating VDD - 0.3 ~ + 7.0 V V0, VOUT - 0.3 ~ + 17.0 V V1, V2, V3, V4 - 0.3 ~ V0 + 0.3 V External reference voltage VEXT +0.3 ~ VDD Input voltage range VIN - 0.3 ~ VDD + 0.3 V Operating temperature range TOPR - 40 ~ + 85 °C Storage temperature range TSTR - 55 ~ + 125 °C Supply voltage range NOTES: 1. VDD, V0, VOUT, V1 to V4 and VEXT are based on VSS = 0V. 2. Voltages V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS must always be satisfied.(VLCD = V0 – VSS) 3. If supply voltage exceeds its absolute maximum range, this LSI may be damaged permanently. It is desirable to use this LSI under electrical characteristic conditions during general operation. Otherwise, this LSI may malfunction or reduced LSI reliability may result. 60 (VSS = 0V) Unit Symbol KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD DC CHARACTERISTICS Table 19. DC Characteristics (VSS = 0V, VDD = 1.8 to 3.3V, Ta = -40 to 85°C) Item Symbol Operating voltage (1) Condition Min. Typ. Max. Unit Pin used VDD 1.8 - 3.3 V VDD *1 Operating voltage (2) V0 4.0 - 15.0 V V0 *2 High VIH 0.8VDD - VDD V *3 Low VIL VSS - 0.2VDD High VOH IOH = -0.5mA 0.8VDD - VDD V *4 Low VOL IOL = 0.5mA VSS - 0.2VDD Input voltage Output voltage Input leakage current IIL VIN = VDD or VSS - 1.0 - + 1.0 µA *3 Output leakage current IOZ VIN = VDD or VSS - 3.0 - + 3.0 µA *5 LCD driver ON resistance RON Ta = 25°C, V0 = 8V - 2.0 3.0 kΩ SEGn COMn *6 Operating frequency f FR Ta = 25°C 1/128 Duty, 9 PWM REXT = TBDkΩ 70 85 100 Hz *7 ×3 1.8 - 5.0 ×4 1.8 - 3.75 ×5 V VCI 1.8 - 3.0 ×6 1.8 - 2.5 x3 / ×4 / ×5 / ×6 voltage conversion (no-load ) 95 99 - % VOUT Voltage converter Input voltage VCI Voltage converter output voltage VOUT Voltage regulator operating voltage VOUT 5.4 - 15.0 V VOUT Voltage follower operating voltage V0 4.0 - 15.0 V V0 *8 Reference voltage VREF 2.04 2.10 2.16 V *9 Ta = 25°C 61 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741 Dynamic Current Consumption (1) when An External Power Supply is used. Table 20. Dynamic Current 1 (External Power) (VDD = 3.0V, Ta = 25°C) Item Dynamic current consumption (1) Symbol Condition Min Typ Max Unit Pin used V0-Vss = 11.0V, duty = 1/128 (Display Off) - - TBD µΑ *10 V0-Vss = 11.0V, duty = 1/128 (Display On , Checker Pattern) - - TBD µΑ *10 IDD1 Dynamic Current Consumption (2) when The Internal Power Supply is ON Table 21. Dynamic Current 2 (Internal Power) Item Dynamic current consumption (2) Symbol (VDD = 3.0V, Ta = 25°C) Max. Unit Pin used Condition Min. Typ. V0 - Vss = 12.0V, x5 boosting, duty = 1/128, normal mode (Display Off) - - TBD µΑ *10 V0 - Vss = 12.0V, x5 boosting, duty = 1/128, normal mode (Display On , Checker Pattern) - - TBD µΑ *10 IDD2 Current Consumption during Power Save Mode Table 22. Power Save Mode Current (VDD = 3.0V, Ta = 25°C) 62 Item Symbol Condition Min. Typ. Max. Unit Pin used Sleep mode current IDDS1 During sleep - - TBD µΑ *10 KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD Table 23. The Relationship between Oscillation Frequency and Frame Frequency Duty ratio 1/N Item fCL fosc On-chip oscillator circuit is fFR x N fFR x PWM x 2 x N used (f OSC: oscillation frequency, f CL: display clock frequency, f FR: frame frequency, N = 16 to 129) [* Remark Solves] *1. Though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from the MPU. *2. In case of external power supply is applied. *3. CSB, RS, DB0 to DB7, E_RD, RW_WR, RESETB, PS1, PS0, INTRS, HPMB and REF *4. DB0 to DB7 *5. Applies when the DB0 to DB7 pins are in high impedance. *6. Resistance value when -0.1[mA] is applied during the ON status of the output pin SEGn or COMn. RON [kΩ] = ∆V[V] / 0.1[mA] (∆V : voltage change when -0.1[mA] is applied in the ON status.) *7. See Table 23 for the relationship between oscillation frequency and frame frequency. *8. The voltage regulator circuit adjusts V0 within the voltage follower operating voltage range. *9. On-chip reference voltage source of the voltage regulator circuit to adjust V0. *10. Applies to the case where the on-chip oscillation circuit is used and no access is made from the MPU. The current consumption, when the built-in power supply circuit is ON or OFF. The current flowing through voltage regulation resistors(Rb and Ra) is not included. It does not include the current of the LCD panel capacity, wiring capacity, etc. 63 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741 AC CHARACTERISTICS Read / Write Characteristics (8080-series MPU) RS tAS80 tAH80 tCY80 tPWL /RD, /WR CS1B 0.9VDD 0.1VDD tPWH tDS80 tDH80 DB0 to DB7 ( Write ) tACC80 tOD80 DB0 to DB7 ( Read ) Figure 39. Read / Write Characteristics (8080-series MPU) Item Signal Symbol Address setup time Address hold time RS tAS80 tAH80 0 0 25 - ns tCY80 330 - ns tPWL tPWH 60 60 - ns tDS80 tDH80 40 10 - ns 15 10 50 ns System cycle time Pulse width low Pulse width high Data setup time Data hold time Read access time Output disable time /WR /RD DB0 to DB7 tACC80 tOD80 Condition (VDD = 1.8V, Ta = -40 ~ +85°C) Min. Max. Unit CL = 100 pF Item Signal Symbol Address setup time Address hold time RS tAS80 tAH80 0 0 25 - ns tCY80 166 - ns tPWL tPWH 50 50 - ns tDS80 tDH80 30 5 - ns 15 10 50 ns System cycle time Pulse width low Pulse width high Data setup time Data hold time Read access time Output disable time /WR /RD DB0 to DB7 tACC80 tOD80 Condition (VDD = 2.7V, Ta = -40 ~ +85°C) Min. Max. Unit CL = 100 pF NOTE: *1. The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. (tr + tf) < (tCY80 - tPWLW - tPWHW ) for write, (tr + tf) < (tCY80 - tPWLR - tPWHR ) for read 64 KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD Read / Write Characteristics (6800-series Microprocessor) RS, R/W tAS68 tAH68 tCY68 tEWL E CSB 0.1VDD 0.9VDD tEWH tDS68 tDH68 DB0 to DB7 ( Write ) tACC68 tOD68 DB0 to DB7 ( Read ) Figure 40. Read / Write Characteristics (6800-series Microprocessor) Signal Symbol Address setup time Address hold time RS RW tAS68 tAH68 0 0 25 - ns tCY68 330 - ns tEWH tEWL 60 60 - ns tDS68 tDH68 40 10 - ns 15 10 50 ns System cycle time Enable width high Enable width low Data setup time Data hold time Read access time Output disable time E_RD (E) DB0 to DB7 tACC68 tOD68 Condition (VDD = 1.8V, Ta = -40 ~ +85°C) Min. Max. Unit Item CL = 100 pF Item Signal Symbol Address setup time Address hold time RS RW tAS68 tAH68 0 0 25 - ns tCY68 166 - ns tEWH tEWL 50 50 - ns tDS68 tDH68 30 5 - ns 15 10 50 ns System cycle time Enable width high Enable width low Data setup time Data hold time Read access time Output disable time E_RD (E) DB0 to DB7 tACC68 tOD68 Condition (VDD = 2.7V, Ta = -40 ~ +85°C) Min. Max. Unit CL = 100 pF NOTE: *1. The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. (tr + tf) < (t CY68 - tEWHW - tEWLW ) for write, (tr + tf) < (t CY68 - tEWHR - tEWLR ) for read 65 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741 Serial Interface Characteristics tCSS tCHS CSB tASS tAHS RS tCYS DB6 (SCLK) 0.9VDD 0.1VDD tWLS tWHS tDSS tDHS DB7 (SID) Figure 41. Serial Interface Characteristics Condition (VDD = 1.8V, Ta = -40 ~ +85°C) Min. Max. Unit Item Signal Symbol Serial clock cycle SCLK high pulse width SCLK low pulse width DB6 (SCLK) tCYS tWHS tWLS 111 60 60 - ns Address setup time Address hold time RS tASS tAHS 60 60 - ns Data setup time Data hold time DB7 (SID) tDSS tDHS 60 60 - ns CSB setup time CSB hold time CSB tCSS tCHS 60 1/2 * tCYS - ns Item Signal Symbol Serial clock cycle SCLK high pulse width SCLK low pulse width DB6 (SCLK) tCYS tWHS tWLS 58.8 30 30 - ns Address setup time Address hold time RS tASS tAHS 30 30 - ns Data setup time Data hold time DB7 (SID) tDSS tDHS 30 30 - ns CSB setup time CSB hold time CSB tCSS tCHS 30 1/2 * tCYS - ns Condition NOTE: *1. The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. 66 (VDD = 2.7V, Ta = -40 ~ +85°C) Min. Max. Unit KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD Reset Input Timing tRW RESETB tR During reset Internal status Reset complete Figure 42. Reset Input Timing Condition (VDD = 1.8 ~ 3.3V, Ta = -40 ~ +85°C) Min. Max. Unit Item Signal Symbol Reset low pulse width RESETB tRW 1000 - ns Reset time - tR - 1000 ns 67 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 REFERENCE APPLICATIONS MICROPROCESSOR INTERFACE In Case of Interfacing with 6800-series (PS0 = “H”, PS1 = “H”) 6800-series MPU CSB RS E RW DB0 to DB7 RESETB VDD VDD CSB RS KS0741 E_RD RW_WR DB0 to DB7 RESETB PS0 PS1 Figure 43. Interfacing with 6800-series (PS0 = “H”, C68 = “H”) In Case of Interfacing with 8080-series (PS0 = “H”, PS1 = “L”) 8080-series MPU CSB RS /RD /W R DB0 to DB7 RESETB VDD VSS CSB RS E_RD KS0741 RW_WR DB0 to DB7 RESETB PS0 PS1 Figure 44. Interfacing with 8080-series (PS0 = “H”, C68 = “L”) 68 KS0741 KS0741 PRELIMINARY SPEC. VER. 1.2 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD In Case of 4-pin SPI mode (PS0 = "L" , PS1 = "H" ) MPU CSB RS SID SCLK RESETB OPEN VSS VDD CSB RS KS0741 DB7(SID) DB6(SCLK) RESETB DB0 to DB5 PS0 PS1 Figure 45. Serial Interface (PS0 = “L”, PS1 = “H”) In Case of 3-pin SPI mode (PS0 = "L" , PS1 = "L" ) CSB MPU SID SCLK RESETB OPEN VSS VSS CSB KS0741 DB7(SID) DB6(SCLK) RESETB DB0 to DB5 PS0 PS1 Figure 46. Serial Interface (PS0 = “L”, PS1 = “L”) 69 128 SEG / 129 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.2 KS0741 CONNECTIONS BETWEEN KS0741 AND LCD PANEL Single Chip Configuration (1/129 Duty Configurations) COMS COM127 : COM64 KS0741 (Bottom View) SEG127 ........... ♣ ♦ ♥ ♠ Ξ COM63 : COM0 COMS SEG0 COM63 : COM0 COMS SEG0 ............ ♣ 129 × 128 pixels ♣ ♦ ♥ ♠ Ξ ♦ ♥ ♠ ♦ ♣ ♦ ♥ ♠ ♣ Ξ ♣ ........... KS0741 (Bottom View) COM64 : COM127 COMS Figure 49. SHL = 1, ADC = 0 70 Ξ ♦ ♥ ♠ Ξ ♦ ♥ ♠ Ξ 129 × 128 pixels Ξ SEG0 COMSSEG127 COM0 : COM63 ♠ Figure 48. SHL = 0, ADC = 0 129 × 128 pixels ♣ ♥ 129 × 128 pixels Figure 47. SHL = 0, ADC = 1 ♣ COMS COM127 : COM64 KS0741 (Top View) ♦ ♥ ♠ Ξ SEG127 COM127 SEG0 : COM64 COMS ........... KS0741 (Top View) COMS COM0 : COM63 Figure 50. SHL = 1, ADC = 1