S6B1400X 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD Mar. 2002 Ver. 0.0 Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team. Precautions for Light Light has characteristics to move electrons in the integrated circuitry of semiconductors, therefore may change the characteristics of semiconductor devices when irradiated with light. Consequently, the users of the packages which may expose chips to external light such as COB, COG, TCP and COF must consider effective methods to block out light from reaching the IC on all parts of the surface area, the top, bottom and the sides of the chip. Follow the precautions below when using the products. 1. Consider and verify the protection of penetrating light to the IC at substrate (board or glass) or product design stage. 2. Always test and inspect products under the environment with no penetration of light. 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X S6B1400X Specification Revision History Version 0.0 2 Content Initial version Date 2002.03 S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD CONTENTS INTRODUCTION ............................................................................................................................................ 1 FEATURES .................................................................................................................................................... 1 BLOCK DIAGRAM ......................................................................................................................................... 3 PAD CONFIGURATION ................................................................................................................................. 4 PAD CENTER COORDINATES ...................................................................................................................... 6 POWER SUPPLY .................................................................................................................................... 8 LCD DRIVER SUPPLY ............................................................................................................................ 8 SYSTEM CONTROL................................................................................................................................ 9 MICROPROCESSOR INTERFACE .........................................................................................................10 LCD DRIVER OUTPUTS .........................................................................................................................12 FUNCTIONAL DESCRIPTION .......................................................................................................................13 MICROPROCESSOR INTERFACE .........................................................................................................13 DISPLAY DATA RAM (DDRAM) ..............................................................................................................18 LCD DISPLAY CIRCUITS .......................................................................................................................21 LCD DRIVER CIRCUITS .........................................................................................................................23 POWER SUPPLY CIRCUITS ..................................................................................................................24 RESET CIRCUIT ....................................................................................................................................30 INSTRUCTION DESCRIPTION ......................................................................................................................31 SPECIFICATIONS .........................................................................................................................................46 ABSOLUTE MAXIMUM RATINGS ...........................................................................................................46 DC CHARACTERISTICS ........................................................................................................................47 AC CHARACTERISTICS .........................................................................................................................50 REFERENCE APPLICATIONS ......................................................................................................................54 MICROPROCESSOR INTERFACE .........................................................................................................54 CONNECTIONS BETWEEN S6B1400X AND LCD PANEL .......................................................................56 3 S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD INTRODUCTION The S6B1400X is a single-chip driver & controller LSI for graphic dot-matrix liquid crystal display systems. This chip can be connected directly to a microprocessor, accepts serial or 8-bit parallel display data from the microprocessor, stores the display data in an on-chip display data RAM of 65 x 104 bits and generates a liquid crystal display drive signal independent of the microprocessor. It provides a high-flexible display section due to 1-to-1 correspondence between on-chip display data RAM bits and LCD panel pixels. It contains 65 common driver circuits and 104 segment driver circuits, so that a single chip can drive a 65 x 104 dot display. This chip is able to minimize power consumption because it performs display data RAM read/write operation with no external operation clock. In addition, because it contains power supply circuits necessary to drive liquid crystal, which is a display clock oscillator circuit, high performance voltage converter circuit, high-accuracy voltage regulator circuit, low power consumption voltage divider resistors and OP-Amp for liquid crystal driver power voltage, it is possible to make the lowest power consumption display system with the fewest components for high performance portable systems. FEATURES Display Driver Output Circuits − 65 common outputs and 104 segment outputs On-chip Display Data RAM − − − Capacity: 65 x 104 = 6,760 bits RAM bit data “1”: a dot of display is illuminated RAM bit data “0”: a dot of display is not illuminated Applicable Duty Ratios Duty ratio Applicable LCD bias Maximum display area 1/65 1/7 or 1/9 65 × 104 1/55 1/6 or 1/8 55 × 104 1/49 1/6 or 1/8 49 × 104 1/33 1/5 or 1/6 33 × 104 Microprocessor Interface − − High-speed 8-bit parallel bi-directional interface with 6800-series or 8080-series SPI (Serial Peripheral Interface) available. (only write operation) Various Function Set − − − Display ON / OFF, set initial display line, set page address, set column address, read status, write/read display data, select segment driver output, reverse display ON / OFF, entire display ON / OFF, select LCD bias, set/reset modify-read, select common driver output, control display power circuit, select internal regulator resistor ratio for VLCD voltage regulation, electronic volume, set static indicator state. H/W and S/W Reset available Static drive circuit equipped internally for indicators with 4 flashing mode 1 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X Built-in Analog Circuit − − − − − − On-chip oscillator circuit for display clock High performance voltage converter (with booster ratios of x3 and x4) High accuracy voltage regulator (temperature coefficient: -0.05 ± 0.03%/°C or external input) Electronic contrast control function (64 steps) Vref = 2.1V ± 3% (V LCD voltage adjustment voltage) High performance voltage follower (V1 to V4 voltage divider resistors and OP-Amp for increasing drive capacity) Operating Voltage Range − − − Supply voltage (V DD): 2.4 to 3.6 V Booster input voltage (VCI): VDD to 3.0 V (x4), VDD to 3.6 V (x3) LCD driving voltage (V LCD): 4.5 to 9.0 V Low Power Consumption − − Operating power: 120 µΑ typical (conditions: VDD = 3V, x 3 boosting (VCI = VDD), VLCD = 7.6V, Internal power supply ON, display OFF and normal mode is selected) Standby power: 10 µΑ maximum (during power save[standby] mode) Operating Temperatures − Wide range of operating temperatures : -40 to 85°C CMOS Process Package Type − 2 Gold bumped chip S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD BLOCK DIAGRAM COM31 : COM0 COMS0 SEG103 SEG102 SEG101 : : SEG2 SEG1 SEG0 COM32 : COM63 COMS1 V DD 33 COMMON DRIVER CIRCUITS 104 SEGMENT DRIVER CIRCUITS 33 COMMON DRIVER CIRCUITS VSS DISPLAY DATA CONTROL CIRCUIT HPMB V/F CIRCUIT PAGE I/O ADDRESS BUFFER CIRCUIT VLCD VR INTRS REF VEXT COMMON OUTPUT CONTROLLER CIRCUIT V/R CIRCUIT LINE DISPLAY DATA RAM ADDRES 65 X 104 = 6,760 Bits S CIRCUIT DISPLAY TIMING GENERATOR CIRCUIT CL FRS FR DUTY0 DUTY1 COLUMN ADDRESS CIRCUIT OSCILLATOR VCI DCDC4B V/C CIRCUIT STATUS REGISTER INSTRUCTION REGISTER BUS HOLDER INSTRUCTION DECODER MPU INTERFACE (PARALLEL & SERIAL) DB0 DB1 DB2 DB3 DB4 DB5 DB6(SCLK) DB7(SID) C68 RESETB PS RW_WRB E_RDB RS CS2 CS1B Figure 1. Block Diagram 3 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X PAD CONFIGURATION 300 125 ððð ððððððððððððððððððð - - - - - - - - - - ððððððððððððððððððð ððð S6B1400X Y (TOP VIEW) (0,0) X ðððððððððððððððððððððð - - - - - - - - - - ðððððððððððððððð 1 TOM 123 Figure 2. S6B1400X Chip Configuration Item Chip size Chip height Pad pitch Bumped pad size (TOP) Bumped pad height 4 Table 1. S6B1400X Pad Dimensions Size Pad No. X Y 11080 1970 - 470u(+/- 10) 1 to 123 70(Min.) 125 to 300 60(Min.) µm 1 to 123 50 100 124, 301 110 40 125 to 300 40 110 All pad Unit 14 (Typ.) ð ð 301 124 S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD COG Align Key Coordinate 30µm 30µm 30µm 30µm 30µm 30µm 42µm 108µm 42µm 108µm (5460, -895) 42µm 108µm 30µm (5425, 845.05) 108µm 42µm (-5470, 915) 60µm 30µm 30µm 30µm (-5295, -830) ILB Align Key Coordinate(with Gold Bump *) * When designing COG pattern, ITO pattern must be prohibited on ILB Align Key, DUMMY pads, TEST pads. If ITO pattern is used for routing over these area, it can be happened pattern-short through bumped pattern on these area. TOM (TEG On Main chip) Coordinate The TOM has test items for process evaluation. There are many bumped PADs in this area as like main chip. So when designing COG pattern, ITO pattern must be prohibited on this area (TOM). If ITO pattern is used for routing over this area, it can be happened pattern-short through bumped PAD on TOM. 600µm (5080 ,-695) 220 µm (4480,-915) 5 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X PAD CENTER COORDINAT ES Table 2. Pad Center Coordinates [Unit: µm] Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 6 Pad Name DUMMY<0> FRS FRI CL TEST VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VDD DB<0> DB<1> DB<2> DB<3> DB<4> DB<5> DB<6> DUMMY<1> DUMMY<2> DB<7> DUMMY<3> DUMMY<4> VSS DUTY0 VDD DUTY1 VSS RS VDD PS Coordinate X Y -5020 -870 -4950 -870 -4880 -870 -4810 -870 -4740 -870 -4670 -870 -4600 -870 -4530 -870 -4460 -870 -4390 -870 -4320 -870 -4250 -870 -4180 -870 -4110 -870 -4040 -870 -3970 -870 -3900 -870 -3830 -870 -3760 -870 -3690 -870 -3620 -870 -3550 -870 -3480 -870 -3410 -870 -3340 -870 -3270 -870 -3200 -870 -3130 -870 -3060 -870 -2990 -870 -2920 -870 -2850 -870 -2780 -870 -2710 -870 -2640 -870 -2570 -870 -2500 -870 -2430 -870 -2144 -870 -2074 -870 -2004 -870 -1718 -870 -1648 -870 -1578 -870 -1508 -870 -1438 -870 -1368 -870 -1298 -870 -1228 -870 -1158 -870 Pad No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pad Name VSS C68 VDD E_RDB RW_WRB VSS CS1B CS2 VDD VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VDD VEXT VSS REF VDD DCDC4B VSS HPMB VDD INTRS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Coordinate X Y -1088 -870 -1018 -870 -948 -870 -878 -870 -808 -870 -738 -870 -668 -870 -598 -870 -528 -870 -458 -870 -388 -870 -318 -870 -248 -870 -178 -870 -108 -870 -38 -870 32 -870 102 -870 172 -870 242 -870 312 -870 382 -870 452 -870 522 -870 592 -870 662 -870 732 -870 802 -870 872 -870 942 -870 1012 -870 1082 -870 1152 -870 1222 -870 1292 -870 1362 -870 1432 -870 1502 -870 1572 -870 1642 -870 1712 -870 1782 -870 1852 -870 1922 -870 1992 -870 2062 -870 2132 -870 2202 -870 2272 -870 2342 -870 Pad No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Pad Name VSS VR VSS TESTA0 TESTB0 VSS VLCD VLCD VLCD VLCD VLCD VLCD TESTA1 TESTB1 TESTA2 TESTB2 TESTA3 TESTB3 TESTA4 TESTB4 DUMMY<5> RESETB DUMMY<6> DUMMY<7> DUMMY<8> COM<31> COM<30> COM<29> COM<28> COM<27> COM<26> COM<25> COM<24> COM<23> COM<22> COM<21> COM<20> COM<19> COM<18> COM<17> COM<16> COM<15> COM<14> COM<13> COM<12> COM<11> COM<10> COM<9> COM<8> COM<7> Coordinate X Y 2412 -870 2482 -870 2552 -870 2622 -870 2692 -870 2762 -870 2832 -870 2902 -870 2972 -870 3042 -870 3112 -870 3182 -870 3252 -870 3322 -870 3392 -870 3462 -870 3532 -870 3602 -870 3888 -870 3958 -870 4244 -870 4314 -870 4384 -870 5420 722 5284 838 5224 838 5164 838 5104 838 5044 838 4984 838 4924 838 4864 838 4804 838 4744 838 4684 838 4624 838 4564 838 4504 838 4444 838 4384 838 4324 838 4264 838 4204 838 4144 838 4084 838 4024 838 3964 838 3904 838 3844 838 3784 838 S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD Table 2. Pad Center Coordinates (Continued) [Unit: µm] Pad No. Pad Name 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 COM<6> COM<5> COM<4> COM<3> COM<2> COM<1> COM<0> COMS<0> DUMMY<9> DUMMY<10> SEG<103> SEG<102> SEG<101> SEG<100> SEG<99> SEG<98> SEG<97> SEG<96> SEG<95> SEG<94> SEG<93> SEG<92> SEG<91> SEG<90> SEG<89> SEG<88> SEG<87> SEG<86> SEG<85> SEG<84> SEG<83> SEG<82> SEG<81> SEG<80> SEG<79> SEG<78> SEG<77> SEG<76> SEG<75> SEG<74> SEG<73> SEG<72> SEG<71> SEG<70> SEG<69> SEG<68> SEG<67> SEG<66> SEG<65> SEG<64> Coordinate X Y 3724 838 3664 838 3604 838 3544 838 3484 838 3424 838 3364 838 3304 838 3244 838 3184 838 3124 838 3064 838 3004 838 2944 838 2884 838 2824 838 2764 838 2704 838 2644 838 2584 838 2524 838 2464 838 2404 838 2344 838 2284 838 2224 838 2164 838 2104 838 2044 838 1984 838 1924 838 1864 838 1804 838 1744 838 1684 838 1624 838 1564 838 1504 838 1444 838 1384 838 1324 838 1264 838 1204 838 1144 838 1084 838 1024 838 964 838 904 838 844 838 784 838 Pad No. Pad Name 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 SEG<63> SEG<62> SEG<61> SEG<60> SEG<59> SEG<58> SEG<57> SEG<56> SEG<55> SEG<54> SEG<53> SEG<52> SEG<51> SEG<50> SEG<49> SEG<48> SEG<47> SEG<46> SEG<45> SEG<44> SEG<43> SEG<42> SEG<41> SEG<40> SEG<39> SEG<38> SEG<37> SEG<36> SEG<35> SEG<34> SEG<33> SEG<32> SEG<31> SEG<30> SEG<29> SEG<28> SEG<27> SEG<26> SEG<25> SEG<24> SEG<23> SEG<22> SEG<21> SEG<20> SEG<19> SEG<18> SEG<17> SEG<16> SEG<15> SEG<14> Coordinate X Y 724 838 664 838 604 838 544 838 484 838 424 838 364 838 304 838 244 838 184 838 124 838 64 838 4 838 -56 838 -116 838 -176 838 -236 838 -296 838 -356 838 -416 838 -476 838 -536 838 -596 838 -656 838 -716 838 -776 838 -836 838 -896 838 -956 838 -1016 838 -1076 838 -1136 838 -1196 838 -1256 838 -1316 838 -1376 838 -1436 838 -1496 838 -1556 838 -1616 838 -1676 838 -1736 838 -1796 838 -1856 838 -1916 838 -1976 838 -2036 838 -2096 838 -2156 838 -2216 838 Pad No. Pad Name 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 SEG<13> SEG<12> SEG<11> SEG<10> SEG<9> SEG<8> SEG<7> SEG<6> SEG<5> SEG<4> SEG<3> SEG<2> SEG<1> SEG<0> DUMMY<11> DUMMY<12> COM<32> COM<33> COM<34> COM<35> COM<36> COM<37> COM<38> COM<39> COM<40> COM<41> COM<42> COM<43> COM<44> COM<45> COM<46> COM<47> COM<48> COM<49> COM<50> COM<51> COM<52> COM<53> COM<54> COM<55> COM<56> COM<57> COM<58> COM<59> COM<60> COM<61> COM<62> COM<63> COMS<1> DUMMY<13> DUMMY<14> Coordinate X Y -2276 838 -2336 838 -2396 838 -2456 838 -2516 838 -2576 838 -2636 838 -2696 838 -2756 838 -2816 838 -2876 838 -2936 838 -2996 838 -3056 838 -3116 838 -3176 838 -3236 838 -3296 838 -3356 838 -3416 838 -3476 838 -3536 838 -3596 838 -3656 838 -3716 838 -3776 838 -3836 838 -3896 838 -3956 838 -4016 838 -4076 838 -4136 838 -4196 838 -4256 838 -4316 838 -4376 838 -4436 838 -4496 838 -4556 838 -4616 838 -4676 838 -4736 838 -4796 838 -4856 838 -4916 838 -4976 838 -5036 838 -5096 838 -5156 838 -5216 838 -5420 662 7 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X PIN DESCRIPTION POWER SUPPLY Table 3. Power Supply Pins Description Name I/O Description VDD Supply Power supply VSS Supply Ground LCD DRIVER SUPPLY Table 4. LCD Driver Supply Pins Description 8 Name I/O VLCD O DCDC4B I VR I VCI I VEXT I REF I Description LCD power supply output pin Connect this pin to VSS through capacitor.(Capacitor is greater than 1µF) 4 times boosting circuit enable input pin − DCDC4B = "H": 3 times boosting − DCDC4B = "L": 4 times boosting VLCD voltage adjustment pin It is valid only when internal voltage regulator resistors are not used (INTRS = “L”). This is the reference voltage for the voltage converter circuit for the LCD driving. Whether internal voltage converter use or not use, this pin should be fixed. The voltage should have the following range: 2.4V ≤ VCI ≤ 3.6V ( VCI ≥ VDD) This is the external-input reference voltage (V REF) for the internal voltage regulator. It is valid only when external VREF is used (REF = “L”). When using internal VREF, this pin is Open Select the external VREF voltage via VEXT pin − REF = "L": using the external VREF − REF = "H": using the internal VREF S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SYSTEM CONTROL Table 5. System Control Pins Description Name I/O CL O FRS O FR O INTRS I Description Display clock output pin Static driver segment output pin This pin is used together with the FR pin. Static driver common output pin This pin is used together with the FRS pin. Internal resistor select pin This pin selects the resistors for adjusting VLCD voltage level. − INTRS = “H”: the internal resistors are used − INTRS = “L”: the external resistors are used VLCD voltage is controlled by VR pin and external resistive divider. (* refer to page 28) The LCD driver duty ratio depends on the following table. DUTY0 DUTY1 HPMB I I DUTY1 DUTY0 Duty ratio L L 1/33 L H 1/49 H L 1/55 H H 1/65 Power control pin of the power supply circuits for LCD driver. − HPMB = “H”: normal mode − HPMB = “L”: high power mode 9 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X MICROPROCESSOR INTERFACE Table 6. Microprocessor Interface Pins Description Name I/O RESETB I Description Reset input pin When RESETB is “L”, initialization is executed. Parallel / Serial data input select input PS I PS Interface mode Chip select Data / instruction Data Read / Write Serial clock H Parallel CS1B, CS2 RS DB0 to DB7 E_RDB RW_WRB - L Serial CS1B, CS2 RS SID (DB7) Write only SCLK (DB6) *Note: In serial mode, it is impossible to read data from the on-chip RAM. And DB0 to DB5 are high impedance and E_RDB and RW_WRB must be fixed to either “H” or “L”. C68 CS1B CS2 RS I Microprocessor interface select input pin − PS = “H”, C68 = "H": 6800-series parallel MPU interface − PS = “H”, C68 = "L": 8080-series parallel MPU interface − PS = “L”, C68 = "H": 4 pin-SPI serial MPU interface − PS = “L”, C68 = "L": 3 pin-SPI serial MPU interface I Chip select input pins Data/instruction I/O is enabled only when CS1B is “L” and CS2 is “H”. When chip select is non-active, DB0 to DB7 may be high impedance. I Register select input pin − RS = "H": DB0 to DB7 are display data − RS = "L": DB0 to DB7 are control data * This pin must be fixed to either “H” or “L” in case of 3 pin-SPI serial MPU interface mode Read / Write execution control pin RW_WRB 10 C68 MPU Type RW_WRB H 6800-series RW Read / Write control input pin − RW_WRB = “H”: read − RW_WRB = “L”: write L 8080-series /WR Write enable clock input pin The data on DB0 to DB7 are latched at the rising edge of the RW_WRB signal. I Description S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD Table 6. Microprocessor Interface Pins Description (Continued) Name I/O Description Read / Write execution control pin C68 E_RDB I MPU Type E_RDB H 6800-series E L 8080-series /RD Description Read/Write control input pin − RW_WRB = “H”: When E_RDB is “H”, DB0 to DB7 are in an output status. − RW_WRB = “L”: The data on DB0 to DB7 are latched at the falling edge of the E_RDB signal. Read enable clock input pin When E_RDB is “L”, DB0 to DB7 are in an output status. DB0 to DB7 I/O 8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data bus. When the serial interface selected (PS = "L"), − DB0 to DB5: high impedance − DB6: serial input clock (SCLK) − DB7: serial input data (SID) When chip select is not active, DB0 to DB7 may be high impedance. TESTs I/O These are pins for chip test. They are set to open. NOTE: DUMMYs – These pins should be opened (floated). 11 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X LCD DRIVER OUTPUTS Table 7. LCD Driver Output Pins Description Name I/O Description LCD segment driver outputs The display data and the FR signal control the output voltage of segment driver. SEG0 to SEG103 O Display data FR H Segment driver output voltage Normal display Reverse display H VLCD V2 H L VSS V3 L H V2 VLCD L L V3 VSS VSS VSS Power save mode LCD common driver outputs The internal scanning data and FR signal control the output voltage of common driver. COM0 to COM63 O Scan data FR Common driver output voltage H H VSS H L VLCD L H V1 L L V4 Power save mode COMS0 COMS1 12 O VSS Common output for the icons The output signals of two pins are same. When not used, these pins should be left open. S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD FUNCTIONAL DESCRIPTION MICROPROCESSOR INTERFACE Chip Select Input There are CS1B and CS2 pins for chip selection. The S6B1400X can interface with an MPU only when CS1B is “L” and CS2 is “H”. When these pins are set to any other combination, RS, E_RDB, and RW_WRB inputs are disabled and DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset. Parallel / Serial Interface S6B1400X has four types of interface with an MPU, which are two serial and two parallel interfaces. This parallel or serial interface is determined by PS pin as shown in table 8. Table 8. Parallel / Serial Interface Mode PS Type CS1B CS2 H Parallel CS1B CS2 L Serial CS1B CS2 C68 Interface mode H 6800-series MPU mode L 8080-series MPU mode H 4 pin-SPI serial MPU mode L 3 pin-SPI serial MPU mode Parallel Interface (PS = "H") The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by C68 as shown in table 9. The type of data transfer is determined by signals at RS, E_RDB and RW_WRB as shown in table 10. Table 9. Microprocessor Selection for Parallel Interface C68 CS1B CS2 RS E_RDB RW_WRB DB0 to DB7 MPU bus H CS1B CS2 RS E RW DB0 to DB7 6800-series L CS1B CS2 RS /RD /WR DB0 to DB7 8080-series Table 10. Parallel Data Transfer Common 6800-series 8080-series E_RDB (E) RW_WRB (RW) E_RDB (/RD) RW_WRB (/WR) Description RS H H H L H Display data read out H H L H L Display data write L H H L H Register status read L H L H L Writes to internal register (instruction) 13 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 CS1B CS2 RS RW_WRB E_RDB DB Command Write Data Write Status Read Data Read Figure 2-1. 6800-Series MPU Interface protocol (PS=”H”, C68=”H”) CS1B CS2 RS RW_WRB E_RDB DB Command Write Data Write Status Read Data Read Figure 2-2. 8080-Series MPU Interface Protocol (PS=”H”, C68=”L”) 14 S6B1400X S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD Serial Interface (PS = "L") When the S6B1400X is active (CS1B=”L”, CS2=”H”), serial data (DB7) and serial clock (DB6) inputs are enabled. And not active, the internal 8-bit shift register and the 3-bit counter are reset. The display data/command indication may be controlled either via software or the Register Select (RS) Pin, based on the setting of C68. When the RS pin is used (PS = “H”), data is display data when RS is high, and command data when RS is low. When RS is not used (C68 = “L”), the LCD Driver will receive command from MPU by default. If messages on the data pin are data rather than command, MPU should send Data Direction command (10000000) to control the data direction and then one more command to define the number of data bytes will be write. After these two continuous commands are sending, the following messages will be data rather than command. Serial data can be read on the rising edge of serial clock going into DB6 and processed as 8-bit parallel data on the eighth serial clock. And the DDRAM column address pointer will be increased by one automatically. The next bytes after the display data string is handled as command data. Serial data can be read on the rising edge of serial clock going into DB6 and processed as 8-bit parallel data on the eighth serial clock. Since the clock signal (DB6) is easy to be affected by the external noise caused by the line length, the operation check on the actual machine is recommended. The serial interface type is selected by setting C68 as shown in table 11. Table 11. Parallel / Serial Interface Mode Serial Mode PS C68 Chip Select Register Select Serial Data / Clock input 4 pin SPI serial mode L H CS1B, CS2 RS pin DB7 / DB6 3 pin SPI serial mode L L CS1B, CS2 Software DB7 / DB6 4 Pin SPI Serial Interface (PS = "L", C68 = "H") In 4-pin serial interface mode, RS pin is used for indicating whether serial data input is display or instruction data. Data is display data when RS is high and instruction data when RS is low. CS1B CS2 SID DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 SCLK RS Figure 3. 4 Pin SPI serial Interface Timing (RS used) 15 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X 3 Pin-SPI Interface (PS = "L", C68 = "L") In 3-Pin SPI Interface mode, the pre-defined instruction called Display Data Length, is used to indicate whether serial data input is display or instruction data instead of RS pin. The data is handled as instruction data until the Display Data Length instruction is issued. This Display Data Length instruction consists of two bytes instruction. The first byte instruction enables the next instruction to be valid, and the data of the second byte indicates that a specified number of display data bytes (1 to 256) are to be transmitted. The next byte after the display data string is handled as instruction data. For details, refers to figure 4. CS1B / CS2 3 Byte (1) SID Page MSB 15 0 829 830 831 ~ ~ ~ SCLK 7 8 ~ ~ 23 0 1 ~ ~ 0 2 Byte (2) LSB 104 Byte Data In DDC No. of DATA (1) Set Page and Column Address. Set Page Address : 1 0 1 1 P3 P2 P1 P0 Set Column Address MSB : 0 0 0 1 0 Y6 Y5 Y4 Set Column Address LSB : 0 0 0 0 Y3 Y2 Y1 Y0 (2) Set DDC(Data Direction Command) and No. of Data Bytes. Set Data Direction Command( For SPI mode Only): 1 0 0 0 0 0 0 0 Set No. of Data Bytes(DDL) : D7 D6 D5 D4 D3D2D1D0 Figure 4. 3 Pin SPI Timing (RS is not used) This command is used in 3-Pin SPI mode only. It will be two continuous commands, the first byte controls the data direction and informs the LCD driver the second byte will be number of data bytes will be write. After these two commands sending out, the following messages will be data. If data is stopped in transmitting, it is not valid data. New data will be transferred serially with most significant bit first. *NOTES: - In spite of transmission of data, if CS1B will be disable, state terminates abnormally. Next state is initialized. - The number of writing display data = DDL register value + 1 Busy Flag The busy flag indicates whether the S6B1400X is operating or not. When DB7 is “H” in read status operation, this device is in busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the MPU performance. 16 S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD Data Transfer The S6B1400X uses bus holder and internal data bus for data transfer with the MPU. When writing data from the MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in figure 5. And when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure 6. This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. Therefore, the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data. MPU signals RS RW_WRB DB0 to DB7 N D(N) D(N+1) D(N+2) D(N+3) N D(N) D(N+1) D(N+2) D(N+3) Internal signals RW_WRB BUS HOLDER COLUMN ADDRESS N N+1 N+2 N+3 Figure 5. Write Timing MPU signals RS RW_WRB E_RDB DB0 to DB7 N Dummy D(N+1) D(N) D(N+2) Internal signals RW_WRB E_RDB BUS HOLDER COLUMN ADDRESS N D(N) N N+1 D(N+1) D(N+2) N+2 N+3 Figure 6. Read Timing 17 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X DISPLAY DATA RAM (DDRAM) The Display Data RAM stores pixel data for the LCD. It is 65-row by 104-column addressable array. Each pixel can be selected when the page and column addresses are specified. The 65 rows are divided into 8 pages of 8 lines and the 9th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page directly through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD common lines as shown in figure 7. The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD controller operates independently, data can be written into RAM at the same time as data is being displayed without causing the LCD flicker. DB0 0 0 1 -- 0 COM0 -- DB1 1 0 0 -- 1 COM1 -- DB2 0 1 1 -- 0 COM2 -- DB3 1 0 1 -- 0 COM3 -- DB4 0 0 0 -- 1 COM4 -- Display Data RAM LCD Display Figure 7. RAM-to-LCD Data Transfer Page Address Circuit This circuit is for providing a page address to Display Data RAM shown in figure 9. It incorporates 4-bit page address register changed by only the “Set Page” instruction. Page Address 8 (DB3 is “H”, but DB2, DB1 and DB0 are “L”) is a special RAM area for the icons and display data DB0 is only valid. When Page Address is above 8, it is impossible to access to on-chip RAM. Line Address Circuit This circuit assigns DDRAM a line address corresponding to the first line (COM0) of the display. Therefore, by setting line address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip RAM as shown in figure 9. It incorporates 6-bit line address register changed by only the Initial Display Line instruction and 6-bit counter circuit. At the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by CL signal and generates the line address for transferring the 104-bit RAM data to the display data latch circuit. However, display data of icons are not scrolled because the MPU cannot access line address of icons. 18 S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD Column Address Circuit Column address circuit has a 7-bit preset counter that provides column address to the Display Data RAM as shown in figure 9. When Set Column Address MSB / LSB instruction is issued, 7-bit [Y6:Y0] is updated. And, since this address is increased by 1 each a Read or Write data instruction, microprocessor can access the display data continuously. However, the counter is not increas ed and locked if a non-existing address above 67H. It is unlocked if a column address is set again by set Column Address MSB/LSB instruction. And the column address counter is independent of page address register. ADC Select instruction makes it possible to invert the relationship between the column address and the segment outputs. It is necessary to rewrite the display data on built-in RAM after issuing ADC Select instruction. Refer to the following figure 8. SEG output SEG 0 SEG 1 SEG 2 SEG 3 ... ... SEG 100 SEG 101 SEG 102 SEG 103 Column address [Y7:Y0] 00H 01H 02H 03H ... ... 64H 65H 66H 67H Display data 1 0 1 0 1 1 0 0 LCD panel display ( ADC = 0 ) LCD panel display ( ADC = 1 ) ... ... ... ... Figure 8. The Relationship between the Column Address and the Segment Outputs Segment Control Circuit This circuit controls the display data by the display ON / OFF, reverse display ON / OFF and entire display ON / OFF instructions without changing the data in the display data RAM. 19 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD DB0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 0 0 0 1 Column Address Data DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 ADC=0 ADC=1 Page1 Page2 Page3 Page4 Page5 Page6 Page7 Page8 00 01 - 02 03 04 05 67 66 65 64 63 62 --------- SEG103 SEG102 SEG101 SEG99 SEG100 ----- 62 63 64 65 66 67 05 04 03 02 01 00 SEG98 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 LCD Output Page0 Figure 9. Display Data RAM Map 20 S6B1400X Line Address COM Output 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COMS Start 1/33 Duty DB1 1/55 Duty DB2 1/49 Duty Page Address DB3 SPEC. VER. 0.0 When the initial display line address is 1C[HEX] S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD LCD DISPLAY CIRCUITS Oscillator This is completely on-chip oscillator and its frequency is nearly independent of VDD. This oscillator signal is used in display timing generation circuit. Display Timing Generator Circuit This circuit generates some signals to be used for displaying LCD. The display clock, CL generated by oscillation clock, generates a clock to the line counter and a latch signal to the display data latch. The line address of on-chip RAM is generated in synchronization with the display clock (CL) and the 104-bit display data is latched by the display data latch circuit in synchronization with the display clock. The display data which is read to the LCD driver is completely independent of the access to the display data RAM from the microprocessor. The LCD AC signal, FR is generated from the display clock. 2-frame AC driver waveforms with internal timing signal are shown in figure 10. 64 65 1 2 3 4 5 6 7 8 9 10 11 12 58 59 60 61 62 63 64 65 1 2 3 4 5 6 CL FR COM0 VLCD V1 V2 V3 V4 VSS COM1 VLCD V1 V2 V3 V4 VSS SEGn VLCD V1 V2 V3 V4 VSS Figure 10. 2-frame AC Driving Waveform (Duty Ratio = 1/65) 21 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X Common Output Control Circuit This circuit controls the relationship between the number of common output and specified duty ratio. SHL Select Instruction specifies the scanning direction of the common output pins. Table 12. The Relationship between Duty Ratio and Common Output Common output pins Duty 1/33 1/49 1/55 1/65 SHL 0 1 0 1 0 1 0 1 COM [0:15] COM [16:23] COM[0:15] COM[31:16] COM[0:23] COM[47:24] COM[0:26] COM[53:27] COM [24:26] COM [27:36] *NC *NC *NC *NC *NC *NC COM[0:63] COM[63:0] COM [37:39] COM [40:47] COM [48:63] COM[16:31] COM[15:0] COM[24:47] COM[23:0] COM[27:53] COM[26:0] COMS COMS COMS COMS COMS *NC: No Connection 22 S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD LCD DRIVER CIRCUITS This driver circuit is configured by 66-channel (including 2 COMS channels) common driver and 104-channel segment driver. This LCD panel driver voltage depends on the combination of display data and FR signal. V DD COM0 FR COM1 V SS COM2 VLCD V1 V2 COM3 COM0 COM4 V3 V4 V SS VLCD V1 V2 COM5 COM6 COM1 COM7 V3 V4 V SS VLCD V1 V2 COM8 COM2 COM9 V3 V4 V SS VLCD V1 V2 COM10 COM11 SEG0 COM12 V3 V4 V SS VLCD V1 V2 COM13 COM14 SEG1 COM15 S E G 0 S E G 1 S E G 2 S E G 3 S E G 4 V3 V4 V SS VLCD V1 V2 SEG2 V3 V4 V SS Figure 11. Segment and Common Timing 23 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X POWER SUPPLY CIRCUITS The power supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low-power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. They are controlled by power control instruction. For details, refers to “Instruction Description”. Voltage Converter Circuits These circuits boost up the electric potential between VCI and VSS to 3 or 4 times toward positive side. VDD VDD VCI VCI VOUT = 4 × VCI VCI VCI VOUT = 3 × VCI VDD DCDC4B DCDC4B V SS VCI VCI VSS V SS Figure 12. Three Times Boosting Circuit Figure 13. Four Times Boosting Circuit * The VCI voltage range must be set so that the VOUT (Voltage converter output) does not exceed the absolute maximum rating value 24 S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD Voltage Regulator Circuits The function of the internal voltage regulator circuits is to determine liquid crystal operating voltage, VLCD, by adjusting resistors, Ra and Rb, within the range of |V LCD| < |VOUT|. Because VOUT is the operating voltage of operational-amplifier circuits shown in figure 14, it is necessary to be applied internally. For the Eq. 1, we determine VLCD by Ra, Rb and VEV . The Ra and Rb are connected internally or externally by INTRS pin. And V EV called the voltage of electronic volume is determined by Eq. 2, where the parameter α is the value selected by instruction, "Set Reference Voltage Register", within the range 0 to 63. VREF voltage at Ta = 25°C is shown in table 13. Rb VLCD = ( 1 + ) x VEV [V] ------ (Eq. 1) Ra (63 - α) VEV = ( 1 - ) x VREF [V] ------ (Eq. 2) 162 Table 13. VREF Voltage at Ta = 25 °C REF Temp. coefficient VREF [V] H -0.05% / °C 2.1 L External input VEXT Table 14. Electronic Contrast Control Register (64 Steps) SV5 SV4 SV3 SV2 SV1 SV0 Reference voltage parameter (α) VLCD Contrast 0 0 0 0 0 0 0 Minimum Low 0 0 0 0 0 1 1 : : : : : : : : : : : : : : : : : : 1 0 0 0 0 0 32 (default) : : : : : : : : : : : : : : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63 Maximum High 25 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 VOUT REF VEXT + VLCD V REF Rb V EV VR INTRS Ra V SS Inside chip GND Figure 14. Internal Voltage Regulator Circuit 26 S6B1400X S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD In Case of Using Internal Resistors, Ra and Rb (INTRS = "H") When INTRS pin is “H”, resistor Ra is connected internally between VR pin and VSS, and Rb is connected between VLCD and VR. We determine VLCD by two instructions, "Regulator Resistor Select" and "Set Reference Voltage". Table 15. Internal Rb / Ra ratio depending on 3-bit data (R2 R1 R0) 3-bit data settings (R2 R1 R0) 1 + (Rb / Ra) 000 001 010 011 100 101 110 111 3.0 3.5 4.0 4.5 5.0 5.5 Not available Not available The following figure shows VLCD voltage measured by adjusting internal regulator resistor ratio (Rb / Ra) and 6-bit electronic volume registers for each temperature coefficient at Ta = 25 °C. 14.00 12.00 (1 0 1) (1 0 0) (0 1 1) (0 1 0) (0 0 1) (0 0 0) 10.00 V0 [V] 8.00 6.00 4.00 2.00 0.00 0 8 16 24 32 40 48 56 Electronic volume level Figure 15. Electronic Volume Level 27 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X In Case of Using External Resistors, Ra and Rb (INTRS = "L") When INTRS pin is “L”, it is necessary to connect external regulator resistor Ra between VR and VSS, and Rb between VLCD and VR. Example: For the following requirements 1. LCD driver voltage, VLCD = 6V 2. 6-bit reference voltage register = (1, 0, 0, 0, 0, 0) 3. Maximum current flowing Ra, Rb = 1 uA From Eq. 1 Rb 6 = ( 1 + ) x VEV [V] ------ (Eq. 3) Ra From Eq. 2 (63 - 32) VEV = ( 1 - ) x 2.1 ≅ 1.698 [V] ------ (Eq. 4) 162 From requirement 3. 6 = 1 [uA] ------ (Eq. 5) Ra + Rb From equations Eq. 3, 4 and 5 Ra ≅ 1.698 [MΩ] Rb ≅ 4.302 [MΩ] The following table shows the range of VLCD depending on the above requirements. Table 16. VLCD Depending on Electronic Volume Level Electronic volume level VLCD 28 0 ....... 32 ....... 63 4.53 ....... 6.00 ....... 7.42 S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD Voltage Follower Circuits VLCD voltage is resistively divided into four voltage levels (V1, V2, V3, V4), and those output impedance are converted by the voltage follower for increasing drive capability. The following table shows the relationship between V1 to V4 level and each duty ratio. Table 17. The Relationship between V1 to V4 Level and Duty Ratio Duty ratio DUTY1 DUTY0 1/33 L L 1/49 L H 1/55 H L 1/65 H H LCD bias V1 V2 V3 V4 1/5 (4/5) VLCD (3/5) VLCD (2/5) VLCD (1/5) VLCD 1/6 (5/6) VLCD (4/6) VLCD (2/6) VLCD (1/6) VLCD 1/6 (5/6) VLCD (4/6) VLCD (2/6) VLCD (1/6) VLCD 1/8 (7/8) VLCD (6/8) VLCD (2/8) VLCD (1/8) VLCD 1/6 (5/6) VLCD (4/6) VLCD (2/6) VLCD (1/6) VLCD 1/8 (7/8) VLCD (6/8) VLCD (2/8) VLCD (1/8) VLCD 1/7 (6/7) VLCD (5/7) VLCD (2/7) VLCD (1/7) VLCD 1/9 (8/9) VLCD (7/9) VLCD (2/9) VLCD (1/9) VLCD High Power Mode The power supply circuit equipped in the S6B1400X for LCD drive has very low power consumption (in normal mode: HPMB = “H”). If use for LCD panels with large loads, this low-power power supply may cause display quality to degrade. When this occurs, setting the HPMB pin to “L”(high power mode) can improve the quality of the display. 29 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X RESET CIRCUIT Setting RESETB to “L” or Reset instruction can initialize internal function. When RESETB becomes “L”, the initialized driver has following states. Display ON / OFF: OFF Entire display ON / OFF: OFF (normal) ADC select: OFF (normal) Reverse display ON / OFF: OFF (normal) Power control register (VC, VR, VF) = (0, 0, 0) Serial interface internal register data clear LCD bias ratio: 1/9 (1/65 duty), 1/8 (1/55 duty), 1/8 (1/49 duty), 1/6 (1/33 duty) On-chip oscillator OFF Power save release Read-modify-write: OFF SHL select: OFF (normal) Static indicator mode: OFF Static indicator register: (S1, S0) = (0, 0) Display start line: 0 (first) Column address: 0 Page address: 0 Regulator resistor select register: (R2, R1, R0) = (0, 1, 1) Reference voltage set: OFF Reference voltage control register: (SV5, SV4, SV3, SV2, SV1, SV0) = (1, 0, 0, 0, 0, 0) Test mode release When RESET instruction is issued, the initialized driver has following states. Read-modify-write: OFF Static indicator mode: OFF Static indicator register: (S1, S0) = (0, 0) SHL select: 0 Display start line: 0 (first) Column address: 0 Page address: 0 Regulator resistor select register: (R2, R1, R0) = (0, 1, 1) Reference voltage set: OFF Reference voltage control register: (SV5, SV4, SV3, SV2, SV1, SV0) = (1, 0, 0, 0, 0, 0) Test mode release While RESETB is “L” or Reset instruction is executed, no instruction except read status could be accepted. Reset status appears at DB4. After DB4 becomes ”L”, any instruction can be accepted. RESETB must be connected to the reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESETB is essential before used. 30 S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD INSTRUCTION DESCRIPTION Table 18. Instruction Table × : Don’t care Instruction RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description Display ON / OFF 0 0 1 0 1 0 1 1 1 DON Turn ON / OFF LCD panel When DON = 0: display OFF When DON = 1: display ON Initial display line 0 0 0 1 ST5 ST4 ST3 ST2 ST1 ST0 Specify DDRAM line for COM0 Set page address 0 0 1 0 1 1 P3 P2 P1 P0 Set page address Set column address MSB 0 0 0 0 0 1 × Y6 Y5 Y4 Set column address MSB Set column address LSB 0 0 0 0 0 0 Y3 Y2 Y1 Y0 Set column address LSB Read status 0 1 BUSY ADC ON/OFF RESETB 0 0 0 0 Read the internal status Write display data 1 0 Write data Write data into DDRAM Read display data 1 1 Read data Read data from DDRAM ADC select 0 0 1 0 1 0 0 0 0 ADC Reverse display ON / OFF 0 0 1 0 1 0 0 1 1 REV Entire display ON / OFF 0 0 1 0 1 0 0 1 0 EON LCD bias select 0 0 1 0 1 0 0 0 1 BIAS Select SEG output direction When ADC = 0: normal direction (SEG0→SEG103) When ADC = 1: reverse direction (SEG103→SEG0) Select normal / reverse display When REV = 0: normal display When REV = 1: reverse display Select normal/ entire display ON When EON = 0: normal display. When EON = 1: entire display ON Select LCD bias Set modify-read 0 0 1 1 1 0 0 0 0 0 Set modify-read mode Reset modify-read 0 0 1 1 1 0 1 1 1 0 Release modify-read mode Reset 0 0 1 1 1 0 0 0 1 0 Initialize the internal functions SHL select 0 0 1 1 0 0 SHL × × × Select COM output direction When SHL = 0: normal direction (COM0→COM63) When SHL = 1: reverse direction (COM63→COM0) Power control 0 0 0 0 1 0 1 VC VR VF Control power circuit operation Regulator resistor select 0 0 0 0 1 0 0 R2 R1 R0 Select internal resistance ratio of the regulator resistor Set reference voltage mode 0 0 1 0 0 0 0 0 0 1 Set reference voltage mode Set reference voltage register 0 0 × × SV5 SV4 SV3 SV2 SV1 SV0 Set reference voltage register Set static indicator mode 0 0 1 0 1 0 1 1 0 SM Set static indicator mode Set static indicator register 0 0 × × × × × × S1 S0 Set static indicator register Set Data Direction & Display Data Length (DDL) x x 1 0 0 0 0 0 0 0 x x D7 D6 D5 D4 D3 D2 D1 D0 2-byte Instruction to specify the number of data bytes (SPI Mode) Power save - - - - - - - - - - Compound Instruction of display OFF and entire display ON 31 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X Table 18. Instruction Table (Continued) × : Don’t care 32 Instruction RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description NOP 0 0 1 1 1 0 0 0 1 1 Non-Operation command Test instruction_1 0 0 1 1 1 1 × × × × Don’t use this instruction Test instruction_2 0 0 1 0 0 1 × × × × Don’t use this instruction S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD DISPLAY ON / OFF Turns the display ON or OFF RS RW 0 0 DON = 1: display ON DON = 0: display OFF DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 1 0 1 1 1 DON INITIAL DISPLAY LINE Sets the line address of display RAM to determine the initial display line. The RAM display data is displayed at the top row (COM0 when SHL = L, COM63 when SHL = H) of LCD panel. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 ST5 ST4 ST3 ST2 ST1 ST0 ST5 ST4 ST3 ST2 ST1 ST0 Line address 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63 SET PAGE ADDRESS Sets the page address of display data RAM from the microprocessor into the page address register. Any RAM data bit can be accessed when its page address and column address are specified. Along with the column address, the page address defines the address of the display RAM to write or read display data. Changing the page address doesn't effect to the display status. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 1 P3 P2 P1 P0 P3 P2 P1 P0 Page 0 0 0 0 0 0 0 0 1 1 : : : : : 0 1 1 1 7 1 0 0 0 8 33 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X SET COLUMN ADDRESS Sets the column address of display RAM from the microprocessor into the column address register. Along with the column address, the column address defines the address of the display RAM to write or read display data. When the microprocessor reads or writes display data to or from display RAM, column addresses are automatically increased. Set Column Address MSB RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 x Y6 Y5 Y4 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Y2 Y1 Y0 Set Column Address LSB RS RW DB7 0 0 0 0 0 0 Y3 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Column address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : 1 1 0 0 1 1 0 102 1 1 0 0 1 1 1 103 READ STATUS Indicates the internal status of the S6B1400X RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 BUSY ADC ON / OFF RESETB 0 0 0 0 Flag BUSY ADC 34 Description The device is busy when internal operation or reset. Any instruction is rejected until BUSY goes Low. 0: chip is active, 1: chip is being busy Indicates the relationship between RAM column address and segment driver. 0: reverse direction (SEG103 → SEG0), 1: normal direction (SEG0 → SEG103) ON / OFF Indicates display ON / OFF status. 0: display ON, 1: display OFF RESETB Indicates the initialization is in progress by RESETB signal. 0: chip is active, 1: chip is being reset S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD WRITE DISPLAY DATA 8-bit data of display data from the microprocessor can be written to the RAM location specified by the column address and page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data to the addressed page. RS RW 1 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Write data Set Page Address Set Page Address Set Column Address Set Column Address Data write Dummy Data Read Column = Column + 1 Column = Column + 1 Data Write Continue ? Data Read YES Column = Column + 1 NO Optional Status Data Read Continue ? YES NO Optional Status Figure 16. Sequence for Writing Display Data Figure 17. Sequence for Reading Display Data Read Display Data 8-bit data from display data RAM specified by the column address and page address can be read by this instruction. As the column address is increased by 1 automatically after each this instruction, the microprocessor can continuously read data from the addressed page. A dummy read is required after loading an address into the column address register. Display data cannot be read through the serial interface. RS RW 1 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Read data ADC SELECT (SEGMENT DRIVER DIRECTION SELECT) Changes the relationship between RAM column address and segment driver. The direction of segment driver output pins can be reversed by software. This makes IC layout flexible in LCD module assembly. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 0 0 ADC ADC = 0: normal direction (SEG0 → SEG103) ADC = 1: reverse direction (SEG103 → SEG0) 35 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X REVERSE DISPLAY ON / OFF Reverses the display status on LCD panel without rewriting the contents of the display data RAM. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 1 1 REV REV RAM bit data = “1” RAM bit data = “0” 0 (normal) LCD pixel is illuminated LCD pixel is not illuminated 1 (reverse) LCD pixel is not illuminated LCD pixel is illuminated ENTIRE DISPLAY ON / OFF Forces the whole LCD points to be turned on regardless of the contents of the display data RAM. At this time, the contents of the display data RAM are held. This instruction has priority over the Reverse Display On/Off instruction. RS RW DB7 0 0 1 EON = 0: normal display EON = 1: entire display ON DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 0 0 1 0 EON SELECT LCD BIAS Selects LCD bias ratio of the voltage required for driving the LCD. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 0 1 Bias Duty ratio DUTY1 DUTY0 1/33 0 1/49 LCD bias Bias = 0 Bias = 1 0 1/6 1/5 0 1 1/8 1/6 1/55 1 0 1/8 1/6 1/65 1 1 1/9 1/7 SET MODIFY-READ This instruction stops the automatic increment of the column address by the read display data instruction, but the column address is still increased by the write display data instruction. And it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. This mode is canceled by the reset Modify-read instruction. 36 RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 0 0 0 0 S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD RESET MODIFY-READ This instruction cancels the Modify-read mode, and makes the column address return to its initial value just before the set Modify-read instruction is started. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 1 1 1 0 Set Page Address Set Column Address (N) Set Modify-Read Dummy Read Data Read Data Process Data Write NO Change Complete ? YES Reset Modify-Read Return Column Address (N) Figure 18. Sequence for Cursor Display RESET This instruction resets initial display line, column address, page address, and common output status select to their initial status, but does not affect the contents of display data RAM. This instruction cannot initialize the LCD power supply, which is initialized by the RESETB pin. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 0 0 1 0 37 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X SHL SELECT (COMMON OUTPUT MODE SELECT) COM output scanning direction is selected by this instruction which determines the LCD driver output status. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 0 0 SHL × × × × : Don’t care SHL = 0: normal direction (COM0 → COM63) SHL = 1: reverse direction (COM63 → COM0) POWER CONTROL Selects one of eight power circuit functions by using 3-bit register. An external power supply and part of internal power supply functions can be used simultaneously. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 1 VC VR VF VC VR VF Status of internal power supply circuits 0 1 Internal voltage converter circuit is OFF Internal voltage converter circuit is ON 0 1 Internal voltage regulator circuit is OFF Internal voltage regulator circuit is ON 0 1 Internal voltage follower circuit is OFF Internal voltage follower circuit is ON REGULATOR RESISTOR SELECT Selects resistance ratio of the internal resistor used in the internal voltage regulator. See voltage regulator section in power supply circuit. Refer to the Table 15. 38 RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 0 R2 R1 R0 R2 R1 R0 (1 + Rb / Ra) ratio 0 0 0 3.0 0 0 1 3.5 0 1 0 4.0 0 1 1 4.5 (default) 1 0 0 5.0 1 0 1 5.5 1 1 0 Not available 1 1 1 Not available S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD REFERENCE VOLTAGE SELECT st nd Consists of 2-byte instruction. The 1 instruction sets reference voltage mode, the 2 one updates the contents of reference voltage register. After second instruction, reference voltage mode is released. st The 1 Instruction: Set Reference Voltage Select Mode RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 0 0 0 0 0 1 nd The 2 Instruction: Set Reference Voltage Register RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 × × SV5 SV4 SV3 SV2 SV1 SV0 SV5 SV4 SV3 SV2 SV1 SV0 Reference voltage parameter (α) VLCD Contrast 0 0 0 0 0 0 0 Minimum Low 0 0 0 0 0 1 1 : : : : : : : : : : : : : : : : : : 1 0 0 0 0 0 : : : : : : : : : : : : : : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63 Maximum High 32 (default) Setting Reference Voltage Start 1st Instruction for Mode Setting nd 2 Instruction for Register Setting Setting Reference Voltage End Figure 19. Sequence for Setting the Reference Voltage 39 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X SET STATIC INDICATOR STATE Consists of two bytes instruction. The first byte instruction (Set Static Indicator Mode) enables the second byte instruction (Set Static Indicator Register) to be valid. The first byte sets the static indicator on/off. When it is on, the second byte updates the contents of static indicator register without issuing any other instruction and this static indicator state is released after setting the data of indicator register. st The 1 Instruction: Set Static Indicator Mode (ON / OFF) RS RW DB7 0 0 1 SM = 0: static indicator OFF SM = 1: static indicator ON nd The 2 40 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 0 1 1 0 SM Instruction: Set Static Indicator Register RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 × × × × × × S1 S0 S1 S0 Status of static indicator output 0 0 OFF 0 1 ON (about 1 second blinking) 1 0 ON (about 0.5 second blinking) 1 1 ON (always ON) S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SET DATA DIRECTION & DISPLAY DATA LENGTH (3-PIN SPI MODE) Consists of two bytes instruction. This command is used in 3-Pin SPI mode only (PS = ”L” and C68 = ”L”). It will be two continuous commands, the first byte control the data direction (write mode only) and inform the LCD driver the second byte will be number of data bytes will be write. When RS is not used, the Display Data Length instruction is used to indicate that a specified number of display data bytes are to be transmitted. The next byte after the display data string is handled as command data. st The 1 Instruction: Set Data Direction (Only Write Mode) RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 x x 1 0 0 0 0 0 0 0 nd The 2 Instruction: Set Display Data Length (DDL) Register RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 x x D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Display Data Length 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 2 0 0 0 0 0 0 1 0 3 : : : : : : : : : 1 1 1 1 1 1 0 1 254 1 1 1 1 1 1 1 0 255 1 1 1 1 1 1 1 1 256 NOP Non-Operation Instruction RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 0 0 1 1 TEST INSTRUCTION (TEST INSTRUCTION_1 & TEST INSTRUCTION_2) These are the instruction for IC chip testing. Please do not use it. If the test instruction is used by accident, it can be cleared by applying “0” signal to the RESETB input pin or the reset instruction. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 1 × × × × 0 0 1 0 0 1 × × × × 41 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X POWER SAVE (COMPOUND INSRTUCTION) If the entire display ON / OFF instruction is issued during the display OFF state, S6B1400X enters the power save status to reduce the power consumption to the static power consumption value. According to the status of static indicator mode, power save is entered to one mode of sleep and standby mode. When Static Indicator mode is ON, standby mode is issued. When OFF, sleep mode is issued. Power save mode is released by the entire display OFF instruction. Static Indicator OFF Static Indicator ON Power Save (Compound Instruction) [Display OFF] [Entire Display ON] Sleep Mode [Oscillator Circuit: OFF] [LCD Power Supply Circuit: OFF] [All COM / SEG Outputs: VSS] [Consumption Current: <2uA] Standby Mode [Oscillator Circuit: ON] [LCD Power Supply Circuit: OFF] [All COM / SEG Outputs: VSS] [Consumption Current: <10uA] Power Save OFF (Compound Instruction) [Entire Display OFF] [Static Indicator ON] 2 Bytes Command Power Save OFF [Entire Display OFF] Release Sleep Mode Release Standby Mode Figure 20. Power Save (Compound Instruction) − Sleep Mode This stops all operations in the LCD display system, and as long as there are no access from the MPU, the consumption current is reduced to a value near the static current. The internal modes during sleep mode are as follows: a. The oscillator circuit and the LCD power supply circuit are halted. b. All liquid crystal drive circuits are halted, and the segment and common outputs go to the VSS level. − Standby Mode The duty LCD display system operations are halted and only the static drive system for the indicator continues to operate, providing the minimum required consumption current for the static drive. The internal modes are in the following states during standby mode. a. The LCD power supply circuits are halted. The oscillator circuit continues to operate. b. The duty drive system liquid crystal drive circuits are halted and the segment and common outputs go to the VSS level. The static drive system does not operate. When a reset command is performed while in standby mode, the system enters sleep mode. 42 S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD REFERENTIAL INSTRUCTION SETUP FLOW (1) User System Setup by External Pins Start of Initialization Power ON (V DD - VSS) Keeping the RESETB Pin = “L” Waiting for Stabilizing the Power RESETB Pin = “H” User Application Setup by Internal Instructions [ADC Select] [SHL Select] [LCD Bias Select] User LCD Power Setup by Internal Instructions [Voltage Converter ON] Waiting for ≥ 25ms User LCD Power Setup by Internal Instructions [Voltage Regulator ON] Waiting for ≥ 1ms User LCD Power Setup by Internal Instructions [Voltage Follower ON] User LCD Power Setup by Internal Instructions [Regulator Resistor Select] [Reference Voltage Register Set] Waiting for Stabilizing the LCD Power Levels End of Initialization Figure 21. Initializing with the Built-in Power Supply Circuits 43 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD REFERENTIAL INSTRUCTION SETUP FLOW (2) End of Initialization Display Data RAM Addressing by Instruction [Initial Display Line] [Set Page Address] [Set Column Address] Write Initial Display Data Turn Display ON by Instruction [Display ON / OFF: DON = 1 ] End of Data Display Figure 22. Data Displaying 44 SPEC. VER. 0.0 S6B1400X S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD REFERENTIAL INSTRUCTION SETUP FLOW (3) Optional Status Turn Display OFF by Instruction [Display OFF] Turn Off the Voltage Regulator by Internal Instructions [Voltage Regulator OFF] Waiting for ≥ 50ms Turn Off the Voltage Follower by Internal Instructions [Voltage Follower OFF] Waiting for ≥ 1ms Turn Off the Voltage Converter by Internal Instructions [Voltage Converter OFF] Waiting for ≥ 1ms Power OFF (VDD - VSS) Figure 23. Power OFF 45 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Table 19. Absolute Maximum Ratings Parameter Symbol Rating Unit VDD - 0.3 to +7.0 V VLCD - 0.3 to +13.0 V Input voltage range VIN - 0.3 to VDD + 0.3 V Operating temperature range TOPR - 40 to +85 °C Storage temperature range TSTR - 55 to +125 °C Supply voltage range Notes: 1. VDD and VLCD are based on VSS = 0V. 2. Voltages VLCD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS must always be satisfied. 3. If supply voltage exceeds its absolute maximum range, this LSI may be damaged permanently. It is desirable to use this LSI under electrical characteristic conditions during general operation. Otherwise, this LSI may malfunction or reduced LSI reliability may result. 46 S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD DC CHARACTERISTICS Table 20. DC Characteristics (V SS = 0V, VDD = 2.4 to 3.6V, Ta = -40 to 85°C) Item Symbol Operating voltage (1) LCD power voltage (2) Min. Typ. Max. Unit Pin used VDD 2.4 - 3.6 V VDD *1 VLCD 4.5 - 9.0 V VLCD *2 High VIH 0.8V DD - VDD V *3 Low VIL VSS - 0.2V DD High VOH IOH = -0.5mA 0.8V DD - VDD V *4 Low VOL IOL = 0.5mA VSS - 0.2V DD Input leakage current IIL VIN = VDD or VSS - 1.0 - + 1.0 µA *5 Output leakage current IOZ VIN = VDD or VSS - 3.0 - + 3.0 µA *6 LCD driver ON resistance RON Ta=25°C, VLCD = 8V - 2.0 3.0 kΩ SEGn COMn *7 fOSC Ta = 25°C Duty ratio = 1/65 32.7 43.6 54.5 4.09 5.45 6.81 KHz CL *8 ×3 2.4 - 3.6 ×4 2.4 - 3.0 V VCI 2.04 2.1 2.16 V *9 Input voltage Output voltage Oscillator frequency Internal fCL Voltage converter Input voltage VCI Reference voltage VREF Condition Ta = 25°C - 0.05%/°C 47 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X Dynamic Current Consumption when the Built-in Power Circuit is ON (At Operate Mode) (Ta = 25°C) Item Dynamic current consumption (2) Symbol IDD2 Condition Min. Typ. Max. Unit Pin used VDD = 3.0V, (VCI = VDD, 3 times boosting) VLCD – VSS = 7.64V, 1/65 duty ratio, Display pattern OFF, Normal power mode - 120 - µΑ *11 VDD = 3.0V, (VCI = VDD, 3 times boosting) VLCD – VSS = 7.64V, 1/65 duty ratio, Display pattern checker, Normal power mode - 140 - µΑ *11 VDD = 3.0V, (VCI = VDD, 4 times boosting) VLCD – VSS = 8.40V, 1/65 duty ratio, Display pattern OFF, Normal power mode - 180 - µΑ *11 VDD = 3.0V, (VCI = VDD, 4 times boosting) VLCD – VSS = 8.40V, 1/65 duty ratio, Display pattern checker, Normal power mode - 200 - µΑ *11 Current Consumption during Power Save Mode (Ta = 25°C) Item Sleep mode current Standby mode current 48 Symbol Condition Min. Typ. Max. Unit IDDS1 During sleep - - 2 µA IDDS2 During standby - - 10 µA Pin used S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD Table 21. The Relationship between Oscillation Frequency and Frame Frequency Duty ratio Item 1/65 On-chip oscillator circuit is used 1/55 1/49 1/33 On-chip oscillator circuit is used On-chip oscillator circuit is used On-chip oscillator circuit is used fCL fFR Frame Frequecncy fOSC fOSC fFR × 2 fFR × 2 -- fFR × 2 8 fOSC 9 fOSC 10 fOSC 2 × 8 × 65 fOSC 2 × 9 × 55 fOSC 2 × 10 × 49 fOSC fFR × 2 15 2 × 15 × 33 (fOSC: oscillation frequency, fCL: display clock frequency, fFR: LCD AC signal frequency) [* Remark Solves] *1. Though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from the MPU. *2. In case of external power supply is applied. *3. CS1B, CS2, RS, DB0 to DB7, E_RDB, RW_WRB, RESETB, C68, PS, INTRS, HPMB pins. *4. DB0 to DB7, FR, FRS, CL pins. *5. CS1B, CS2, RS, DB[7:0], E_RDB, RW_WRB, RESETB, C68, PS, INTRS, HPMB pins. *6. Applies when the DB[7:0], FR, FRS and CL pins are in high impedance. *7. Resistance value when ± 0.1[mA] is applied during the ON status of the output pin SEGn or COMn. RON = ∆V / 0.1 [kΩ] (∆V: voltage change when ± 0.1[mA] is applied in the ON status.) *8. See table 21 for the relationship between oscillation frequency and frame frequency. *9. On-chip reference voltage source of the voltage regulator circuit to adjust VLCD. *10,11. Applies to the case where the on-chip oscillation circuit is used and no access is made from the MPU. The current consumption, when the built-in power supply circuit is ON or OFF. The current flowing through voltage regulation resistors (Ra and Rb) is not included. It does not include the current of the LCD panel capacity, wiring capacity, etc. 49 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X AC CHARACTERISTICS Read / Write Characteristics (8080-series MPU) RS tAS80 tAH80 CS1B (CS2) tCY80 tPW L80(R), E_RDB, RW_WRB 0.9V DD tPWL80(W) tPWH80(R), 0.1V DD tDS80 tPWH80(W) tDH80 DB0 to DB7 (Write) tACC80 tOD80 DB0 to DB7 (Read) ** tPWL80(W) and tPWL80(R) is specified in the overlapped period when CS1B is low (CS2 is high) and RW_WRB(E_RDB) is low. Figure 24. Read / Write Characteristics (8080-series MPU) Item Address setup time Address hold time System cycle time Signal RS RS Pulse width (WRB) RW_WRB Pulse width (RDB) E_RDB Data setup time Data hold time Read access time Output disable time DB7 to DB0 Symbol Min. tAS80 tAH80 tCY80 0 0 300 60 60 60 60 40 15 10 tPWL80 (W) tPWH80 (W) tPWL80 (R) tPWH80 (R) tDS80 tDH80 tACC80 tOD80 Typ. (V DD = 2.4 to 3.6V, Ta = -40 to +85°C) Max. Unit Remark - - ns - - ns - - ns - - ns - - ns - 140 100 ns CL = 100 pF Note: 1. The input signal rising time and falling time (tr,tf) is specified at 15ns or less. (tr + tf) < (tCY80 - tPWL80 (W) - tPWH80 (W) ) for write, (tr + tf) < (tCY80 - tPWL80 (R) - tPWH80 (R) ) for read 50 S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD Read / Write Characteristics (6800-series Microprocessor) RS, RW_WRB tAS68 tAH68 CS1B (CS2) tCY68 tPW H68(R), tPW H68(W) tPW L68(R), tPW L68(W) E_RDB 0.1V DD 0.9V DD tDS68 tDH68 DB0 to DB7 (Write) tACC68 tOD68 DB0 to DB7 (Read) ** tPWH68(W) and tPWH68(R) is specified in the overlapped period when CS1B is low (CS2 is high) and E_RDB is high. Figure 25. Read / Write Characteristics (6800-series Microprocessor) (V DD = 2.4 to 3.6V, Ta = -40 to +85°C) Max. Unit Remark Item Signal Symbol Min. Typ. Address setup time Address hold time RS RW_WRB tAS68 tAH68 0 0 - - ns System cycle time RS tCY68 300 - - ns Data setup time Data hold time Access time Output disable time DB7 to DB0 tDS68 tDH68 40 15 10 120 120 60 60 - - ns - 140 100 ns - - ns Enable pulse width Read E_RDB Write tACC68 tOD68 tPWH68(R) tPWL68(R) tPWH68(W) tPWL68(W) CL = 100 pF Note: 1. The input signal rising time and falling time (tr,tf) is specified at 15ns or less. (tr + tf) < (tCY68 – tPWH68 (W) – tPWH68 (W) ) for write, (tr + tf) < (tCY80 – tPWH68 (R) – tPWL68 (R) ) for read 51 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X Serial Interface Characteristics tCSS CS1B (CS2) tCHS tASS RS tAHS tCYS 0.9V DD DB6 (SCLK) 0.1V DD tWLS tWHS tDSS tDHS DB7 (SID) Figure 26. Serial Interface Characteristics (V DD = 2.4 to 3.6V, Ta = -40 to +85°C) Max. Unit Remark Item Signal Symbol Min. Typ. Serial clock cycle SCLK high pulse width SCLK low pulse width DB6 (SCLK) tCYS tWHS tWLS 250 100 100 - - ns Address setup time Address hold time RS tASS tAHS 150 150 - - ns Data setup time Data hold time DB7 (SID) tDSS tDHS 100 100 - - ns CS1B setup time CS1B hold time CS1B tCSS tCHS 150 150 - - ns Note: 1. The input signal rising time and falling time (tr,tf) is specified at 15ns or less. 52 S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD Reset Input Timing tRW RESETB tR Internal status During reset Reset complete Figure 27. Reset Input Timing (V DD = 2.4 to 3.6V, Ta = -40 to +85°C) Remark Max. Unit Item Signal Symbol Min. Typ. Reset low pulse width RESETB tRW 1.0 - - µs Reset time - tR - - 1.0 µs 53 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 REFERENCE APPLICATIONS MICROPROCESSOR INTERFACE In Case of Interfacing with 6800-series (PS = “H”, C68 = “H”) CS1B CS2 6800-series MPU RS E RW DB0 to DB7 RESETB V DD V DD CS1B CS2 RS E_RDB S6B0725 RW_WRB DB0 to DB7 RESETB C68 PS Figure 29. Interfacing with 6800-series In Case of Interfacing with 8080-series (PS = “H”, C68 = “L”) 8080-series MPU CS1B CS2 RS RDB WRB DB0 to DB7 RESETB VSS VDD CS1B CS2 RS S6B0725 E_RDB RW_WRB DB0 to DB7 RESETB C68 PS Figure 30. Interfacing with 8080-series 54 S6B1400X S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD In Case of Serial Interface with RS Pin (PS = “L”, C68 = “H ”) MPU CS1B CS2 RS SID SCLK RESETB OPEN VDD VSS CS1B CS2 RS S6B0725 DB7(SID) DB6(SCLK) RESETB DB0 to DB5 C68 PS Figure 31. 4 Pin Serial Interface In Case of Serial Interface with Software Command (PS = “L”, C68 = “L ”) CS1B CS2 MPU VSS or VDD SID SCLK RESETB OPEN VSS VSS CS1B CS2 RS S6B0725 DB7(SID) DB6(SCLK) RESETB DB0 to DB5 C68 PS Figure 32. 3 Pin SPI Serial Interface 55 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X CONNECTIONS BETWEEN S6B1400X AND LCD PANEL Single Chip Structure (1/65 Duty Configurations) ♣ ♦ ♥ ♠ Ξ ♣ ♦ ♥ 64 × 104 pixels 64 × 104 pixels ♣ ♦ ♥ ♠ Ξ SEG103 COMS COM0 : COM31 ........... S6B1400X (Bottom View) ♣ ♦ ♥ SEG0 COM32 : COM63 COMS SEG0 S6B1400X (Top View) SEG103 ........... COMS COM63 : COM32 SEG0 ♣ ♦ ♥ ♠ Ξ 64 × 104 pixels ♣ ♦ ♥ ♠ Ξ Figure 35. SHL = 0, ADC = 1 56 ♠ Ξ ........... SEG103 COMS COM0 : COM31 S6B1400X (Top View) COM3 2 : COM6 3 COMS Figure 33. SHL = 1, ADC = 1 COM31 : COM0 COMS ♠ Ξ Figure 34. SHL = 1, ADC = 0 COMS COM63 : COM32 COM31 : COM0 COMS S6B1400X (Bottom View) SEG0 ............ SEG103 ♣ ♦ ♥ ♠ Ξ 64 × 104 pixels ♣ ♦ ♥ ♠ Ξ Figure 36. SHL = 0, ADC = 0 S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD Single Chip Structure (1/55 Duty Configurations) ♣ ♦ ♥ ♠ Ξ ♣ ♦ ♥ 54 × 104 pixels 54 × 104 pixels ♣ ♦ ♥ ♠ Ξ SEG103 COMS COM0 : COM26 ........... S6B1400X (Bottom View) ♣ ♦ ♥ SEG0 COM37 : COM63 COMS SEG0 S6B1400X (Top View) SEG103 ........... COMS COM63 : COM37 SEG0 ♣ ♦ ♥ ♠ Ξ 54 × 104 pixels ♣ ♦ ♥ ♠ Ξ Figure 39. SHL = 0, ADC = 1 ♠ Ξ ........... SEG103 COMS COM0 : COM26 S6B1400X (Top View) COM37 : COM63 COMS Figure 37. SHL = 1, ADC = 1 COM26 : COM0 COMS ♠ Ξ Figure 38. SHL = 1, ADC = 0 COMS COM63 : COM37 COM26 : COM0 COMS S6B1400X (Bottom View) SEG0 ............ SEG103 ♣ ♦ ♥ ♠ Ξ 54 × 104 pixels ♣ ♦ ♥ ♠ Ξ Figure 40. SHL = 0, ADC = 0 57 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X Single Chip Structure (1/49 Duty Configurations) ♣ ♦ ♥ ♠ Ξ ♣ ♦ ♥ 48 × 104 pixels 48 × 104 pixels ♣ ♦ ♥ ♠ Ξ SEG103 COMS COM0 : COM23 ........... S6B1400X (Bottom View) ♣ ♦ ♥ SEG0 COM40 : COM63 COMS SEG0 S6B1400X (Top View) SEG103 ........... COMS COM63 : COM40 SEG0 ♣ ♦ ♥ ♠ Ξ 48 × 104 pixels ♣ ♦ ♥ ♠ Ξ Figure 43. SHL = 0, ADC = 1 58 ♠ Ξ ........... SEG103 COMS COM0 : COM23 S6B1400X (Top View) COM40 : COM6 3 COMS Figure 41. SHL = 1, ADC = 1 COM23 : COM0 COMS ♠ Ξ Figure 42. SHL = 1, ADC = 0 COMS COM63 : COM40 COM23 : COM0 COMS S6B1400X (Bottom View) SEG0 ............ SEG103 ♣ ♦ ♥ ♠ Ξ 48 × 104 pixels ♣ ♦ ♥ ♠ Ξ Figure 44. SHL = 0, ADC = 0 S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD Single Chip Structure (1/33 Duty Configurations) ♣ ♦ ♥ ♠ Ξ ♣ ♦ ♥ 32 × 104 pixels 32 × 104 pixels ♣ ♦ ♥ ♠ Ξ SEG103 COMS COM0 : COM15 ........... S6B1400X (Bottom View) ♣ ♦ ♥ SEG0 COM48 : COM63 COMS SEG0 S6B1400X (Top View) SEG103 ........... COMS COM63 : COM48 SEG0 ♣ ♦ ♥ ♠ Ξ 32 × 104 pixels ♣ ♦ ♥ ♠ Ξ Figure 47. SHL = 0, ADC = 1 ♠ Ξ ........... SEG103 COMS COM0 : COM15 S6B1400X (Top View) COM48 : COM6 3 COMS Figure 45. SHL = 1, ADC = 1 COM15 : COM0 COMS ♠ Ξ Figure 46. SHL = 1, ADC = 0 COMS COM63 : COM48 COM15 : COM0 COMS S6B1400X (Bottom View) SEG0 ............ SEG103 ♣ ♦ ♥ ♠ Ξ 32 × 104 pixels ♣ ♦ ♥ ♠ Ξ Figure 48. SHL = 0, ADC = 0 59 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X Application Circuit for Serial Mode n 4 Pin SPI Serial Interface LCD MODULE VCC C1 - + VCC PORT4 PORT3 PORT1 PORT0 GND MPU RESET GND VLCD V DD VCI SCLK COM[0:64] SID RS CS1B COMMONS LCD PANEL S6B1400X SEG[0:103] RESETB V SS SEGMENTS GND * C1 is greater than 1 µF Figure 49. S6B1400X Application Circuit for 4 Pin SPI Serial Interface 60 S6B1400X