Data Sheet S6D0144 Preliminary 128-RGB X 160-DOT SINGLE CHIP DRIVER IC WITH INTERNAL GRAM FOR 262,144 Colors TFT-LCD January 6, 2006 Ver. 0.7 Prepared by Checked by Approved by Hak-Seong. Lee [email protected] Byoung-Ha, Kim Yhong-Deug, Ma [email protected] [email protected] System LSI Division Device Solution Network SAMSUNG ELECTRONICS CO., LTD. Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team. 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY CONTENTS INTRODUCTION ..................................................................................................................................................................... 5 FEATURES................................................................................................................................................................................ 6 BLOCK DIAGRAM.................................................................................................................................................................. 7 PHYSICAL INFORMATION .................................................................................................................................................. 8 PAD CONFIGURATION ..................................................................................................................................................... 8 ALIGN KEY CONFIGURATION ..................................................................................................................................... 10 PAD COORDINATES......................................................................................................................................................... 11 PIN DESCRIPTION................................................................................................................................................................ 17 FUNCTIONAL DESCRIPTION............................................................................................................................................ 23 SYSTEM INTERFACE....................................................................................................................................................... 23 RGB INTERFACE .............................................................................................................................................................. 23 COMMAND BOX................................................................................................................................................................ 23 GRAPHICS RAM................................................................................................................................................................ 24 PANEL INTERFACE CONTROLLER ............................................................................................................................ 24 GRAYSCALE VOLTAGE GENERATOR ....................................................................................................................... 24 OSCILLATION CIRCUIT (OSC) ..................................................................................................................................... 24 SOURCE DRIVER CIRCUIT ............................................................................................................................................ 24 GATE DRIVER CIRCUIT ................................................................................................................................................. 24 GRAM ADDRESS MAP ..................................................................................................................................................... 25 INSTRUCTIONS..................................................................................................................................................................... 26 OUTLINE............................................................................................................................................................................. 26 INSTRUCTION TABLE..................................................................................................................................................... 27 INSTRUNCTION DESCRIPTIONS.................................................................................................................................. 29 INDEX REGISTER (IR) ..................................................................................................................................................... 29 STATUS READ .................................................................................................................................................................. 29 SYSTEM CONTROL (R00h) .............................................................................................................................................. 29 DRIVER OUTPUT CONTROL (R01h).............................................................................................................................. 30 LCD INVERSION CONTROL (R02h) ............................................................................................................................... 34 ENTRY MODE (R03h)....................................................................................................................................................... 35 DISPLAY CONTROL (R07h)............................................................................................................................................. 38 BLANK PERIOD CONTROL 1 (R08h).............................................................................................................................. 40 FRAME CYCLE CONTROL (R0Bh).................................................................................................................................. 42 EXTERNAL DISPLAY INTERFACE CONTROL (R0Ch) .................................................................................................. 43 POWER CONTROL 1 (R10h)............................................................................................................................................ 45 GAMMA CONTROL 1 (R11h)........................................................................................................................................... 48 POWER CONTROL 2 (R12h)............................................................................................................................................ 49 POWER CONTROL 3 (R13h)............................................................................................................................................ 49 POWER CONTROL 4 (R14h)............................................................................................................................................ 49 GRAM ADDRESS SET (R21h) .......................................................................................................................................... 53 WRITE DATA TO GRAM (R22h) ...................................................................................................................................... 54 READ DATA FROM GRAM (R22H) ................................................................................................................................. 55 GAMMA CONTROL 2 (R30h to R37h) ............................................................................................................................. 56 GAMMA CONTROL 3 (R38h)........................................................................................................................................... 57 GATE SCAN POSITION (R40h)........................................................................................................................................ 58 2 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY 1st SCREEN DRIVING POSITION (R42h)......................................................................................................................... 59 2nd SCREEN DRIVING POSITION (R43h)........................................................................................................................ 59 HORIZONTAL RAM ADDRESS POSITION (R44h).......................................................................................................... 60 VERTICAL RAM ADDRESS POSITION (R45h) ............................................................................................................... 60 OSCILLATOR CONTROL (R61h) ..................................................................................................................................... 65 DC/DC CONVERT LOW POWER MODE SETTING (R69h)............................................................................................ 66 SOURCE DRIVER PRE-DRIVING PERIOD SETTING (R70h)........................................................................................ 67 GATE OUTPUT PERIOD CONTROL (R71h)................................................................................................................... 68 SOFTWARE RESET CONTROL (R72h) ............................................................................................................................ 69 TEST_KEY (R73h) ............................................................................................................................................................. 70 PUMPING CLOCK SOURCE SELECTION (RB3h) ......................................................................................................... 71 MTP CONTROL (RB4h) .................................................................................................................................................... 72 MTP DATA READ (RBDh) ................................................................................................................................................ 74 RESET FUNCTION ................................................................................................................................................................ 76 POWER CONTROL ............................................................................................................................................................... 77 POWER SUPPLY CIRCUIT .............................................................................................................................................. 77 PATTERN DIAGRAMS FOR VOLTAGE SETTING ..................................................................................................... 78 SETUP FLOW OF POWER SUPPLY ............................................................................................................................... 79 VOLTAGE REGULATION FUNCTION ............................................................................................................................. 80 VCOM SETTING .................................................................................................................................................................... 81 INTERFACE SPECIFICATION ........................................................................................................................................... 82 SYSTEM INTERFACE....................................................................................................................................................... 83 68-18BIT CPU INTERFACE ............................................................................................................................................. 84 68-16BIT CPU INTERFACE ............................................................................................................................................. 85 68-9BIT CPU INTERFACE ............................................................................................................................................... 86 68-8BIT CPU INTERFACE ............................................................................................................................................... 87 80-18BIT CPU INTERFACE ............................................................................................................................................. 88 80-16BIT CPU INTERFACE ............................................................................................................................................. 89 80-9BIT CPU INTERFACE ............................................................................................................................................... 90 80-8BIT CPU INTERFACE ............................................................................................................................................... 91 SERIAL PERIPHERAL INTERFACE ................................................................................................................................ 92 RGB INTERFACE............................................................................................................................................................... 96 MOTION PICTURE DISPLAY .......................................................................................................................................... 96 18BIT RGB INTERFACE................................................................................................................................................... 97 16BIT RGB INTERFACE................................................................................................................................................... 98 6BIT RGB INTERFACE..................................................................................................................................................... 99 INTERFACE SWAPPING FOR MEMORY ACCESS .................................................................................................. 101 DISPLAY MODES AND GRAM ACCESS CONTROL..................................................................................................... 101 GRAM ACCESS VIA RGB INTERFACE AND SPI.......................................................................................................... 102 TRANSITION SEQUENCES BETWEEN DISPLAY MODES .......................................................................................... 103 PANEL CONTROL INTERFACE................................................................................................................................... 104 INTERCONNECTION BETWEEN PANEL AND S6D0144............................................................................................. 104 TIMING DIAGRAMS ....................................................................................................................................................... 105 GAMMA ADJUSTMENT FUNCTION .............................................................................................................................. 108 STRUCTURE OF GRAYSCALE AMPLIFIER ............................................................................................................. 109 GAMMA ADJUSTMENT REGISTER............................................................................................................................ 111 LADDER RESISTOR / 8-TO-1 SELECTOR ................................................................................................................... 113 VARIABLE RESISTOR.................................................................................................................................................... 113 3 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY 8-TO-1 SELECTOR ........................................................................................................................................................... 115 OUTPUT LEVEL AS THE FUNCTION OF GRAM DATA.......................................................................................... 120 THE 8-COLOR DISPLAY MODE ...................................................................................................................................... 122 INSTRUCTION SET UP FLOW ......................................................................................................................................... 124 DISPLAY ON / OFF SEQUENCE.................................................................................................................................... 124 D-STAND-BY / STAND-BY / SLEEP SEQUENCE........................................................................................................ 125 OSCILLATION CIRCUIT................................................................................................................................................... 126 APPLICATION CIRCUIT ................................................................................................................................................... 127 ELECTRICAL SPECIFICATIONS .................................................................................................................................... 128 ABSOLUTE MAXIMUM RATINGS .............................................................................................................................. 128 DC CHARACTERISTICS ................................................................................................................................................ 129 AC CHARACTERISTICS ................................................................................................................................................ 132 68-SYSTEM 18/16/9/8BIT INTERFACE.......................................................................................................................... 132 80-SYSTEM 18/16/9/8BIT INTERFACE.......................................................................................................................... 133 RGB INTERFACE ........................................................................................................................................................... 134 SERIAL PERIPHERAL INTERFACE .............................................................................................................................. 135 RESETB ........................................................................................................................................................................... 136 REVISION HYSTORY......................................................................................................................................................... 141 NOTICE ................................................................................................................................................................................. 144 4 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY INTRODUCTION S6D0144 is a single chip solution for TFT-LCD panel: source driver with built-in memory, gate driver and power circuits are integrated on this LSI. It can display to the maximum of 128-RGB x 160-dot graphics on 260k-color TFT-LCD panel. S6D0144 supports 18-/16-/9-/8-bits high-speed parallel bus interfaces and Serial Peripheral Interface (SPI). In addition, the LSI has 18-/16-/6-bit RGB interface for motion picture display. The motion picture area can be specified by Window Addressing Function. The specified window area can be updated selectively in order for motion picture to be able to be displayed independently of and simultaneously with still picture display. S6D0144 has various functions for reducing the power consumption of TFT-LCD system: The LSI operates at low voltage and has internal GRAMs to store 128-RGB x 160-dot 260k-color image data. Additionally, it has an internal booster that generates the TFT-LCD driving voltage, breeder resistance and the voltage follower circuit for TFT-LCD driver. S6D0144 is suitable for any medium-sized or small portable mobile solution requiring long-term driving capabilities such as digital cellular phones supporting a web browser, bi-directional pagers, and small PDAs. 5 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY FEATURES Overalls - 128-RGB x 160-dot Resolution, 384ch Source Driver / 160ch Gate Driver Various color-display control functions - 262,144 colors can be displayed at the same time (including gamma adjust) - 65,536 colors, 8 colors can be displayed Various Interfaces - 18-/16-/9-/8-bit high-speed parallel bus interfaces including MDT(Multiple Data Transfer) mode. - serial peripheral interface - 18-/16-/6-bit RGB interfaces for motion picture display Various Graphic Operations - Window-Addressing Function to display motion picture independently of still image display - Image Rotation / Mirroring Function Internal RAM capacity: 128 x 18 x 160 = 368,640 bits Alternating functions for TFT-LCD counter-electrode power Low-power operation supports - Power-save functions (standby mode, sleep mode, deep-standby mode) - Partial display (up to two separated screens) in any position - Maximum 6-times step-up circuit for generating driving voltage - Equalizing function for the switching performance of step-up circuits and operational amplifiers Internal oscillation and external hardware reset - The S6D0144 can provide R-C oscillation without external resistor. Internal power supply circuit - Step-up circuit: four to six times, positive-polarity inversion Applying voltage - VDD3 to VSS = 1.65V to 3.3V - VCI to VSS = 2.5V to 3.3V - VDD to VSS = 1.4V to 1.6V (internal regulator only) (I/O operating voltage range) (internal reference power-supply voltage range) (internal core operating voltage range) Generated voltage - For the source driver : AVDD to VSS = 3.5V to 5.5V (power supply for driving circuits) GVDD to VSS = 3.0V to 5.0V (reference power supply for grayscale voltages) - For the gate driver : VGH to VGL = 14.0V to 30.0V VGH to VSS = 7.0V to 16.5V VGL to VSS = -13.5V to -7.0V - For the TFT-LCD counter electrode : Vcom amplitude(max) = 6.0V VcomH to VSS (max) = GVDD VomL to VSS (max) =1.0V to -VCI1 + 0.5V - The S6D0144 has various VCOM amplitude adjusting methods. User can select external resistor setting or internal electronic volume setting or MTP programmed setting. 6 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY BLOCK DIAGRAM Gate Clocks Source Data S6D0144 GATE_DRIVER Gamma Adjusting Circuit Gray Scale Voltage Generator Source Driver (Data) DRIVER_CON (Logic) VCI PANEL_IF_CON POWER_GEN GRAM ETC TEST ( Oscillator POR) POWER_ CON CBOX POWER_STEPUP HOST_IF CPU I/F RGB I/F SPI Figure 1 : Block Diagram of S6D0144 7 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY PHYSICAL INFORMATION PAD CONFIGURATION TOP VIEW Figure 2 : Pad Configuration 8 S6D0144 PRELIMINARY S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY Table 1 : S6D0144 Pad Dimensions Items Pad name. Size X 12990 Y 930 Unit 1) Chip size E 91 F 40 A 105 Input Bump pad size um Output Bump to Bump B 21 Output D 35 Input G 60 Output C 22 Bump pad pitch [NOTE] Scribe lane included in this chip size (Scribe lane: 100 um) CHIP EDGE (Include S/L 100 um) C D A B 9 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY ALIGN KEY CONFIGURATION DUMMY DUMMY wafer thickness : 470 um DUMMY Gold bump height : 15 ± 3um (typ.) 2. G4 G3 DUMMY DUMMY 10 1. DUMMY G2 G1 DUMMY DUMMY 30um30um30um 170um 15um 15um 90um Figure 3 : COG align key S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY PAD COORDINATES Table 2 : Pad Center Coordinates [Unit : um] # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 X -6180 -6120 -6060 -6000 -5940 -5880 -5820 -5760 -5700 -5640 -5580 -5520 -5460 -5400 -5340 -5280 -5220 -5160 -5100 -5040 -4980 -4920 -4860 -4800 -4740 -4680 -4620 -4560 -4500 -4440 -4380 -4320 -4260 -4200 -4140 -4080 -4020 -3960 -3900 -3840 -3780 -3720 -3660 -3600 -3540 -3480 -3420 -3360 -3300 -3240 Y -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 Name DUMMY VCOMOUT VCOMOUT VCOMOUT DUMMY VGH VGH VGH VGH VGH VGH DUMMYR1 DUMMYR2 C22+ C22+ C22C22C21+ C21+ C21C21DUMMY VGL VGL VGL VGL VGL VGL VGL VGL VGL VGL VGL DUMMY DUMMY DUMMY DUMMY DUMMY NDT_EN TEST_IN0 TEST_IN1 TEST_IN2 TEST_IN3 TEST_IN4 IM0 IM1 IM2 IM3 RESETB TEST_MODE0 # 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 X -3180 -3120 -3060 -3000 -2940 -2880 -2820 -2760 -2700 -2640 -2580 -2520 -2460 -2400 -2340 -2280 -2220 -2160 -2100 -2040 -1980 -1920 -1860 -1800 -1740 -1680 -1620 -1560 -1500 -1440 -1380 -1320 -1260 -1200 -1140 -1080 -1020 -960 -900 -840 -780 -720 -660 -600 -540 -480 -420 -360 -300 -240 Y -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 Name TEST_MODE1 TEST_MODE2 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 FLM/TEST_OUT0 TEST_OUT1 TEST_OUT2 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 TEST_OUT3 TEST_OUT4 SDO SDI VSYNC HSYNC DOTCLK ENABLE RWB_RDB E_WRB RS CSB DSTB_EN EX_CLK VGS VGS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSC # 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 X -180 -120 -60 0 60 120 180 240 300 360 420 480 540 600 660 720 780 840 900 960 1020 1080 1140 1200 1260 1320 1380 1440 1500 1560 1620 1680 1740 1800 1860 1920 1980 2040 2100 2160 2220 2280 2340 2400 2460 2520 2580 2640 2700 2760 Y -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 Name VSSC VSSC VSSC VSSC VSSC VSSC VSSA VSSA VSSA VSSA VSSA VSSA VSSA VDD VDD VDD VDD VDD VDDM VDDM VDDM VDDM VDDM RVDD RVDD RVDD RVDD RVDD VDD3 VDD3 VDD3 VDD3 VDD3 DUMMY MTPD MTPD MTPD MTPD MTPD MTPD MTPD MTPD MTPG MTPG MTPG MTPG MTPG MTPG MTPG MTPG 11 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY Table 3 : Pad Center Coordinates [Unit : um] # 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 12 X 2820 2880 2940 3000 3060 3120 3180 3240 3300 3360 3420 3480 3540 3600 3660 3720 3780 3840 3900 3960 4020 4080 4140 4200 4260 4320 4380 4440 4500 4560 4620 4680 4740 4800 4860 4920 4980 5040 5100 5160 5220 5280 5340 5400 5460 5520 5580 5640 5700 5760 Y -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 Name VCI VCI VCI VCI VCI VCI1 VCI1 VCI1 VCI1 VCI1 VCI1 VCOML VCOML VCOMH VCOMH VCOMR GVDD GVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD VCL VCL VCL VCL VCL VCL C11C11C11C11C11C11+ C11+ C11+ C11+ C11+ C23C23C23C23C23C23+ C23+ C23+ # 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 X 5820 5880 5940 6000 6060 6120 6180 6248 6226 6204 6182 6160 6138 6116 6094 6072 6050 6028 6006 5984 5962 5940 5918 5896 5874 5852 5830 5808 5786 5764 5742 5720 5698 5676 5654 5632 5610 5588 5566 5544 5522 5500 5478 5456 5434 5412 5390 5368 5346 5324 Y -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 Name C23+ C23+ DUMMY VCOMOUT VCOMOUT VCOMOUT DUMMY DUMMY DUMMY DUMMY DUMMY G2 G4 G6 G8 G10 G12 G14 G16 G18 G20 G22 G24 G26 G28 G30 G32 G34 G36 G38 G40 G42 G44 G46 G48 G50 G52 G54 G56 G58 G60 G62 G64 G66 G68 G70 G72 G74 G76 G78 # 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 X 5302 5280 5258 5236 5214 5192 5170 5148 5126 5104 5082 5060 5038 5016 4994 4972 4950 4928 4906 4884 4862 4840 4818 4796 4774 4752 4730 4708 4686 4664 4642 4620 4598 4576 4554 4532 4510 4488 4466 4444 4422 4400 4378 4356 4334 4312 4290 4268 4246 4224 Y 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 Name G80 G82 G84 G86 G88 G90 G92 G94 G96 G98 G100 G102 G104 G106 G108 G110 G112 G114 G116 G118 G120 G122 G124 G126 G128 G130 G132 G134 G136 G138 G140 G142 G144 G146 G148 G150 G152 G154 G156 G158 G160 DUMMY DUMMY VCOMOUT VCOMOUT VCOMOUT VCOMOUT DUMMY DUMMY SOUT384 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY Table 4 : Pad Center Coordinates [Unit : um] # 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 X 4202 4180 4158 4136 4114 4092 4070 4048 4026 4004 3982 3960 3938 3916 3894 3872 3850 3828 3806 3784 3762 3740 3718 3696 3674 3652 3630 3608 3586 3564 3542 3520 3498 3476 3454 3432 3410 3388 3366 3344 3322 3300 3278 3256 3234 3212 3190 3168 3146 3124 Y 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 Name SOUT383 SOUT382 SOUT381 SOUT380 SOUT379 SOUT378 SOUT377 SOUT376 SOUT375 SOUT374 SOUT373 SOUT372 SOUT371 SOUT370 SOUT369 SOUT368 SOUT367 SOUT366 SOUT365 SOUT364 SOUT363 SOUT362 SOUT361 SOUT360 SOUT359 SOUT358 SOUT357 SOUT356 SOUT355 SOUT354 SOUT353 SOUT352 SOUT351 SOUT350 SOUT349 SOUT348 SOUT347 SOUT346 SOUT345 SOUT344 SOUT343 SOUT342 SOUT341 SOUT340 SOUT339 SOUT338 SOUT337 SOUT336 SOUT335 SOUT334 # 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 X 3102 3080 3058 3036 3014 2992 2970 2948 2926 2904 2882 2860 2838 2816 2794 2772 2750 2728 2706 2684 2662 2640 2618 2596 2574 2552 2530 2508 2486 2464 2442 2420 2398 2376 2354 2332 2310 2288 2266 2244 2222 2200 2178 2156 2134 2112 2090 2068 2046 2024 Y 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 Name SOUT333 SOUT332 SOUT331 SOUT330 SOUT329 SOUT328 SOUT327 SOUT326 SOUT325 SOUT324 SOUT323 SOUT322 SOUT321 SOUT320 SOUT319 SOUT318 SOUT317 SOUT316 SOUT315 SOUT314 SOUT313 SOUT312 SOUT311 SOUT310 SOUT309 SOUT308 SOUT307 SOUT306 SOUT305 SOUT304 SOUT303 SOUT302 SOUT301 SOUT300 SOUT299 SOUT298 SOUT297 SOUT296 SOUT295 SOUT294 SOUT293 SOUT292 SOUT291 SOUT290 SOUT289 SOUT288 SOUT287 SOUT286 SOUT285 SOUT284 # 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 X 2002 1980 1958 1936 1914 1892 1870 1848 1826 1804 1782 1760 1738 1716 1694 1672 1650 1628 1606 1584 1562 1540 1518 1496 1474 1452 1430 1408 1386 1364 1342 1320 1298 1276 1254 1232 1210 1188 1166 1144 1122 1100 1078 1056 1034 1012 990 968 946 924 Y 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 Name SOUT283 SOUT282 SOUT281 SOUT280 SOUT279 SOUT278 SOUT277 SOUT276 SOUT275 SOUT274 SOUT273 SOUT272 SOUT271 SOUT270 SOUT269 SOUT268 SOUT267 SOUT266 SOUT265 SOUT264 SOUT263 SOUT262 SOUT261 SOUT260 SOUT259 SOUT258 SOUT257 SOUT256 SOUT255 SOUT254 SOUT253 SOUT252 SOUT251 SOUT250 SOUT249 SOUT248 SOUT247 SOUT246 SOUT245 SOUT244 SOUT243 SOUT242 SOUT241 SOUT240 SOUT239 SOUT238 SOUT237 SOUT236 SOUT235 SOUT234 13 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY Table 5 : Pad Center Coordinates [Unit : um] # 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 14 X 902 880 858 836 814 792 770 748 726 704 682 660 638 616 594 572 550 528 506 484 462 440 418 396 374 352 330 308 286 264 242 220 198 176 154 132 110 88 66 44 22 0 -22 -44 -66 -88 -110 -132 -154 -176 Y 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 Name SOUT233 SOUT232 SOUT231 SOUT230 SOUT229 SOUT228 SOUT227 SOUT226 SOUT225 SOUT224 SOUT223 SOUT222 SOUT221 SOUT220 SOUT219 SOUT218 SOUT217 SOUT216 SOUT215 SOUT214 SOUT213 SOUT212 SOUT211 SOUT210 SOUT209 SOUT208 SOUT207 SOUT206 SOUT205 SOUT204 SOUT203 SOUT202 SOUT201 SOUT200 SOUT199 SOUT198 SOUT197 SOUT196 SOUT195 SOUT194 SOUT193 SOUT192 SOUT191 SOUT190 SOUT189 SOUT188 SOUT187 SOUT186 SOUT185 SOUT184 # 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 X -198 -220 -242 -264 -286 -308 -330 -352 -374 -396 -418 -440 -462 -484 -506 -528 -550 -572 -594 -616 -638 -660 -682 -704 -726 -748 -770 -792 -814 -836 -858 -880 -902 -924 -946 -968 -990 -1012 -1034 -1056 -1078 -1100 -1122 -1144 -1166 -1188 -1210 -1232 -1254 -1276 Y 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 Name SOUT183 SOUT182 SOUT181 SOUT180 SOUT179 SOUT178 SOUT177 SOUT176 SOUT175 SOUT174 SOUT173 SOUT172 SOUT171 SOUT170 SOUT169 SOUT168 SOUT167 SOUT166 SOUT165 SOUT164 SOUT163 SOUT162 SOUT161 SOUT160 SOUT159 SOUT158 SOUT157 SOUT156 SOUT155 SOUT154 SOUT153 SOUT152 SOUT151 SOUT150 SOUT149 SOUT148 SOUT147 SOUT146 SOUT145 SOUT144 SOUT143 SOUT142 SOUT141 SOUT140 SOUT139 SOUT138 SOUT137 SOUT136 SOUT135 SOUT134 # 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 X -1298 -1320 -1342 -1364 -1386 -1408 -1430 -1452 -1474 -1496 -1518 -1540 -1562 -1584 -1606 -1628 -1650 -1672 -1694 -1716 -1738 -1760 -1782 -1804 -1826 -1848 -1870 -1892 -1914 -1936 -1958 -1980 -2002 -2024 -2046 -2068 -2090 -2112 -2134 -2156 -2178 -2200 -2222 -2244 -2266 -2288 -2310 -2332 -2354 -2376 Y 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 Name SOUT133 SOUT132 SOUT131 SOUT130 SOUT129 SOUT128 SOUT127 SOUT126 SOUT125 SOUT124 SOUT123 SOUT122 SOUT121 SOUT120 SOUT119 SOUT118 SOUT117 SOUT116 SOUT115 SOUT114 SOUT113 SOUT112 SOUT111 SOUT110 SOUT109 SOUT108 SOUT107 SOUT106 SOUT105 SOUT104 SOUT103 SOUT102 SOUT101 SOUT100 SOUT99 SOUT98 SOUT97 SOUT96 SOUT95 SOUT94 SOUT93 SOUT92 SOUT91 SOUT90 SOUT89 SOUT88 SOUT87 SOUT86 SOUT85 SOUT84 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY Table 6 : Pad Center Coordinates [Unit : um] # 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 X -2398 -2420 -2442 -2464 -2486 -2508 -2530 -2552 -2574 -2596 -2618 -2640 -2662 -2684 -2706 -2728 -2750 -2772 -2794 -2816 -2838 -2860 -2882 -2904 -2926 -2948 -2970 -2992 -3014 -3036 -3058 -3080 -3102 -3124 -3146 -3168 -3190 -3212 -3234 -3256 -3278 -3300 -3322 -3344 -3366 -3388 -3410 -3432 -3454 -3476 Y 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 Name SOUT83 SOUT82 SOUT81 SOUT80 SOUT79 SOUT78 SOUT77 SOUT76 SOUT75 SOUT74 SOUT73 SOUT72 SOUT71 SOUT70 SOUT69 SOUT68 SOUT67 SOUT66 SOUT65 SOUT64 SOUT63 SOUT62 SOUT61 SOUT60 SOUT59 SOUT58 SOUT57 SOUT56 SOUT55 SOUT54 SOUT53 SOUT52 SOUT51 SOUT50 SOUT49 SOUT48 SOUT47 SOUT46 SOUT45 SOUT44 SOUT43 SOUT42 SOUT41 SOUT40 SOUT39 SOUT38 SOUT37 SOUT36 SOUT35 SOUT34 # 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 X -3498 -3520 -3542 -3564 -3586 -3608 -3630 -3652 -3674 -3696 -3718 -3740 -3762 -3784 -3806 -3828 -3850 -3872 -3894 -3916 -3938 -3960 -3982 -4004 -4026 -4048 -4070 -4092 -4114 -4136 -4158 -4180 -4202 -4224 -4246 -4268 -4290 -4312 -4334 -4356 -4378 -4400 -4422 -4444 -4466 -4488 -4510 -4532 -4554 -4576 Y 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 Name SOUT33 SOUT32 SOUT31 SOUT30 SOUT29 SOUT28 SOUT27 SOUT26 SOUT25 SOUT24 SOUT23 SOUT22 SOUT21 SOUT20 SOUT19 SOUT18 SOUT17 SOUT16 SOUT15 SOUT14 SOUT13 SOUT12 SOUT11 SOUT10 SOUT9 SOUT8 SOUT7 SOUT6 SOUT5 SOUT4 SOUT3 SOUT2 SOUT1 DUMMY DUMMY DUMMY VCOM_OUT VCOM_OUT VCOM_OUT VCOM_OUT DUMMY DUMMY G159 G157 G155 G153 G151 G149 G147 G145 # 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 X -4598 -4620 -4642 -4664 -4686 -4708 -4730 -4752 -4774 -4796 -4818 -4840 -4862 -4884 -4906 -4928 -4950 -4972 -4994 -5016 -5038 -5060 -5082 -5104 -5126 -5148 -5170 -5192 -5214 -5236 -5258 -5280 -5302 -5324 -5346 -5368 -5390 -5412 -5434 -5456 -5478 -5500 -5522 -5544 -5566 -5588 -5610 -5632 -5654 -5676 Y 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 Name G143 G141 G139 G137 G135 G133 G131 G129 G127 G125 G123 G121 G119 G117 G115 G113 G111 G109 G107 G105 G103 G101 G99 G97 G95 G93 G91 G89 G87 G85 G83 G81 G79 G77 G75 G73 G71 G69 G67 G65 G63 G61 G59 G57 G55 G53 G51 G49 G47 G45 15 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY Table 7 : Pad Center Coordinates [Unit : um] # 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 16 X -5698 -5720 -5742 -5764 -5786 -5808 -5830 -5852 -5874 -5896 -5918 -5940 -5962 -5984 -6006 -6028 -6050 -6072 -6094 -6116 -6138 -6160 -6182 -6204 -6226 -6248 Y 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 215.5 355.5 Name G43 G41 G39 G37 G35 G33 G31 G29 G27 G25 G23 G21 G19 G17 G15 G13 G11 G9 G7 G5 G3 G1 DUMMY DUMMY DUMMY DUMMY S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY PIN DESCRIPTION Symbol VDD VDDM VDD3 I/O O/ Power I/ Power I/ Power Table 8 : Power supply pin description Description System power supply. S6D0144 has internal regulator. Regulated mode only : typ. 1.5V (1.4 ~ 1.6 V) System power supply for memory. Connect to VDD VDD level for I/O. (VDD3 : 1.65 ~ 3.3V) AVDD O/ Power A power output pin for source driver block that is generated from power block. Connect a capacitor for stabilization. (AVDD: 3.5 ~ 5.5V) GVDD O/ Power VCI I/ Power A Standard level for grayscale voltage generator. Connect a capacitor for stabilization. A power supply for internal reference circuits. Connect VDD3 when VDD3 = 2.5 to 3.3V. Connect a 2.5 to 3.3V external-voltage power supply when VDD3 = 1.65 to 2.5V. System ground (0V) VSS VSSC VSSA VGS VCI1 VCL VcomOUT I / Power I/ Power I/ Power I/ Power O/ Power Power O System ground level for step up circuit block. System ground level for analog circuit block. Reference voltage for gamma voltage generator. A reference voltage in step-up circuit 1. Connect a capacitor for stabilization. A power supply pin for generating VcomL. When VCL is higher than VSS, VcomL outputs VSS level. Connect a capacitor for stabilization. A power supply for the TFT-display counter electrode. Connect this pin to the TFT-display counter electrode. This pin is also used as equalizing function: When EQ = “High” period, all source drivers’ outputs are short to VcomOUT level (Hi-z). 17 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY Symbol I/O S6D0144 PRELIMINARY Table 9 : Power supply pin description (continued) Description A reference voltage of VcomH. When VcomH is externally adjusted, halt the internal adjuster of VcomH by setting the register and insert a variable resistor between GVDD and VSS. When this pin is not externally adjusted, leave it open and adjust VcomH by setting the internal register. VcomR I VcomH O This pin indicates a high level of Vcom generated in driving the Vcom alternation. Connect this pin to the capacitor for stabilization. O When the Vcom alternation is driven, this pin indicates a low level of Vcom. An internal register can be used to adjust the voltage. Connect this pin to a capacitor for stabilization. When the VCOMG bit is low, the VcomL output stops and a capacitor for stabilization is not needed. VcomL VGH O/ Power VGL O/ Power A positive power output pin for gate driver, internal step-up circuits, bias circuits, and operational amplifiers. Connect a capacitor for stabilization. A Negative power output pin for gate driver, bias circuits, and operational amplifiers. Connect a capacitor for stabilization. When internal VGL generator is not used, connect an external-voltage power supply higher than –13.75 V. To protect IC against Latch up, connect the cathode of the schottky diode to the VSS pad. And the anode of the schottky diode to the VGL pad. Refer to application circuit. Connect a capacitor for stabilization. C11+,C11- - Connect the step-up capacitor for generating the AVDD level. C22+, C22C21+, C21- - Connect a step-up capacitor for generating the VGL/VGH level. C23+,C23- - Connect a step-up capacitor for generating the VCL level. 18 S6D0144 PRELIMINARY Symbol I/O 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY Table 10 : System interface pin description Description Selects the System interface mode. IM[3:0] Description 4’b0000 4’b0001 4’b0010 4’b0011 IM[3:0] / ID I CSB I RS I E_WRB / SCL I RWB_RDB I DB[17:0] [NOTE] SDI SDO I/O I O 68-16bit CPU interface 68-8bit CPU interface 80-16bit CPU interface 80-8bit CPU interface Serial peripheral interface (SPI) 4’b010x IM[0] = ID Reserved 4’b011x 4’b1000 68-18bit CPU interface 4’b1001 68-9bit CPU interface 4’b1010 80-18bit CPU interface 4’b1011 80-9bit CPU interface Reserved 4’b11xx Selects the S6D0144: - Low: S6D0144 is selected and can be accessed. - High: S6D0144 is not selected and cannot be accessed. Must be fixed to VDD3 level when not used. Selects the register. - Low : Index / status - High : Control Must be fixed to VDD3 or VSS level when SPI mode. In 68-system mode, this serves as write/read enable strobe (E). In 80-system mode, this serves as a write strobe signal (WRB). In SPI mode, it serves as a synchronous clock (SCL). In 68-system mode, this is used to select operation, read or write. (RWB) In 80-system mode, this serves as a read strobe signal. (RDB). Must be fixed to VDD3 or VSS level when SPI mode. Data Bus. Interface Mode Description IM[3:0] Index Data 4’b0000 68-16bit CPU interface DB[8:1] DB[17:10], DB[8:1] 4’b0001 68-8bit CPU interface DB[17:10] DB[17:10] 4’b0010 80-16bit CPU interface DB[8:1] DB[17:10], DB[8:1] 4’b0011 80-8bit CPU interface DB[17:10] DB[17:10] 4’b010x Serial peripheral interface (SPI) Reserved 4’b011x 4’b1000 68-18bit CPU interface DB[8:1] DB[17:0] 4’b1001 68-9bit CPU interface DB[17:10] DB[17:9] 4’b1010 80-18bit CPU interface DB[8:1] DB[17:0] 4’b1011 80-9bit CPU interface DB[17:10] DB[17:9] Reserved 4’b11xx Must be fixed to VDD3 or VSS level when not used. Serial input data. Must be fixed to VDD3 or VSS level when not used. Serial output data. Leave this pin open when not used. [NOTE] When used as system interface. 19 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY Symbol I/O ENABLE I VSYNC I HSYNC I DOTCLK I DB[17:0] [NOTE] I [NOTE] When used as RGB I/F 20 S6D0144 PRELIMINARY Table 11 : RGB interface pin description (Continued) Description Data enable signal of RGB interface. When ENABLE is in active state data on RGB bus is valid, but when this is not in active state data on RGB bus is invalid. (For details, refer to the description of EPL register) Must be fixed to VDD3 level when not used. Synchronous signal of frame. (Active Low Pin) Must be fixed to VDD3 or VSS level when not used. Synchronization signal of a horizontal line. (Active Low Pin) Must be fixed to VDD3 or VSS level when not used. Data Clock of RGB interface. Must be fixed to VDD3 or VSS level when not used. Serves as an input data bus for RGB I/F. - 6-bit interface: DB[17:12] - 16-bit interface: {DB[17:13], DB[11:1]} - 18-bit interface: DB[17:0] Must be fixed to VDD3 or VSS level when not used. S6D0144 PRELIMINARY Symbol I/O S1 - S384 O G1 - G160 O 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY Table 12 : Display pin description Description Source driver output pins. The SS bit can change the shift direction of the source signal. For example, if SS = 0, gray data of S1 is read from RAM address 0000h. If SS = 1, contents of RAM address 0000h is out from S384. S1, S4, S7, ... S(3n-1) : display Red (R) (SS = 0) S2, S5, S8, ... S(3n-2) : display Green (G) (SS = 0) S3, S6, S9, ... S(3n) : display Blue (B) (SS = 0) Gate driver output pins. The output of driving circuit is whether VGH or VGL VGH : gate-ON level VGL : gate-OFF level Table 13 : Oscillator and internal power regulator pin description Description Symbol I/O MTPD I MTP Program pin.16V ~ 16.5V. Leave this pin open when not used. MTPG I MTP Erase initial pin. 19V ~ 19.5V. Leave this pin open when not used. RESETB I Reset pin. Initializes the LSI when low. Must be reset after power-on. Leave this pin open when not used. DSTB_EN I Deep standby mode enable : fix to VDD3 level. Deep standby mode disable : fix to VSS level. RVDD O Internal power regulated-RVDD output (typ. 1.5V). Connect a capacitor for stabilization. 21 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY Symbol I/O S6D0144 PRELIMINARY Table 14 : DUMMY pin description Description TEST_IN[4:0] I Test pin. In normal operation, leave this pin open or fix to VSS level. TEST_MODE[2:0] I Test pin. In normal operation, leave this pin open or fix to VSS level. FLM/TEST_OUT[0] O Frame start signal. Leave this pin open when not used. TEST_OUT[4:1] O Test pin. In normal operation, leave this pin open. DUMMY - Dummy pin. These pins have no connection to the internal circuit. EX_CLK I Test pin. In normal operation, leave this pin open or fix to VDD3 level. (Test Mode : 140kHz ~ 340kHz) NDT_EN I Test signal input pin. In normal operation, leave this pin open or fix to VSS level. DUMMYR1 DUMMYR2 - Contact resistance measurement pin. In normal operation, leave this pin open. 22 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY FUNCTIONAL DESCRIPTION SYSTEM INTERFACE S6D0144 has nine high-speed system interfaces: 80-system 18/16/9/8bit CPU Interfaces, 68-system 18/16/9/8bit CPU Interfaces and a serial peripheral (SPI: Serial Peripheral Interface). The IM[3:0] pin determines the interface mode. Users may write/read data to/from internal GRAM (Graphics RAM) as well as a lot of internal control registers through these system interfaces. All instructions except Oscillation Start performed with 0-cycle, so the instructions can be written in succession. When users want to access the LSI, they must generate control signals as shown below. E / WRB Table 15 : Register Selection (80/68-8/9/16/18bit CPU Interface) RS Operations RWB / RDB 1/0 0/1 0 Write indexes into IR (Index Register). 1/1 1/0 0 Read internal status. 1/0 0/1 1 Write into control registers or GRAM. 1/1 1/0 1 Read data from control registers or GRAM. RWB Bit Table 16 : Register Selection (Serial Peripheral Interface) RS Bit Operations 0 0 Write indexes into IR (Index Register). 1 0 Read internal status. 0 1 Write into control registers or GRAM. 1 1 Read data from control registers or GRAM. RGB INTERFACE S6D0144 has RGB interface for the reproduction of motion picture display. When the RGB interface is used, the synchronization signals (VSYNC, HSYNC, and DOTCLK) are available for the display operation. The data for display (DB[17:0]) are written according to the values of ENABLE and DOTCLK. This allows flicker-free update of screen. COMMAND BOX S6D0144 has a command box to control internal operations and many internal analog blocks including Power Blocks, Source Driver and Gate Driver. 23 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY GRAPHICS RAM The graphics RAM (GRAM) has 18 bits/pixel and stores the bit-pattern data of 128-RGB x 160 pixels. S6D0144 has an address counter for GRAM access. The address counter (AC) assigns addresses to the GRAM. When an address set instruction is performed, the address from system interface is sent to this AC. After writing into GRAM, the AC is automatically increased (or decremented) by 1. But after reading data from GRAM, the AC is not updated. Window Address Function allows data to be written only into the Window specified by some control registers. PANEL INTERFACE CONTROLLER The Panel Interface Controller generates timing signals for TFT-LCD Driver and control signals for the operation of internal circuits such as source driver and GRAM. The GRAM read operations done by this Panel Interface Controller and GRAM write operations done through system interface are performed independently to avoid the interference between them. GRAYSCALE VOLTAGE GENERATOR The grayscale voltage circuit generates a certain voltage level that is specified by the grayscale ϒ-adjusting resistor for LCD driver circuit. By use of the generator, 262,144 colors can be displayed at the same time. For details, see the ϒ-adjusting resistor section. OSCILLATION CIRCUIT (OSC) The S6D0144 can provide R-C oscillation without external resistor. The appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the register setting value[R61h]. Clock pulse can also be supplied externally. Since R-C oscillation stops during the standby mode, current consumption can be reduced. For details, see the Oscillation Circuit section. SOURCE DRIVER CIRCUIT The liquid crystal display source driver circuit consists of 384 drivers (S1 to S384). Display pattern data is latched when 384-bit data has arrived. Then the latched data enables the source drivers to output to expected voltage level. The SS bit can change the shift direction of 384-bit data by selecting an appropriate direction for the device-mounted configuration. GATE DRIVER CIRCUIT The liquid crystal display gate driver circuit consists of 160 gate drivers (G1 to G160). The VGH or VGL level is output by the signal from the gate control circuit. G1 and G160 are IC maker’s test pins. 24 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY GRAM ADDRESS MAP The image data stored in GRAM corresponds to real pixel on display as shown below. S1 S2 S3 DB[17:12] DB[11:6] DB[5:0] G1 G2 S382 S383 S384 DB[17:12] DB[11:6] DB[5:0] (00h, 00h) (00h, 7Fh) GRAM G159 G160 (9Fh, 00h) (9Fh, 7Fh) Figure 4 : GRAM Address and Display Image [NOTE] The display condition of this figure is like this. SS = 0, BGR = 0, GS = 0. 25 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY INSTRUCTIONS OUTLINE S6D0144 uses 18bit bus architecture. To execute an instruction of the S6D0144, control information from external 18/16/9/8bit data is stored in Index Register (IR) and Control Register (CR) as described later to allow high-speed interface to high-performance microcomputer. The internal operation of S6D0144 is determined by the signals sent from microcomputer. These signals, which include the register selection signal (RS), the write/read signals (E/RWB for 68-system, WRB/RDB for 80-system), and the internal 16-bit data bus signals (IB15 to IB0), make up S6D0144 instructions. There are eight categories of instructions that - Specifies the index Reads the status Controls the display Controls power management Processes the graphics data Sets internal GRAM addresses Transfers data to and from the internal GRAM Sets grayscale level for the internal grayscale palette table Normally, instructions writing data are used the most frequently. So, the automatic update of internal GRAM address after each data write can lighten the microcomputer’s load. Because instructions are executed in 0 cycles, they can be written in succession. The 16bit instruction assignment varies with interface mode specified by IM. And you can see the assignment for each interface mode in SYSTEM INTERFACE section described later. 26 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY INSTRUCTION TABLE Table 17 : Instruction table 1 Reg.No R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 IR W 0 X X X X X X X X ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 SR R00h R 0 L7 L6 L5 L4 L3 L2 L1 L0 0 0 0 0 0 0 0 0 W 1 X X X X X X X X X X X X X X X 1 R 1 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 EPL (0) SM (0) GS (0) SS (0) X X X NL4 (1) NL3 (0) NL2 (1) NL1 (0) NL0 (0) R01h W 1 X X X DPL (0) R02h W 1 X X X X X X FL1 (0) FL0 (0) X X X FLD (0) X X X X R03h W 1 X X X BGR (0) X X MDT1 (0) MDT0 (0) X X I/D1 (1) I/D0 (1) AM (0) X X X R07h W 1 X X X PT1 (0) PT0 (0) X X SPT (0) X X GON (0) DTE (0) CL (0) REV (0) D1 (0) D0 (0) R08h W 1 X X X X FP3 (0) FP2 (0) FP1 (1) FP0 (0) X X X X BP3 (0) BP2 (0) BP1 (1) BP0 (0) R0Bh W 1 X X X X X X DIV1 (0) DIV0 (0) X X X X RTN3 (0) RTN2 (0) RTN1 (0) RTN0 (0) R0Ch W 1 X X X X X X X RM (0) X X DM1 (0) DM0 (0) X X RIM1 (0) RIM0 (0) R10h W 1 DSTB (0) X SAP2 (0) SAP1 (0) SAP0 (0) BT2 (0) BT1 (0) BT0 (0) DC2 (0) DC1 (0) DC0 (0) AP2 (0) AP1 (0) AP0 (0) SLP (0) STB (0) R11h W 1 VR1C (0) X X X X X VRP14 VRP13 VRP12 VRP11 VRP10 (0) (0) (0) (0) (0) R12h R13h R14h R21h VRN14 VRN13 VRN12 VRN11 VRN10 (0) (0) (0) (0) (0) W 1 X X X X X X X X W 1 X X X X VCMR (1) X X X R31h R32h R33h R34h R35h R36h R37h R38h R40h R42h R43h R44h R45h pin while pin while Blank period control 1 (R08H)/ BP3-0: Back porch setting FP3-0: Front porch setting Frame cycle control (R0BH)/ DIV1-0: division ratio of internal clock setting RTN3-0: set the 1-H period External interface control(R0CH) / RM: specify the interface for RAM access DM1-0: specify display operation mode RIM1-0: specify RGB-I/F mode Power control 1 (R10H) / SAP2-0: Adjust the amount of fixed current in the op Amp for the source driver BT2-0: Adjust scale factor of the step-up DC2-0: Select operating frequency in the step-up circuit AP2-0: Adjust the amount of fixed current in the op Amp for the power supply SLP: enters the sleep mode STB: enters the standby mode DSTB : enters the deep standby mode. Gamma control 1 (R11H)/ VR1C : Control step of amplitude positive and negative of 64-grayscale VRN14-10: Control amplitude (positive polarity) of 64-grayscale. VRP14-10: Control amplitude (negative polarity) of 64-grayscale. Power control 2 / SVC3-0:set VCI1 voltage VC2-0: set reference voltage of VREFS Power control 3 / VCMR : select VCOMH voltage adjusting method PON : Power circuit ON/OFF setting VRH3-0 : Set GVDD voltage Power control 4 / VCOMG : VCOML voltage level negative voltage setting VDV6-0 : COM output amplitude setting VCM6-0 : VCOMH voltage level setting SVC3 (0) SVC2 (0) SVC1 (0) SVC0 (0) X VC2 (0) VC1 (0) VC0 (0) X X X PON (0) VRH3 (0) VRH2 (0) VRH1 (0) VRH0 (0) VCM6 (0) VCM5 (0) VCM4 (0) VCM3 (0) VCM2 (0) VCM1 (0) VCM0 (0) AD6 (0) AD5 (0) AD4 (0) AD3 (0) AD2 (0) AD1 (0) AD0 (0) RAM address register / AD15-AD0 W 1 X VDV6 (0) VDV5 (0) VDV4 (0) VDV3 (0) VDV2 (0) VDV1 (0) VDV0 (0) W 1 AD15 (0) AD14 (0) AD13 (0) AD12 (0) AD11 (0) AD10 (0) AD9 (0) AD8 (0) VCOM G (0) AD7 (0) W 1 WD15 WD14 WD13 WD12 WD11 WD10 WD9 WD8 WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0 Write data to GRAM / WD15-WD0 R 1 RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 Read data from GRAM / RD15-RD0 W 1 X X X X X PKP12 PKP11 PKP10 (0) (0) (0) X X X X X PKP02 (0) PKP01 (0) PKP00 (0) Gamma control 2/ PKP12-10, PKP02-00: Micro adjustment setting W 1 X X X X X PKP32 PKP31 PKP30 (0) (0) (0) X X X X X PKP22 (0) PKP21 (0) PKP20 (0) Gamma control 2/ PKP32-30, PKP22-20: Micro adjustment setting W 1 X X X X X PKP52 PKP51 PKP50 (0) (0) (0) X X X X X PKP42 (0) PKP41 (0) PKP40 (0) Gamma control 2/ PKP52-50, PKP42-40: Micro adjustment setting W 1 X X X X X PRP12 PRP11 PRP10 (0) (0) (0) X X X X X PRP02 (0) PRP01 (0) PRP00 (0) Gamma control 2/ PRP12-10, PRP02-00: Gradient adjustment setting W 1 X X X X X PKN12 PKN11 PKN10 (0) (0) (0) X X X X X PKN02 (0) PKN01 (0) PKN00 (0) Gamma control 2/ PKN12-10, PKN2-0: Micro adjustment setting W 1 X X X X X PKN32 PKN31 PKN30 (0) (0) (0) X X X X X PKN22 (0) PKN21 (0) PKN20 (0) Gamma control 2/ PKN32-30, PKN22-20: Micro adjustment setting W 1 X X X X X PKN52 PKN51 PKN50 (0) (0) (0) X X X X X PKN42 (0) PKN41 (0) PKN40 (0) Gamma control 2/ PKN52-50, PKN42-40: Micro adjustment setting W 1 X X X X X PRN12 PRN11 PRN10 (0) (0) (0) X X X X X PRN02 PRN01 PRN00 (0) (0) (0) Gamma control 2/ PRN12-10, PRN02-00: Gradient adjustment setting W 1 X X X X VRN03 VRN02 VRN01 VRN00 (0) (0) (0) (0) X X X X VRP03 (0) VRP02 (0) VRP01 (0) VRP00 (0) Gamma control 3/ VRN03-00 : gamma amplitude setting(negative polarity) VRP03-00 : gamma amplitude setting(positive polarity) W 1 X X X X X X X X X X X SCN4 (0) SCN3 (0) SCN2 (0) SCN1 (0) SCN0 (0) Gate Scan Position / SCN4-0 : scan starting position of gate W 1 SE17 (1) SE16 (0) SE15 (0) SE14 (1) SE13 (1) SE12 (1) SE11 (1) SE10 (1) SS17 (0) SS16 (0) SS15 (0) SS14 (0) SS13 (0) SS12 (0) SS11 (0) SS10 (0) 1st screen driving position/ SE17-10 : 1st screen end position setting SS17-10 : 1st screen start position setting W 1 SE27 (1) SE26 (0) SE25 (0) SE24 (1) SE23 (1) SE22 (1) SE21 (1) SE20 (1) SS27 (0) SS26 (0) SS25 (0) SS24 (0) SS23 (0) SS22 (0) SS21 (0) SS20 (0) 2nd screen driving position/ SE27-20 : 2nd screen end position setting SS27-20 : 2nd screen start position setting W 1 HEA7 (0) HEA6 (1) HEA5 (1) HEA4 (1) HEA3 (1) HEA2 (1) HEA1 (1) HEA0 (1) HSA7 (0) HSA6 (0) HSA5 (0) HSA4 (0) HSA3 (0) HSA2 (0) HSA1 (0) HSA0 (0) Horizontal window address/ HEA7-0 : Horizontal window address end position HSA7-0 : Horizontal window address start position W 1 VEA7 (1) VEA6 (0) VEA5 (0) VEA4 (1) VEA3 (1) VEA2 (1) VEA1 (1) VEA0 (1) VSA7 (0) VSA6 (0) VSA5 (0) VSA4 (0) VSA3 (0) VSA2 (0) VSA1 (0) VSA0 (0) Vertical window address/ VEA7-0 : Vertical window address end position VSA7-0 : Vertical window address start position R22h R30h Register Name / Description Index / Sets the index register value Status read / Reads the internal status of the S6D0144 Start Oscillation(R00H) / Starts/Stops the oscillation circuit Device code read / Read 0144H Driver output control(R01H) / DPL: set polarity of DOTCLK using RGB interface. EPL: set polarity of ENABLE using RGB interface. SM: gate driver division drive control GS: gate driver shift direction SS: source driver shift direction NL4-0: number of driving lines LCD-Driving-waveform control (R02H)/ FL1-0 : Line/Frame inversion setting FLD : Interlace Mode Control Entry mode(R03H) / BGR: RGB swap control MDT2-1: Multiple Data Transfer I/D1-0: address counter Increment / Decrement control AM: horizontal / vertical RAM update Display control (R07H) / PT1-0: Non-display area source output control st nd SPT: 1 /2 partial display enable GON: gate-off to be VSS level DTE:DISPTMG to be VSS level CL: 8-color display mode enable REV: display area inversion drive D1-0: source output control 27 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY Table 18 : Instruction table 2 Reg.No R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R61h W 1 X X X X X X X X (0) X X X RADJ4 (1) RADJ3 (1) RADJ2 (0) RADJ1 (0) RADJ0 (0) R69h W 1 X X X X X X X X X X X NLDC3 NLDC2 NLDC1 NLDC0 (0) (1) (1) (0) NLPM (0) R70h W 1 X X X X X X X X SDT1 (0) SDT0 (0) X X X X EQ1 (0) EQ0 (0) Low power mode (LPM) setting register Sets Low power mode (NLPM) Sets DC/DC converter clock for AVDD at LPM (NLDC1-0) Sets DC/DC converter clock for VGH/L at LPM (NLDC3-2) Select capability of DC/DC converter for VGH/L (NLPDC) Sets source output pre-driving period Specifies equalize period (EQ 1-0) Specifies source output delay term (SDT1-0) R71h W 1 X X X X GNO1 (0) GNO0 (0) X X X X X X X X X X Sets the amount of non-overlap period of gate outputs R72h W 1 X X X X X X X X X X X X X X X SR(1) R73h W 1 X X X X X X X RB3h W 1 X X (0) X (0) X (0) X X (0) X (1) X X X RB4h W 1 X X X MTP_ SEL (1) RBDh R/W 1 X X X X X X X RBEh W 1 X X X X X X X 28 X X (0) MTP_ INIT (0) DISEN (0) X TEST_ TEST_ KEY7 KEY6 (0) (0) X X X X TEST_ TEST_ TEST_ TEST_ TEST_ KEY4 KEY3 KEY2 KEY1 KEY0 (0) (0) (0) (0) (0) DCR_ X X X X X X EX (0) (0) MTP_ MTP_ X X WRB X X X LOAD (1) (0) MTP_ MTP_ MTP_ MTP_ MTP_ MTP_ MTP_ DOUT6 DOUT5 DOUT4 DOUT3 DOUT2 DOUT1 DOUT0 X TEST_ KEY5 (0) X IM_SEL IM_3 X X X Register Name / Description Sets internal oscillator oscillation frequency (RADJ4-0) Software Reset Control Test Key to update MTP Value. ‘hA5 should be written to do it. DCR_EX Select Source of Pumping Clock MTP Control Registers DISEN : VGL/VCL Discharge Enable MTP Read Registers. Interface mode selection S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY INSTRUNCTION DESCRIPTIONS INDEX REGISTER (IR) The index instruction specifies indexes. It can set the register number in the range of 00000000b to 10111101b in binary form. However, do not access index registers and instruction bits those are not allocated in this document. R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 0 * * * * * * * * ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 STATUS READ The status read instruction allows read operation of the internal status of S6D0144. The status indicates the position of horizontal line currently being driven. R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R 0 L7 L6 L5 L4 L3 L2 L1 L0 0 0 0 0 0 0 0 0 SYSTEM CONTROL (R00h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X X X X X X X X X X X X X X 1 R 1 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 Issuing this instruction forces the internal oscillator to start oscillation. It can be used to restart the internal oscillator from the halt state in standby mode. After issuing this instruction, wait at least 10 ms for oscillation to stabilize before issuing the next instruction. (See the Standby Mode section.) If this register (00h) is read forcibly, “0144h” is read. 29 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY DRIVER OUTPUT CONTROL (R01h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X X DPL EPL SM GS SS X X X NL4 NL3 NL2 NL1 NL0 DPL Determine the active polarity of DOTCLK for using RGB interface. DPL Table 19 : DPL and DOTCLK polarity DOTCLK Description 0 (1) () Valid (Valid) 0 (1) () Invalid (Invalid) EPL Determine the active polarity of ENABLE for using RGB interface. EPL 30 Table 20 : EPL, ENABLE and RAM access ENABLE RAM Write RAM Address 0 (1) 0 (1) Valid (Valid) Updated (Updated) 0 (1) 1 (0) Invalid (Invalid) Hold (Hold) S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY SM Select the division drive method of the gate driver. When SM = 0, even/odd division is selected; SM = 1, upper/lower division drive is selected. Various connections between TFT panel and the IC can be supported with the combination of SM and GS bit. GS Set the order of Gate Clock generation. When GS = 0, G1 is output first and G160 is finally output. When GS = 1, G160 is output first and G1 is finally output (NL = 5’b10100). But in case of NL = 5’b00001, when GS = 0, G1 is output first and G8 is finally output, and when GS = 1, G8 is output first and G1 is finally output SM 0 0 1 1 GS 0 1 0 1 LCD LCD G2 G1 EVEN LCD G2 ODD LCD G1 EVEN G1 G1 ODD G159 EVEN G160 G159 G160 G160 G159 G2 G1 ODD ODD G159 EVEN G160 G159 G159 G2 G159 G2 G1 G160 G160 G159 G2 G2 G1 G160 G159 G2 G1 S6D0144 (Bottom View : BUMP is downside) S6D0144 (Bottom View : BUMP is downside) S6D0144 (Bottom View : BUMP is downside) S6D0144 (Bottom View : BUMP is downside) G1 -> G2 -> G3 -> ... -> G158 -> G159 -> G160 G160 -> G159 -> G158 -> ... -> G3 -> G2 -> G1 G1 -> G3 -> ... -> G159 -> G2 -> G4 -> ... -> G160 G160 -> G158 -> ... -> G2 -> G159 -> G157 -> ... -> G1 Figure 5 : Gate Clock Generation order selection using GS and SM (NL = 5’b10100, SCN = 5’b00000) SM 0 0 1 1 GS 0 1 0 1 LCD G2 LCD G1 EVEN G2 ODD LCD G1 EVEN LCD G1 G1 ODD G95 EVEN G96 G2 G96 G95 G95 G96 G1 G2 ODD ODD G96 G95 G95 G95 G2 EVEN G96 G1 G2 G96 G2 G96 G95 G1 G2 G96 G95 G1 S6D0144 (Bottom View : BUMP is downside) S6D0144 (Bottom View : BUMP is downside) S6D0144 (Bottom View : BUMP is downside) S6D0144 (Bottom View : BUMP is downside) G1 -> G2 -> G3 -> ... -> G94 -> G95 -> G96 G96 -> G95 -> G94 -> ... -> G3 -> G2 -> G1 G1 -> G3 -> ... -> G95 -> G2 -> G4 -> ... -> G96 G96 -> G94 -> ... -> G2 -> G95 -> G93 -> ... -> G1 Figure 6 : Gate Clock Generation order selection using GS and SM (NL = 5’b01100, SCN = 5’b00000) 31 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY SS Select the direction of the source driver channel in pixel unit. When user changes the value of SS, memory should be updated to apply the change. S382 S383 S384 DB[17:12] DB[11:6] DB[5:0] G1 G2 S1 S2 S3 DB[17:12] DB[11:6] DB[5:0] (00h, 00h) (00h, 7Fh) GRAM G159 G160 (9Fh, 00h) (9Fh, 7Fh) Figure 7 : Image mirroring using SS register (SS = “1”) [NOTE] The display condition of this figure is like this. SS = 1, BGR = 0, GS = 0. 32 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY NL Specify the number of horizontal lines to be driven. The number of the lines can be adjusted in units of eight. GRAM address mapping is independent of this setting. The set value should be higher than the panel size. NL[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 Table 21 : NL bit and Drive Duty (SCN = “00000”) Display Size Drive Line Gate Driver- Lines Used Reserved 384 X 8 dots 8 G1 to G8 384 X 16 dots 16 G1 to G16 384 X 24 dots 24 G1 to G24 384 X 32 dots 32 G1 to G32 384 X 40 dots 40 G1 to G40 384 X 48 dots 48 G1 to G48 384 X 56 dots 56 G1 to G56 384 X 64 dots 64 G1 to G64 384 X 72 dots 72 G1 to G72 384 X 80 dots 80 G1 to G80 384 X 88 dots 88 G1 to G88 384 X 96 dots 96 G1 to G96 384 X 104 dots 104 G1 to G104 384 X 112 dots 112 G1 to G112 384 X 120 dots 120 G1 to G120 384 X 128 dots 128 G1 to G128 384 X 136 dots 136 G1 to G136 384 X 144 dots 144 G1 to G144 384 X 152 dots 152 G1 to G152 384 X 160 dots 160 G1 to G160 [NOTE] A FP (front porch) and BP (back porch) period will be inserted as blanking period (All gates output VGL level) before / after the driver scan through all of the scans. 33 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY LCD INVERSION CONTROL (R02h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X X X X X FL1 FL0 X X X FLD X X X X F/L Set LCD inversion method as show below Table 22 : LCD inversion selection Description FL[1:0] 00 Frame Inversion 01 Line Inversion 10 No Inversion. Active with positive polarity (VCOM = Low) 11 No Inversion. Active with negative polarity (VCOM = High) For more detail information about inversion, refer to PANEL CONTROL INTERFACE described later. FLD Enables or disables 3-field interlaced scanning function like below. When you want to save power consumption, you’d better enable 3 field interfaced scanning function. FLD Table 23 : LCD interlaced scanning method control Description 0 1 field interlace (normal) 1 3 field interlace G1 G2 G3 G4 G5 TFT LCD G160 ( a : normal ) TFT LCD G1 G2 G3 G4 G5 G6 G7 G8 G9 G160 TFT LCD G158 TFT LCD ( b : 3-field interlaced scanning ) Figure 8 : Interlaced scanning methods 34 G159 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY ENTRY MODE (R03h) R/W RS W IB15 1 X IB14 X IB13 X IB12 IB11 BGR IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 X MDT 1 MDT 0 X X ID1 ID0 AM X X X X BGR When 18-bit data is written to GRAM through DB bus, RGB assignment can be changed. - BGR = 0 ; {DB[17:12], DB[11:6], DB[5:0]} is assigned to {R, G, B}. Actually the analog value that corresponds to DB[17:12] is output firstly at source output - BGR = 1 ; {DB[17:12], DB[11:6], DB[5:0]} is assigned to {B, G, R}. Actually the analog value that corresponds to DB[5:0] is output firstly at source output. MDT When user wants to transfer 260k color data on 8/16-bit parallel bus, MDT (Multiple Times Data Transfer mode control) register may be used for that. Table 24 : Multiple Data Transfer Mode Control IM[3:0] Description MDT[1:0] 0X X 10 11 Normal Data Transfer 8-bit 260k color data is transferred by 3-times Data Transfer. 16-bit 260k color data is transferred by 2-times Data Transfer. 8-bit 65k color data is transferred by 3-times Data Transfer. 16-bit 260k color data is transferred by 2-times Data Transfer. 1st transfer Input Data Instruction Bit (IB) 2nd transfer 3rd transfer DB17 DB16 DB15 DB14 DB13 DB12 DB17 DB16 DB15 DB14 DB13 DB12 DB17 DB16 DB15 DB14 DB13 DB12 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Figure 9 : 260k color data transfer on 8-bit parallel bus (MDT = 2’b10) 1st transfer Input Data Instruction Bit (IB) 2nd transfer 3rd transfer DB17 DB16 DB15 DB14 DB13 DB12 DB17 DB16 DB15 DB14 DB13 DB12 DB17 DB16 DB15 DB14 DB13 DB12 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Figure 10 : 65k color data transfer on 8-bit parallel bus by 3-times Data Transfer (MDT = 2’b11) 35 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY 1st transfer (Upper) Input Data Instruction Bit (IB) 2nd transfer (Lower) DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB17 DB16 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Figure 11 : 260k color data transfer on 16-bit parallel bus (MDT = 2’b10) 1st transfer (Upper) Input Data Instruction Bit (IB) 2nd transfer (Lower) DB2 DB1 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 Figure 12 : 260k color data transfer on 16-bit parallel bus (MDT = 2’b11) 36 B1 B0 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY ID When ID[1], ID[0] = 1, the address counter (AC) is automatically increased by 1 after the data is written to the GRAM. When ID[1], ID[0] = 0, the AC is automatically decreased by 1 after the data is written to the GRAM. The increment/decrement setting of the address counter using ID[1:0] is done independently for the horizontal address and vertical address. AM Set the automatic update method of the AC after the data is written to GRAM. When AM = “0”, the data is continuously written in horizontally. When AM = “1”, the data is continuously written vertically. When window addresses are specified, the GRAM in the window range can be written to according to the ID[1:0] and AM. Table 25 : Address Direction Setting ID[1:0] = “00” ID[1:0] = “01” ID[1:0] = “10” H: decrement H: increment H: decrement V: decrement V: decrement V: increment 0000h 0000h 0000h ID[1:0] = “11” H: increment V: increment 0000h AM=”0” Horizontal Update 9F7F 0000h 9F7Fh 0000h 9F7Fh 0000h 9F7Fh 0000h AM=”1” Vertical Update 9F7Fh 9F7Fh 9F7Fh 9F7Fh [NOTE] When window addresses have been set, the GRAM can only be written within the window. When AM or ID is set, the start address should be written accordingly prior to memory write. 37 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY DISPLAY CONTROL (R07h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X X PT1 PT0 X X SPT X X GON DTE CL REV D1 D0 PT Normalize the source outputs when non-displayed area of the partial display is driven. For details, see the Screen-division Driving Function section. You should note that the control with PT is not affected by REV. Table 26 : Non-Displayed Area Control Source Output for Non-display Area Gate Output for Non-display Area Positive Polarity Negative Polarity PT[1:0] 00 V63 V0 Normal Drive 01 V0 V63 Normal Drive 10 GND GND VGL 11 Hi-z Hi-z VGL [NOTE] In this table, GND means source driver’s outputs are short to VcomOUT level. SPT When SPT = “1”, the Split Screen Driving Function is performed. This function is not available when RGB interface is in use. For details, see “Split Screen Driving Function section” describe later. GON / DTE GON and DTE set gate output (G1 to G160) as following table. GON 0 1 38 Table 27 : Gate Clock Control DTE Gate output VCOMOUT X VGH Halt (VSS) 0 VGL Normal operation 1 VGH/VGL Normal operation S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY CL CL = 1 selects 8-color display mode. For details, see the section on 8-color display mode. Table 28 : Color Depth Control Color Depth CL 0 262,144 colors / 65,536 colors 1 8 colors REV Displays all character and graphics display sections with reversal when REV = 1. Since the grayscale level can be reversed, display of the same data is enabled on normally white and normally black panels. Table 29 : Source Output Control in operation REV Display Area GRAM data Positive Negative 0 6’b000000 : 6’h111111 V63 : V0 V0 : V63 1 6’b000000 : 6’h111111 V0 : V63 V63 : V0 PT[1:0] = ”00” Source output level Non-display area PT[1:0] = ”01” PT[1:0] = “10” PT[1:0] = “11” Positive Negative Positive Negative Positive Negative Positive Negative V63 V0 V0 V63 VSS VSS Hi-z Hi-z D Display is on when D[1] = “1” and off when D[1] = “0”. When off, the display data remains in the GRAM, and can be re-displayed instantly by setting D[1] = “1”. When D[1] is “0”, the display is off with the entire source outputs set to the VSS level. Because of this, the S6D0144 can control the charging current for the LCD with AC driving. Control the display on/off while control GON and DTE. For details, see the Instruction Set-Up Flow. When D[1:0] = “01”, the internal display of the S6D0144 is performed although the display is off. When D[1:0] = “00”, the internal display operation halts and the display is off. D[1:0] Table 30 : Source Output Control Source output internal operation 00 GND Halt 01 GND Operate 10 11 White on Normally White Panel Black on Normally Black Panel Display Operate Operate [NOTE] 1. Writing from MCU to GRAM is independent from D. 2. In sleep and standby mode, S6D0144 operates as D[1:0] = “00”. However, the register of D is not modified. 3. In this table, GND means source driver’s outputs are short to VcomOUT level. 39 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY BLANK PERIOD CONTROL 1 (R08h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X X X FP3 FP2 FP1 FP0 X X X X BP3 BP2 BP1 BP0 FP/BP Set the period of Blank Period, which is placed at the beginning and the end of a frame. FP[3:0] is for a Front Porch and BP[3:0] is for a Back Porch. When Front Porch and Back Porch are set, the settings should meet the following conditions. BP+FP ≤16 lines FP ≥2 lines BP ≥2 lines When S6D0144 operates in External Clock Operation mode, the Back Porch (BP) will start on the falling edge of the VSYNC signal and display operation begins just after the Back Porch period. The Front Porch (FP) will start when data of the number of lines specified by the NL has been displayed. During the period between the completion of the Front Porch and the next VSYNC signal, the display will remain blank. Table 31 : Blank Period Control with FP and BP FP[3:0] (BP[3:0]) Number of Raster Periods In Front (Back) Porch 40 0000 Reserved 0001 Reserved 0010 2 0011 3 0100 4 --- --- 1000 8 --- --- 1100 12 1101 13 1110 14 1111 Reserved S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY [NOTE] - In case of t1 > 1DOTCLK 1 Frame VSYNC >= 1H Back Porch t1 1H Front Porch HSYNC DOTCLK ENABLE DB[17:0] 1 DISP_CK FLM G[1] G[160] Figure 13 : BP & FP in External Clock Operation Mode (DM[0] = “1”) 1 Frame FLM 1 DISP_CK Back Porch + 1 G[1] G[160] Front Porch - 1 Figure 14 : BP & FP in Internal Clock Operation Mode (DM[0] = “0”) [NOTE] DISP_CK : OSCK_CK divided by DIV[1:0](DM = 2’b00) or DOTCLK divided by 8(DM = 2’b01 and RIM[1] = 1’b1) 41 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY FRAME CYCLE CONTROL (R0Bh) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X X X X X DIV1 DIV0 X X X X RTN3 RTN2 RTN1 RTN0 DIV Set the division ratio of clocks for internal operation. Internal operations are driven by clocks, which are frequency divided according to the value of this register. Frame frequency can be adjusted with this. When changing number of the drive cycle, adjust the frame frequency. Table 32 : Frame Frequency Control DIV[1:0] Division Ratio Internal operation clock frequency 00 1 fosc/1 01 2 fosc/2 10 4 fosc/4 11 8 fosc/8 [NOTE] fosc = R-C oscillation frequency. The clock which is divided by DIV is called as INCLK below Frame Frequency = f OSC Clock cycles per raster-row x division ratio x (Line+B) fOSC: R-C oscillation frequency Line: Number of raster-rows (NL bit) Clock cycles per raster-row: RTN bit Division ratio: DIV bit B: Blank period(Back porch + Front Porch) Figure 15 : Formula for the frame frequency RTN Set the 1H period. Table 33 : Clock Cycles per horizontal line 42 RTN[3:0] Clock Cycles per horizontal Line 0000 0001 --1110 1111 16 (INCLKs) 17 (INCLKs) --30 (INCLKs) 31 (INCLKs) [Hz] S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY EXTERNAL DISPLAY INTERFACE CONTROL (R0Ch) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X X X X X X RM X X DM1 DM0 X X RIM1 RIM0 RM Specify the interface for GRAM access as shown below. This register and DM register can be set independently. The display data can be written through System Interface by clearing this register while the RGB interface is used. RM Table 34 : RM and GRAM Access Interface GRAM Access Interface 0 System interface 1 RGB interface DM Specify the display operation mode. The interface can be set based on the bits of DM[1:0]. In Internal Clock Opeartion mode the source clock for display operation comes from internal oscillator while in External Clock Opeartion mode it comes from RGB interface(DOTCLK, VSYNC, HSYNC). DM[1:0] Table 35 : DM and Display Operation Mode Display operation mode 00 Internal clock operation 01 External clock operation 10 Reserved 11 Reserved 43 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY RIM Specify RGB interface mode when the RGB interface is used. This register is valid when RM is set to “1”. DM and this register should be set before proper display operation is performed through the RGB interface. RIM[1:0] 44 Table 36 : RIM and RGB Interface Mode RGB Interface mode 00 6-bit RGB interface (three transfers per pixel) 01 16-bit RGB interface (one transfer per pixel) 10 18-bit RGB interface (one transfer per pixel) 11 Reserved S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY POWER CONTROL 1 (R10h) R/W W RS IB15 1 DST B IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 X SAP 2 SAP 1 SAP 0 BT2 BT1 BT0 DC2 DC1 DC0 AP2 AP1 AP0 SLP STB DSTB When DSTB = 1, the S6D0144 enters the deep standby mode, where display operation completely stops, halting all the internal operations including the internal R-C oscillator and RVDD regulator. Further, no external clock pulses are supplied. For details, see the Standby Mode section. Any instructions can not be executed during the deep standby mode. SAP Adjust the slew-rate of the operational amplifier for the source driver. If higher SAP2-0 is set, LCD panel having higher resolution or higher frame frequency can be driven because the slew-rate of the operational amplifier is increased. But, these bits must be set as adequate value because the amount of fixed current of the operational amplifier is also adjusted. During non-display, when SAP2-0 = “000”, the current consumption can be reduced. Table 37 : Current and Slew Rate Control SAP[2:0] 000 Slew-Rate of Operational Amplifier Amount of Current in Operational Amplifier Operation of the operational amplifier halted. 001 Setting disabled Setting disabled 010 Slow or medium Small or medium 011 Medium Medium 100 Medium or fast Medium or large 101 Fast Large 110 Setting disabled Setting disabled 111 Setting disabled Setting disabled *To use SAP=001, please contact SEC engineer. 45 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY BT The output factor of step-up is switched. Adjust scale factor of the step-up circuit by the voltage used. When the step-up operating frequency is high, the driving ability of the step-up circuit and the display quality become high, but the current consumption is increased. Adjust the frequency considering the display quality and the current consumption. BT[2:0] Table 38 : Step-Up Control VGH Output VGL Output 000 Notes -(AVDDx2+VCI1) VGH = Vci1 X six times -(AVDDx2) VGH = Vci1 X six times 010 -(AVDD+VCI1) VGH = Vci1 X six times 011 -(AVDDx2+VCI1) VGH = Vci1 X five times -(AVDDx2) VGH = Vci1 X five times -(AVDD+VCI1) VGH = Vci1 X five times -(AVDDx2) VGH = Vci1 X four times -(AVDD+VCI1) VGH = Vci1 X four times 001 100 AVDD X 3 AVDD X 2 + VCI1 101 110 111 AVDD X 2 DC The operating frequency in the step-up circuit is selected. When the step-up operating frequency is high, the driving ability of the step-up circuit and the display quality become high, but the current consumption is increased. Adjust the frequency considering the display quality and the current consumption. DC[2:0] Table 39 : Step-Up Control Step-up Cycle in Step-up Circuit for AVDD, VCL VGH, VGL 000 DCCLK / 1 DCCLK / 2 001 DCCLK / 2 DCCLK / 2 010 DCCLK / 4 DCCLK / 2 011 DCCLK / 2 DCCLK / 8 100 DCCLK / 1 DCCLK / 4 101 DCCLK / 2 DCCLK / 4 110 DCCLK / 4 DCCLK / 4 111 DCCLK / 4 DCCLK / 8 [NOTE] DCCLK is asynchronous with Hoizontal Line Clock (as it has been called CL1). 46 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY AP The amount of fixed current in the operational amplifier for the power supply can be adjusted. When the amount of fixed current is large, the LCD driving ability and the display quality become high, but the current consumption is increased. Adjust the fixed current considering the display quality and the current consumption. During no display, when AP2-0 = “000”, the current consumption can be reduced by ending the operational amplifier and step-up circuit operation. Table 40 : Current Control AP[2:0] Amount of Current in Operational Amplifier 000 Operation of the operational amplifier and step-up circuit stops. 001 Small 010 Small or medium 011 Medium 100 Medium or large 101 Large 110 Setting Inhibited 111 Setting Inhibited SLP When SLP = 1, the S6D0144 enters the sleep mode, where the internal display operations are halted except for the R-C oscillator, thus reducing current consumption. Only the following instructions can be executed during the sleep mode. − Power control (BT2–0, DC3–0, AP2–0, SLP, STB, VC3-0, VRH3-0, VCOMG, VDV6-0, and VCM6-0 bits) During the sleep mode, the other GRAM data and instructions cannot be updated although they are retained and G1 to G160output is fixed to VSS level, and register set-up is protected (maintained). STB When STB = 1, the S6D0144 enters the standby mode, where display operation completely stops, halting all the internal operations including the internal R-C oscillator. Further, no external clock pulses are supplied. For details, see the Standby Mode section. Only the following instructions can be executed during the standby mode. − − Standby mode cancel(STB = “0”) Start oscillation Mode Normal Table 41 : Operation Mode Summary Operation Oscillator RVDD Active Active Active Sleep Inactive Active Active Standby Inactive Inactive Active Deep Standby Inactive Inactive Inactive 47 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY GAMMA CONTROL 1 (R11h) R/W W RS IB15 1 VR1 C IB14 X IB13 IB12 IB11 IB10 IB9 IB8 X VRN 14 VRN 13 VRN 12 VRN 11 VRN 10 IB7 X IB6 X IB5 IB4 IB3 IB2 IB1 IB0 X VRP 14 VRP 13 VRP 12 VRP 11 VRP 10 VR1C Control step of amplitude positive and negative of 64-grayscale. For details, see the amplitude Adjusting Circuit section. VRP1[4:0] Control amplitude positive polarity of 64-grayscale. For details, see the amplitude Adjusting Circuit section. VRN1[4:0] Control amplitude negative polarity of 64-grayscale. For details, see the amplitude Adjusting Circuit section. 48 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY POWER CONTROL 2 (R12h) POWER CONTROL 3 (R13h) POWER CONTROL 4 (R14h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 SVC 2 SVC 1 SVC 0 X VC2 VC1 VC0 W 1 X X X X X X X X SVC 3 W 1 X X X X VCM R X X X X X X PON VRH 3 VRH 2 VRH 1 VRH 0 W 1 X VDV 6 VDV 5 VDV 4 VDV 3 VDV 2 VDV 1 VDV 0 VCO MG VCM 6 VCM 5 VCM 4 VCM 3 VCM 2 VCM 1 VCM 0 SVC Adjust reference voltage of AVDD, VGH, VGL and VCL Table 42 : VCI1 voltage setting SVC[3:0] VCI1 [Without Load] 0000 2.10 V 0001 2.16 V 0010 2.22 V 0011 2.28 V 0100 2.34 V 0101 2.40 V 0110 2.46 V 0111 2.52 V 1000 2.58 V 1001 2.64 V 1010 2.70 V 1011 2.76 V 1100 Setting Disable 1101 Setting Disable 1110 Setting Disable 1111 Setting Disable [Note] VCI = VCI1, when VCI is lower than VCI1. 49 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY VC Adjust reference voltage of VREFS for GVDD. Table 43 : Internal Reference Voltage Control VC[2:0] Internal Reference Voltage VREFS 000 2.879 001 2.648 010 Setting disabled 011 2.389 100 Setting disabled 101 Setting disabled 110 2.101 111 2.879 [NOTE] Let VREFS < VCI. PON The operational amplifier ON/OFF signal. PON = 0 is to stop and PON = 1 to start operation. For further information about timing, please refer to the set up flow of power supply circuit. 50 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY VCMR Select VCOMH adjusting method. It is selected from external resistor setting (VCOMR) or internal electronic volume setting(VCM). Table 44 : VCOMH Control VCOMH voltage VCOMR Internal electronic volume VCMR 0 1 VRH Set the amplified factor of the GVDD voltage Table 45 : GVDD Control VRH[3:0] GVDD Voltage 0000 Setting disabled … Setting disabled 0111 Setting disabled 1000 VREFS x 1.38 1001 VREFS x 1.45 1010 VREFS x 1.53 1011 VREFS x 1.60 1100 VREFS x 1.68 1101 VREFS x 1.75 1110 VREFS x 1.83 1111 Setting disabled [NOTE] 1) Adjust the VRH so that the GVDD voltage is lower than 5.0 V. VCOMG When VCOMG = 1, VcomL voltage can output to negative voltage (-2.8V). When VCOMG = 0, VcomL voltage becomes VSS and stops the amplifier of the negative voltage. Therefore, low power consumption is accomplished. Also, When VCOMG = 0 and when Vcom is driven in A/C, set up of the VDV6-0 is invalid. In this case, adjustment of Vcom A/C amplitude must be adjusted VcomH with VCM6-0. 51 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY VDV Set the alternating amplitudes of Vcom at the Vcom alternating drive. These bits amplify Vcom 0.534 to 1.20 times the GVDD voltage. When the Vcom alternation is not driven, the settings become invalid. VDV[6:0] Table 46 : Vcom Amplitude Control Vcom Amplitude 0000000 Setting disable : Setting disable 0001111 Setting disable 0010000 GVDD X 0.534 0010001 GVDD X 0.540 : : 0010101 GVDD X 0.564 0010110 GVDD X 0.570 0010111 GVDD X 0.576 : : 1111110 GVDD X 1.194 1111111 GVDD X 1.200 [NOTE] Adjust the settings between GVDD and VDV0 to VDV6 so that the Vcom amplitudes are lower than 6.0 V. VcomL voltage should be : VCL+0.5 < VcomL <0.0V VCM Set the VcomH voltage (a high-level voltage at the Vcom alternating drive). These bits amplify the VcomH voltage 0.36 to 0.98 times the GVDD voltage. When VCOMR = 0, the adjustment of the internal volume stops, and VcomH can be adjusted from VcomR by an external resistor. VCM[6:0] 52 Table 47 : VcomH Control VcomH Voltage 0000000 GVDD X 0.360 0000001 GVDD X 0.365 0000010 GVDD X 0.370 : : 0001100 GVDD X 0.420 0001101 GVDD X 0.425 0001110 GVDD X 0.430 : : 1111011 GVDD X 0.975 1111100 GVDD X 0.980 1111101 Setting disable 1111110 Setting disable 1111111 Setting disable S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY GRAM ADDRESS SET (R21h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 AD You can write initial GRAM address into internal Address Counter (AC). When GRAM data is transferred through System Interface or RGB Interface, the AC is automatically updated according to AM and ID. This allows consecutive write without re-setting address in AC. But when GRAM data is read, the AC is not automatically updated. GRAM address setting is not allowed in Standby mode. Ensure that the address is set within the specified window area specified with VSA, VEA, HSA and HEA. When RGB interface is used (RM=”1”) to access GRAM, AD[16:0] will be set in the address counter at the falling edge of the VSYNC signal. And when one uses System Interface to access GRAM (RM = “0”), AD[16:0] will be set upon the execution of an instruction. Table 48 : GRAM Address Range AD[15:0] GRAM setting “0000H” to “007F”H “0100H” to “017F”H “0200H” to “027F”H “0300H” to “037F”H : : : “9C00H” to “9C7F”H “9D00H” to “9D7F”H “9E00H” to “9E7F”H “9F00H” to “9F7F”H Bitmap data for G1 Bitmap data for G2 Bitmap data for G3 Bitmap data for G4 : : : Bitmap data for G157 Bitmap data for G158 Bitmap data for G159 Bitmap data for G160 53 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY WRITE DATA TO GRAM (R22h) R/W RS W 1 RAM write data (WD17 ~ WB0). ※Interface mode controls the width of WD WDR Data on DB bus is expanded to 18-bits before being written to GRAM and the data determines grayscale level of S6D0144’s source output. Please keep in mind that the expansion format varies with interface mode. GRAM cannot be accessed in Standby mode. When data is written to GRAM via system interface while another data is being written to through RGB interface, please make sure that the two write operations does not conflict. Start RM = 0 Index Write (21h) Memory Address Write Index Write (22h) No Yes In the next address? Write Data Write Address is updated by 1 Write More ? Yes No End ( Memory Write ) Figure 16 : Memory Data Write Sequence 54 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY READ DATA FROM GRAM (R22h) RDR You may read data from GRAM using this register. When you make read operations, you can get a proper data on the second read operation as shown below. The first word you get just after address setting may be invalid. Start RM = 0 Index Write (21h) Memory Address Write Index Write (22h) Read Dummy Data Read Valid Data Read More ? Yes No End ( Memory Read ) Figure 17 : Memory Data Read Sequence 55 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY GAMMA CONTROL 2 (R30h to R37h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 PKP 11 PKP 10 IB7 IB6 IB5 X X X IB4 IB3 IB2 IB1 IB0 X X PKP 02 PKP 01 PKP 00 W 1 X X X X X PKP 12 W 1 X X X X X PKP 32 PKP 31 PKP 30 X X X X X PKP 22 PKP 21 PKP 20 W 1 X X X X X PKP 52 PKP 51 PKP 50 X X X X X PKP 42 PKP 41 PKP 40 W 1 X X X X X PRP 12 PRP 11 PRP 10 X X X X X PRP 02 PRP 01 PRP 00 W 1 X X X X X PKN 12 PKN 11 PKN 10 X X X X X PKN 02 PKN 01 PKN 00 W 1 X X X X X PKN 32 PKN 31 PKN 30 X X X X X PKN 22 PKN 21 PKN 20 W 1 X X X X X PKN 52 PKN 51 PKN 50 X X X X X PKN 42 PKN 41 PKN 40 W 1 X X X X X PRN 12 PRN 11 PRN 10 X X X X X PRN 02 PRN 01 PRN 00 PKP5[2:0], PKP4[2:0], PKP3[2:0], PKP2[2:0], PKP1[2:0], PKP0[2:0] The gamma fine adjustment registers for the positive polarity output PRP1[2:0], PRP0[2:0] The gradient adjustment registers for the positive polarity output PKN5[2:0], PKN4[2:0], PKN3[2:0], PKN2[2:0], PKN1[2:0], PKN0[2:0] The gamma fine adjustment registers for the negative polarity output PRN1[2:0], PRN0[2:0] The gradient adjustment registers for the negative polarity output For details, see the Gamma Adjustment Function. 56 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY GAMMA CONTROL 3 (R38h) R/W W RS 1 IB15 X IB14 X IB13 X IB12 IB11 IB10 IB9 IB8 X VRN 03 VRN 02 VRN 01 VRN 00 IB7 X IB6 X IB5 X IB4 IB3 IB2 IB1 IB0 X VRP 03 VRP 02 VRP 01 VRP 00 VRP0[3:0] Control amplitude positive polarity of 64-grayscale. For details, see the amplitude Adjusting Circuit section. VRN0[3:0] Control amplitude negative polarity of 64-grayscale. For details, see the amplitude Adjusting Circuit section. 57 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY GATE SCAN POSITION (R40h) R/W W RS 1 IB15 X IB14 IB13 X X IB12 X IB11 X IB10 IB9 X X IB8 X IB7 X IB6 X IB5 IB4 IB3 IB2 IB1 IB0 X SCN 4 SCN 3 SCN 2 SCN 1 SCN 0 SCN Set the scanning starting position of the gate driver. Table 49 : Gate Scan Position Control Start Position SCN[4:0] GS = 0 GS = 1 00000 G1 G160 00001 G9 G152 00010 G17 G144 --- --- --- 10001 G137 G24 10010 G145 G16 10011 G153 G8 [NOTE] Ensure that gate start position (SCN) + the number of LCD driver lines (NL) ≤ 160 when GS = 0, and that gate start position (SCN) - the number of LCD driver lines (NL) ≥ 0 when GS = 1 1 1 NL 1 33 NL NL 160 (A) SCN = 0, GS = 0 128 160 (B) SCN = 00100, GS = 0 Figure 18 : Gate Scan Position Control 58 (C) SCN = 00100, GS = 1 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY st 1 SCREEN DRIVING POSITION (R42h) nd 2 SCREEN DRIVING POSITION (R43h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 SE17 SE16 SE15 SE14 SE13 SE12 SE11 SE10 SS17 SS16 SS15 SS14 SS13 SS12 SS11 SS10 W 1 SE27 SE26 SE25 SE24 SE23 SE22 SE21 SE20 SS27 SS26 SS25 SS24 SS23 SS22 SS21 SS20 SS1 Specify the start position of the first screen to drive in a line unit. The LCD display starts from “SS1 + 1”. SE1 Specify the end position of the first screen to drive in a line unit. The LCD display is performed to the “SE1 + 1”. For instance, when SS[7:0] = “07h” and SE[7:0] = “10h” are set, the LCD display is performed from G8 to G17, and white or black display is performed according to PT for G1 to G7, G18 and others. Ensure that SS1[7:0] ≤ SE1[7:0] ≤”9F”h. For details, see “SPLIT SCREEN DRIVING FUNCTION” described later. SS2 Specify the start position of the second screen to display in a line unit. The LCD display starts from the “SS2 + 1”. The second screen is displayed when SPT = “1”. SE2 Specify the end position of the second screen to display in a line unit. The LCD display is performed to the “SE2 + 1”. For instance, when SS2[7:0] = “20h”, SE2[7:0] = “4Fh” and SPT = “1” are set, the LCD display is performed from G33 to G80. Ensure that “00h”≤SS1[7:0] ≤ SE1[7:0] ≤ SS2[7:0] ≤ SE2[7:0] ≤ ”9Fh”. For details, see “SPLIT SCREEN DRIVING FUNCTION” described later. 59 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY HORIZONTAL RAM ADDRESS POSITION (R44h) VERTICAL RAM ADDRESS POSITION (R45h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 HEA 7 HEA 6 HEA 5 HEA 4 HEA 3 HEA 2 HEA 1 HEA 0 HSA 7 HSA 6 HSA 5 HSA 4 HSA 3 HSA 2 HSA 1 HSA 0 W 1 VEA 7 VEA 6 VEA 5 VEA 4 VEA 3 VEA 2 VEA 1 VEA 0 VSA 7 VSA 6 VSA 5 VSA 4 VSA 3 VSA 2 VSA 1 VSA 0 VSA, VEA Specify the vertical start/end positions of a window for access to the specified partial memory (Window). Data can be written to GRAM from the address specified by VEA[7:0] to the address specified by VSA[7:0]. Note that the Window Addresses must be set before GRAM is updated. Ensure 00h ≤ VSA[7:0] ≤ VEA[7:0] ≤ ”9F”h. HSA, HEA Specify the horizontal start/end positions of a Window for access to the specified partial memory (Window). Data can be written to GRAM from the address specified by HSA[7:0] to the address specified by HEA[7:0]. Note that the Window Addresses must be set before GRAM is updated. Ensure 00h ≤ HSA[7:0] ≤ HEA[7:0] ≤ ”7F”h. HSA HEA 0000h 007Fh VSA Window Address Range -0 HSA HEA 7Fh VSA VEA 9Fh -0 Window VEA GRAM 9F00h 9F7Fh Figure 19 : Window Address Function [NOTE] Ensure that the Window addresses are within the GRAM address space. 60 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY ■ SPLIT SCREEN DRIVING FUNCTION S6D0144 can select and drive two screens at any position with the screen-driving position registers. Any of the two screens required for display are selectively driven and so you can reduce power consumption. st st For the 1 divided screen, start line and end line are specified by the 1 screen-driving position registers (SS1[7:0], nd nd SE1[7:0]). For the 2 division screen, start line and end line are specified by the 2 screen-driving position registers (SS2[7:0], SE2[7:0]). nd st The 2 screen control is effective when SPT is set to “1”. The total count of selection-driving lines for the 1 and 2 screens must correspond to the LCD-driving duty set value. G1 G7 Rm 1st screen 7 raster-row driving Non-Display Area G26 G42 JAN 1st 00:00 am 2nd screen 17 raster-row driving Non-Display Area Driving Raster-Row : NL[4:0] = 10100 (160 Lines) 1st Screen Setting : SS1[7:0] = 00h, SE1[7:0] = 06h 2nd Screen Setting : SS2[7:0] = 19h, SE2[7:0] = 29h, SPT = 1 Figure 20 : Split Screen Driving Function 61 nd 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY ■ Examples of Split Screen Driving Function Table 50 : Split Screen Driving Function with SPT = 0 Register Value Display Operation SE1[7:0] – SS1[7:0] = NL Full screen display Normally display from SS1[7:0] to SE1[7:0] SE1[7:0] – SS1[7:0] < NL Partial display Normally display from SS1[7:0] to SE1[7:0] Black or White display according to PT in remained area (GRAM data is not related at all) SE1[7:0] – SS1[7:0] > NL Setting disabled [NOTE] SS2[7:0] and SE2[7:0] are ignored Table 51 : Split Screen Driving Function with SPT = 1 Register Value Display Operation SE1[7:0] – SS1[7:0] + Full screen display SE2[7:0] – SS2[7:0] = NL Normally display from SS1[7:0] to SE2[7:0] Partial display Normally displays from SS1[7:0] to SE1[7:0] and from SS2[7:0] to SE1[7:0] – SS1[7:0] + SE2[7:0] SE2[7:0] – SS2[7:0] < NL Black or White display according to PT in remained area (RAM data is not related at all) SE1[7:0] – SS1[7:0] + Setting disabled SE2[7:0] – SS2[7:0] > NL 62 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY ■ PARTIAL DISPLAY SETUP FLOW Refer to the following flowchart to set up Partial Display. It is possible to determine the output levels of the driver in Non-Display Area (the area out of partial display), so one can select appropriate level depending on the panel’s condition. Full Screen Display PT[1:0] = "00" Set SS / SE Split Scree Drive Setup Wait 2 Frames Adjust according to necessity Set PT[1:0] properly Partial Display Set SS / SE Full Screen Drive Setup Full Screen Display Figure 21 : Partial Display Set Up Flow 63 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY ■ DATA UPDATE WITH WINDOW ADDRESS FUNCTION When data is written to the internal GRAM, the Window that is specified by the horizontal address register (HSA[7:0], HEA[7:0]) and the vertical address register (VSA[7:0], VEA[7:0]) can be updated consecutively. Data is written in the direction specified by AM (horizontally / vertically) and ID (incrementally / decrementally). When image data, etc. is being written, data can be written consecutively without thinking a data wrap by doing this. The Window must be specified to be within GRAM address area as described below and the start address for write must be set within the Window. HSA HEA 0000h 007Fh VSA 2020h 205Fh 7F20h 7F5Fh [NOTE] VSA = 20h, VEA = 7Fh HSA = 20h, HEA = 5Fh AM = 0, ID[1:0] = 11b VEA GRAM 9F00h 9F7Fh Figure 22 : Example of Data Update with Window Address Function 64 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY OSCILLATOR CONTROL (R61h) R/W RS W 1 IB15 X IB14 X IB13 X IB12 X IB11 IB10 X X IB9 X IB8 X IB7 X IB6 X IB5 IB4 IB3 IB2 IB1 IB0 X RAD J4 RAD J3 RAD J2 RAD J1 RAD J0 RADJ Select the oscillation frequency of internal oscillator. Table 52 : RADJ and Internal oscillator oscillation frequency RADJ[4:0] Oscillation Speed 00000 Setting disabled : Setting disabled 10000 Setting disabled 10001 x 0.768 10010 X 0.795 10011 x 0.823 10100 x 0.853 10101 x 0.885 10110 x 0.921 10111 x 0.958 11000 x 1.000 11001 x 1.045 11010 x 1.095 11011 x 1.148 11100 x 1.210 11101 x 1.276 11110 Setting disabled 11111 Setting disabled Min. Default Max. [Note] Setting example)If the default oscillation frequency is 240kHz and the register setting of RADJ[4:0] is 10001, internal oscillator oscillation frequency is 240kHz x 0.768 =184kHz. 65 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY DC/DC CONVERT LOW POWER MODE SETTING (R69h) R/W W RS 1 IB15 0 IB14 IB13 0 0 IB12 0 IB11 0 IB10 0 IB9 0 IB8 0 IB7 0 IB6 0 IB5 IB4 IB3 IB2 IB1 IB0 0 NLD C3 NLD C2 NLD C1 NLD C0 NLP M NLPM Set DC/DC converter to the Low power mode. Table 53 : VGH,VGL DC/DC converter operation mode NLPM 0 1 Operation mode Normal operation mode Low power mode NLDC Set the operation clock speed of each DC/DC converter circuit as following table while the low power mode. These setting are valid in NLPM=1. Table 54 : AVDD DC/DC converter operation while low power mode NLDC[1:0] AVDD, VCL DC/DC converter operation clock 00 01 10 11 DCCLK/1 DCCLK/2 DCCLK/4 DCCLK/8 Table 55 : VGH DC/DC converter operation while low power mode 66 NLDC[3:2] VGH, VGL DC/DC converter operation clock 00 01 10 11 DCCLK/2 DCCLK/4 DCCLK/8 DCCLK/16 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY SOURCE DRIVER PRE-DRIVING PERIOD SETTING (R70h) R/W W RS 1 IB15 X IB14 X IB13 X IB12 X IB11 X IB10 X IB9 X IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 X SDT 1 SDT 0 X X X X EQ1 EQ0 The S6D0144 generates the TFT-LCD drive timing inside. The TFT-LCD panel is driven at the timing of one line display period(1H) generated based on RTN[3:0](R0Bh) setting. EQ EQ period is sustained for the number of clock cycle that is set in EQ1-0. When VcomL<0V, use AVDD-VcomL<6V or set these bits as “00” for preventing the abnormal function. EQ 00 01 10 11 [NOTE] Table 56 : Equalization Control EQ Period Internal Operation (synchronized with internal clock) No EQ 1 DISP_CK 2 DISP_CKs 3 DISP_CKs DISP_CK : OSCK_CK divided by DIV[1:0](DM = 2’b00) or DOTCLK divided by 8(DM = 2’b01 and RIM[1] = 1’b1) f(EQ) + f(SDT) + f(GNO) < 15 DISP_CKs SDT Set delay amount from 1H start timing to source output. Table 57 : Source Output Delay Control [NOTE] SDT Delay Amount of the Source Output 00 01 10 11 1 DISP_CK 2 DISP_CKs 3 DISP_CKs 4 DISP_CK s DISP_CK : OSCK_CK divided by DIV[1:0](DM = 2’b00) or DOTCLK divided by 8(DM = 2’b01 and RIM[1] = 1’b1) f(EQ) + f(SDT) + f(GNO) < 15 DISP_CKs For detail, refer to “PANEL CONTROL INTERFACE TIMING DIAGRAMS” described later. 67 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY GATE OUTPUT PERIOD CONTROL (R71h) R/W W RS 1 IB15 X IB14 X IB13 X IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 X GNO 1 GNO 0 X X X X X X X X X X GNO Control the amount of non-overlap period between gate outputs. Table 58 : Non-Overlap Period Control [NOTE] 68 GNO Non-Overlap Period 00 01 10 11 2 DISP_CKs 4 DISP_CKs 6 DISP_CKs 8 DISP_CK s DISP_CK : OSCK_CK divided by DIV[1:0](DM = 2’b00) or DOTCLK divided by 8(DM = 2’b01 and RIM[1] = 1’b1) f(EQ) + f(SDT) + f(GNO) < 15 DISP_CKs S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY SOFTWARE RESET CONTROL (R72h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X X X X X X X X X X X X X X SR SR User can reset the internal status of S6D0144 by setting this register to “0”. This register is automatically set to “1” after about 100ns. 69 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY TEST_KEY (R73h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 W 1 X X X X X X X X IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 TEST_KEY[7:0] TEST_KEY When you want to update MTP data, “A5” should be written to this register. And you should write different value for MTP data not to be corrupted. 70 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY PUMPING CLOCK SOURCE SELECTION (RB3h) R/W W RS 1 IB15 X IB14 X IB13 X IB12 X IB11 X IB10 X IB9 X IB8 X IB7 X IB6 X IB5 IB4 IB3 IB2 IB1 IB0 X DCR _EX X X X X DCR_EX Select the source of pumping clock Table 23 : Pumping Clock Control DCR_EX Source of the pumping clock 0 1 Internal Oscillator Clock External DOTCLK 71 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY MTP CONTROL (RB4h) R/W W RS IB15 1 X IB14 X IB13 IB12 X MTP _SEL IB11 X IB10 X IB9 X IB8 MTP _INIT IB7 X IB6 X IB5 X IB4 MTP_ WRB MTP_LOAD User can load MTP data into internal register with writing “1” to this register before reading. MTP_WRB User can write MTP data writing “0” to this register. MTP_INIT User can initialize MTP data writing “1” to this register and writing “0” to MTP_WRB register MTP_SEL User can use MTP data to control VCOMH. Table 24 : VCOMH Control 72 MTP_SEL VCOMH Control Data 0 1 VCM Register MTP data IB3 X IB2 X IB1 X IB0 MTP_ LOAD S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY Start Start RESET Display On after a RESET Discharge Mode Set (RBDh DISEN= ”1") Enter Standby Mode (R10h STB = "1" ) Find Desired MTP value with RB4h MTP_SEL = "0" Wait 1ms or more Read MTP_DOUT Bad Good = "00" != "00" Supply MTPG, MTPD ( MTPG = 19V), MTPD = 0V) Erase Flow Set Test Key (R73h TEST_KEY = "0xA5" ) Discharge Mode Set (RBDh DISEN= ”1") Enable Initialization (RB4h MTP_INIT = "1" ) Enter Standby Mode (R10h STB = "1" ) Wait 1ms or more Wait 1ms or more Enable MTP Write (RB4h MTP_WRB = "0" ) Supply MTPG, MTPD ( MTPG = 0V), MTPD = 16V) Wait 100ms or more Disable MTP Write (RB4h MTP_WRB = "1" ) SEQ_A Set Test Key (R73h TEST_KEY = "0xA5" ) Cut Off MTPG, MTPD ( MTPG = MTPD = floating ) Set Desired MTP Value RESET SEQ_A End End ( A: MTP Erease & Initialization ) ( B: MTP Program ) Figure 25 : MTP Initializae, Erase & Program Flow of S6D0144 73 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY MTP DATA READ (RBDh) R/W RS R/W IB15 1 X IB14 IB13 X X IB12 X IB11 X IB10 X IB9 IB8 IB7 X DIS EN X IB6 IB5 IB4 IB3 IB2 MTP_DOUT[6:0] DISEN Battery off detection discharge circuit and standby mode discharge circuit operation setting register. Table 59 : Discharge Circuit Operation DISEN VGL/VCL discharge circuit operation 0 1 Discharge circuit operation stop Discharge circuit operating MTP_DOUT MTP data read using MTP_READ reigister. Start MTP Load Enable (MTP_LOAD = "1") Wait 1us or more Read MTP_DOUT End Figure 26 : MTP Read Flow of S6D0144 74 IB1 IB0 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY INTERFACE MODE SELECTION (RBEh) R/W W RS 1 IB15 X IB14 X IB13 X IB12 X IB11 X IB10 X IB9 X IB8 X IB7 X IB6 X IB5 IB4 IB3 IB2 IB1 IB0 X IM_ SEL IM_3 X X X IM_SEL IM_SEL register selects interface mode. Interface mode is selected by external pins(IM[3:0]) when the value of IM_SEL is 0 and interface mode is selected by internal register(IM_3) and external pins(IM[2:0]) when the value of IM_SEL is 1. In SPI mode, the use of IM_SEL is prohibited. The initial value of IM_SEL is 0. Table 60 : Interface mode selection IM_SEL Interface mode 0 1 IM[3:0] {IM_3, IM[2:0]} IM_3 IM_3 is only applied to the interface mode if IM_SEL is set to 1. The initial value of IM_3 is 0.. 75 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY RESET FUNCTION The S6D0144 is internally initialized by RESET input. The reset input must be held for at least 20us. Don’t access the GRAM or initially set the instructions until the R-C oscillation frequency is stable after power has been supplied (10 ms). Instruction Set Initialization All Registers in S6D0144 are initialized when RESET is asserted. GRAM Data Initialization GRAM is not automatically initialized by RESET input so it must be initialized by software while display is off(D = 00). Output Pin Initialization 1. LCD driver output pins (Source output) : Output VSS level (Gate output) : Output VGH level 76 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY POWER CONTROL POWER SUPPLY CIRCUIT The following figure shows a configuration of the voltage generation circuit for S6D0144. The step-up circuits consist of step-up circuits 1 to 3. Step-up circuit1 doubles the voltage supplied to VCI1, and that voltage is X2, X2.5, X3 in step-up circuit2. Step-up circuit 3 reverses the VCI1 level with reference to VSS and generates the VCL level. These step-up circuits generate power supplies AVDD, GVDD, VGH, VGL, and VCOM. Reference voltages GVDD, VCOM, and VGL for the grayscale voltage are amplified in amplification circuits 1 and 2 from the internal-voltage adjustment circuit or the REGP or REGN voltage, and generate each level depending on that voltage. Connect VCOM to the TFT panel. VCI 1uF Internal Referece Generation VCI Generation Circuit GVDD Adjust VCI1 1uF 1uF C11+ C11- 1uF DC/DC converter1 VREG1 amplifier GVDD AVDD VCOMR C21+ C22+ DC/DC converter2 C220.22uF ~ 1uF 0.22uF ~ 1uF 0.22uF ~ 1uF VCOM Adjust Note1) VCOMR VCOMH amplifier VCOMH 0.22uF~1uF VCOMRb C210.22uF ~ 1uF VGH VCOML amplifier VGL 0.22uF~1uF VCOML 0.22uF~1uF C23+ 1uF C23- DC/DC converter3 NVM MTPG/D VCL 1uF Note1) When VCOMH is externally adjusted, attach these registor. The total resistance should be higher than 100 kilohm. Figure 27 : Configuration of the Internal Power-Supply Circuit 77 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY PATTERN DIAGRAMS FOR VOLTAGE SETTING The following figure shows a pattern diagram for the voltage setting and an example of waveforms. Figure 28 : Pattern diagram and an example of waveforms 78 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY SETUP FLOW OF POWER SUPPLY Apply the power in a sequence as shown in the following figure. The stable time of the oscillation circuit, step-up circuit, and operational amplifier depend on the external resistor or capacitance. Power Supply (Vdd on) 90% VDD3 Min. 1ms RESETB 10% VCI Note : VCI (analog power) have to get more than 90% level of VCI before the analog circuit controlling. Power-on reset and display off Bits for display off. DTE="0" D1-0="00" GON="0" PON="0" Bits for display on: DTE="1", D1-0="11", GON="1" Normal Display 10ms or more (Stable time of the oscillation circuit) Issues instructions for power supply setting (1) 100ms or more (Stable times of step-up circuit) Bits for power-supply initial setting: SVC3-0,VC2-0, VRH3-0 VCM6-0, VDV6-0, VRN4-0,VRP4-0 (setting of the sourcedriver grayscale voltage) Issues instruction for power supply setting (2) Bits for power-supply operation start setting: BT2-0,DC2-0,AP2-0 Issues instruction for power supply setting (3) Bits for operational amplifier operation start PON=1 Display off sequence* Bits for display off: DTE="0", D1-0="00", GON="0" Display off Instruction for power supply setting Bits for power supply stop setting : AP2-0 for operational amplifier, DC2-0 for step-up circuit Power supply (Vdd off) Power-off sequence 50ms or more (Stable time of the operational amplifier) Issues instruction for other mode setting VDD3 90% Min. 1ms RESETB Display-on Sequence* 10% VCI Diplay on Bits for display on: DTE="1", D1-0="11", GON="1" Figure 29 : Set up Flow of Power Supply 79 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY VOLTAGE REGULATION FUNCTION The S6D0144 have internal voltage regulator. Voltage regulation function is controlled by DSTB signal. If DSTB = “1”, voltage regulation is stopped. DSTB = “0” enables internal voltage regulation function. By use of this function, internal logic circuit damage can be prohibited. Furthermore, power consumption also is obtained. Detailed function description and application setup is described in the following diagram. Internal VDD Level Shifter INPUT GND VDD3 (External Power) Range: 1.65~3.3V VCI Range: 2.5~3.3V DSTB VOLTAGE REGULATOR RVDD VDD Internal VDD (1.5V) Figure 30 : Voltage regulation function 80 INTERNAL LOGIC S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY VCOM SETTING The S6D0144 has 3 kind of VCOM amplitude adjusting method. It selects from external resistor setting, internal electronic volume setting, or MTP programmed setting. . Figure 31 : VCOMH control function 81 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY INTERFACE SPECIFICATION S6D0144 incorporates nine System Interfaces which are used to set instructions, and an RGB interface that is used to display motion pictures. Selecting one of these interfaces to match the screen data (motion picture or still picture) enables efficient transfer of data for display. The External Clock Operation mode that uses RGB interface allows flicker-free screen update. In this mode, the synchronization signals (VSYNC, HSYNC, and DOTCLK) are available for display operation. The data for display (DB[17:0]) is written according to the status of ENABLE in synchronization with VSYNC, HSYNC, and DOTCLK. In addition, using Window Address function enables rewriting only to the internal GRAM area to display motion pictures. Using this function also enables simultaneously display of motion picture and the GRAM data that was written earlier. HOSTs S6D0144 CSB RS E_WRB RWB_RDB DB CPU Interface 18/16/9/8 Serial Peripheral Interface (CSB) (E_WRB) SDI SDO RGB Interface VSYNC HSYNC ENABLE DOTCLK (DB) System Interface RGB Interface 18/16/6 Figure 32 : System Interface and RGB Interface 82 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY SYSTEM INTERFACE S6D0144 has nine System Interfaces as show below. No 1 2 3 4 5 6 7 8 9 Table 61 : System Interfaces of S6D0144 Description 68x-System 18-bit bus interface 68x-System 16-bit bus interface 68x-System 9-bit bus interface 68x-System 8-bit bus interface 80x-System 18-bit bus interface 80x-System 16-bit bus interface 80x-System 9-bit bus interface 80x-System 8-bit bus interface SPI (Serial Peripheral Interface) In order to select one of them you should set IM[3:0] properly. For detail, see “PIN DESCRIPTION” described earlier. 83 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY 68-18BIT CPU INTERFACE Bit Assignment Input Data DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Instruction Bit (IB) IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 Figure 33 : Bit Assignment of Instructions on 68-18bit CPU Interface Input Data Instruction Bit (IB) DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 * 262,144 color display is possible using the 18-bit system interface Figure 34 : Bit Assignment of GRAM Data on 68-18bit CPU Interface Timing Diagram There are 4 timing conditions for 68 18-bit CPU interface, which are index write timing condition, data write timing condition, data read timing condition and status read timing condition. IM[3:0] 68x-18/16bit CSB RS E RWB DB index data Index Write Data Write data status Data Read Status Read Figure 35 : Timing Diagram of 68-18bit CPU Interface 84 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY 68-16BIT CPU INTERFACE Bit Assignment Input Data DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 Instruction Bit (IB) IB15 IB14 IB13 IB12 IB11 IB10 IB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 Figure 36 : Bit Assignment of Instructions on 68-16bit CPU Interface Input Data GRAM Data DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 R5 R4 R3 R2 R1 R0 G5 G4 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 * 65,538 color display is possible using the 16-bit system interface Figure 37 : Bit Assignment of GRAM Data on 68-16bit CPU Interface Timing Diagram There are 4 timing conditions for 68-16bit CPU interface, which are index write timing condition, data write timing condition, data read timing condition and status read timing condition. IM[3:0] 68x-18/16bit CSB RS E RWB DB index data Index Write Data Write data status Data Read Status Read Figure 38 : Timing Diagram of 68-16bit CPU Interface 85 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY 68-9BIT CPU INTERFACE Bit Assignment 1st transfer (Upper) Input Data 2nd transfer (Lower) DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 Instruction Bit (IB) IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 Figure 39 : Bit Assignment of Instructions on 68-9bit CPU Interface 1st transfer (Upper) Input Data Instruction Bit (IB) 2nd transfer (Lower) DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 * 262,144 color display is possible using the 9-bit system interface Figure 40 : Bit Assignment of GRAM Data on 68-9bit CPU Interface Timing Diagram There are 4 timing conditions for 68-9bit CPU interface, which are index write timing condition, data write timing condition, data read timing condition and status read timing condition. In this mode, 16-bit instructions and GRAM data are divided into two half words and the transfer starts from the upper half word. IM[3:0] 68x-9/8bit CSB RS E RWB DB index upper data Index Write lower data Data Write upper data lower data Data Read Figure 41 : Timing Diagram of 68-9bit CPU Interface 86 upper status Status Read lower status S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY 68-8BIT CPU INTERFACE Bit Assignment Input Data 1st transfer (Upper) 2nd transfer (Lower) DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 Instruction Bit (IB) IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 Figure 42 : Bit Assignment of Instructions on 68-8bit CPU Interface Input Data GRAM Data 1st transfer (Upper) 2nd transfer (Lower) DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 * 65,538 color display is possible using the 8-bit system interface (MDT[1] = 0) Figure 43 : Bit Assignment of GRAM Data on 68-8bit CPU Interface Timing Diagram There are 4 timing conditions for 68-8bit CPU interface, which are index write timing condition, data write timing condition, data read timing condition and status read timing condition. In this mode, 16-bit instructions and GRAM data are divided into two half words and the transfer starts from the upper half word. IM[3:0] 68x-9/8bit CSB RS E RWB DB index upper data Index Write lower data Data Write upper data lower data Data Read upper status lower status Status Read Figure 44 : Timing Diagram of 68-8bit CPU Interface 87 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY 80-18BIT CPU INTERFACE Bit Assignment Input Data DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Instruction Bit (IB) IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 Figure 45 : Bit Assignment of Instructions on 80-18bit CPU Interface Input Data Instruction Bit (IB) DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 * 262,144 color display is possible using the 18-bit system interface Figure 46 : Bit Assignment of GRAM Data on 80-18bit CPU Interface Timing Diagram There are 4 timing conditions for 80 18-bit CPU interface, which are index write timing condition, data write timing condition, data read timing condition and status read timing condition. IM[3:0] 80x-18/16bit CSB RS WRB RDB DB index data Index Write Data Write data Data Read status Status Read Figure 47 : Timing Diagram of 80-18bit CPU Interface 88 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY 80-16BIT CPU INTERFACE Bit Assignment Input Data DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 Instruction Bit (IB) IB15 IB14 IB13 IB12 IB11 IB10 IB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 Figure 48 : Bit Assignment of Instructions on 80-16bit CPU Interface Input Data GRAM Data DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 R5 R4 R3 R2 R1 R0 G5 G4 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 * 65,538 color display is possible using the 16-bit system interface Figure 49 : Bit Assignment of GRAM Data on 80-16bit CPU Interface Timing Diagram There are 4 timing conditions for 80-16bit CPU interface, which are index write timing condition, data write timing condition, data read timing condition and status read timing condition. IM[3:0] 80x-18/16bit CSB RS WRB RDB DB index data Index Write Data Write data Data Read status Status Read Figure 50 : Timing Diagram of 80-16bit CPU Interface 89 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY 80-9BIT CPU INTERFACE Bit Assignment 1st transfer (Upper) Input Data 2nd transfer (Lower) DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 Instruction Bit (IB) IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 Figure 51 : Bit Assignment of Instructions on 80-9bit CPU Interface 1st transfer (Upper) Input Data Instruction Bit (IB) 2nd transfer (Lower) DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 * 262,144 color display is possible using the 9-bit system interface Figure 52 : Bit Assignment of GRAM Data on 80-9bit CPU Interface Timing Diagram There are 4 timing conditions for 80-9bit CPU interface, which are index write timing condition, data write timing condition, data read timing condition and status read timing condition. In this mode, 16-bit instructions and GRAM data are divided into two half words and the transfer starts from the upper half word. IM[3:0] 80x-9/8bit CSB RS WRB RDB DB index upper data Index Write lower data Data Write upper data lower data Data Read Figure 53 : Timing Diagram of 80-9bit CPU Interface 90 upper status lower status Status Read S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY 80-8BIT CPU INTERFACE Bit Assignment Input Data 1st transfer (Upper) 2nd transfer (Lower) DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 Instruction Bit (IB) IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 Figure 54 : Bit Assignment of Instructions on 80-8bit CPU Interface Input Data GRAM Data 1st transfer (Upper) 2nd transfer (Lower) DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 * 65,538 color display is possible using the 8-bit system interface (MDT[1] = 0) Figure 55 : Bit Assignment of GRAM Data on 80-8bit CPU Interface Timing Diagram There are 4 timing conditions for 80-8bit CPU interface, which are index write timing condition, data write timing condition, data read timing condition and status read timing condition. In this mode, 16-bit instructions and GRAM data are divided into two half words and the transfer starts from the upper half word. IM[3:0] 80x-9/8bit CSB RS WRB RDB DB index upper data Index Write lower data Data Write upper data lower data Data Read upper status lower status Status Read Figure 56 : Timing Diagram of 80-8bit CPU Interface 91 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY SERIAL PERIPHERAL INTERFACE Setting IM[3:0] properly allows standard clock-synchronized serial data transfer (SPI ; Serial Peripheral Interface), using CSB (chip select), SCL (serial transfer clock), SDI (serial input data) and SDO (serial output data). For the serial interface, IM[0] is used as ID. S6D0144 initiates serial data transfer by transferring the start byte at the falling edge of CSB input. It ends serial data transfer at the rising edge of CSB input. S6D0144 is selected when the 6-bit chip address in the start byte transferred by the transmitting device matches the 6-bit device identification code assigned to S6D0144. ID is the least significant bit of the device identification code. S6D0144, when selected, receives the subsequent data string. Two different chip addresses must be assigned to a single S6D0144 because the seventh bit of the start byte is used as a register select bit (RS): that is, when RS = “0”, data can be written to the index register or status can be read, and when RS = “1”, an instruction can be issued or data can be written to or read from GRAM. Read or write is determined according to the eighth bit of the start byte (R/WB bit). The data is written (receives) when the R/WB bit is “0”, and is read (transmits) when the R/WB bit is “1”. After receiving the start byte, S6D0144 receives or transmits the subsequent data. The data is transferred with the MSB first. All S6D0144 instructions are 16 bits, so two bytes are received with the MSB first (DB15 to 0), and then the instruction is internally executed. Five bytes of GRAM data read just after the start byte are invalid. S6D0144 starts to read correct GRAM data from the sixth byte. Likewise, it starts to read correct register/status from the second byte. Table 62 : Start Byte Format Transfer Bit st nd 1 2 rd 3 th 4 th th 5 6 Device Identification code Start byte format 0 1 1 1 th 7 RS 0 ID [NOTE] The IM[0] pin is used as ID Table 63 : RS and RWB Bit Function 92 RS bit RWB bit Function 0 0 Set index register 0 1 Read status 1 0 Writes instruction or RAM data 1 1 Reads instruction or RAM data th 8 RWB S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY Bit Assignment Input Data D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Instruction Bit (IB) IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 Figure 57 : Bit Assignment of Instructions on SPI Input Data GRAM Data D15 D14 D13 D12 D11 D10 D9 D8 R5 G5 G4 R4 R3 R2 R1 R0 G3 D7 D6 D5 D4 D3 D2 D1 D0 G2 G1 G0 B5 B4 B3 B2 B1 B0 Figure 58 : Bit Assignment of GRAM Data on SPI 93 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY Timing Diagrams Transfer Start CSB 1 Transfer End 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ID RS RW d15 SCL SDI d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 Device ID Start Byte Register, GRAM Write Data Figure 59 : Basic Timing Diagram of Data Transfer through SPI CSB SCL SDI I D start byte d d d d d d d d d d d d d d d d 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 5 4 3 2 1 0 d d d d d d d d d d d d d d d d 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 5 4 3 2 1 0 1st Data 2nd Data Figure 60 : Timing Diagram of Consecutive Data-Write through SPI CSB SCL SDI I R D S d d d d d d d d 7 6 5 4 3 2 1 0 SDO start byte 1 dummy byte d d d d d d d d 7 6 5 4 3 2 1 0 Read Data Figure 61 : Timing Diagram of Register / Status Read through SPI 94 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY CSB SCL SDI I D d d d d d d d d 1 1 1 1 1 1 9 8 5 4 3 2 1 0 SDO start byte 5 dummy bytes d d d d d d d d 7 6 5 4 3 2 1 0 Read Data Figure 62 : Timing Diagram of GRAM-Data Read through SPI 95 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY RGB INTERFACE MOTION PICTURE DISPLAY S6D0144 incorporates RGB interface to display motion pictures and GRAM to store data for display. To display motion pictures, S6D0144 has the following features. - Only motion picture area can be transferred by the Window Address function. - Only motion picture area to be rewritten can be transferred selectively. - Reducing the amount of data transferred enables reduce the power consumption of the whole system. - Still picture area, such as an icon, can be updated while displaying motion pictures combining with the system interface (for details, refer to “GRAM ACCESS VIA RGB INTERFACE AND SPI” described later). The RGB interface is performed in synchronization with VSYNC, HSYNC, and DOTCLK. Window Address Function enables transfer only the screen to be updated and reduce the power consumption. In the period between the completion of displaying one frame data and the next VSYNC signal, the display status will remain in front porch period. VSYNC L H Back Porch (BP) Moving Picture Display Area (NL) Front Porch (FP) HSYNC DOTCLK ENABLE DB [NOTE] - Number of Line in a Frame ; BP + NL + FP - EPL = 0, DPL = 0 Figure 63 : RGB Interface [NOTE] For RGB interface, VSYNC, HSYNC, DOTCLK should be supplied at much higher resolution than that of panel. There are three timing conditions for RGB Interface that is determined according to RIM and each condition is described below. 96 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY 18BIT RGB INTERFACE Bit Assignment Input Data DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Instruction Bit (IB) R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 * 262,144 color display is possible using the 18-bit system interface Figure 64 : Bit Assignment of GRAM Data on 18bit RGB Interface Timing Diagram 1 Frame VSYNC >= 1H A Back Porch Front Porch 1H HSYNC DOTCLK ENABLE DB[17:0] B HSYNC >= 1CLK 1CLK DOTCLK ENABLE DB[17:0] Figure 65 : Timing Diagram of 18/16bit RGB Interface 97 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY 16BIT RGB INTERFACE Bit Assignment Input Data GRAM Data DB17 DB16 DB15 DB14 DB13 R5 R4 R3 R2 R1 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 R0 G5 G4 G3 G2 G1 G0 B5 B4 * 65,538 color display is possible using the 16-bit system interface Figure 66 : Bit Assignment of GRAM Data on 16bit RGB Interface Timing Diagram There are two timing conditions for RGB Interface that is determined according to RIM. 1 Frame VSYNC >= 1H A Back Porch Front Porch 1H HSYNC DOTCLK ENABLE DB[17:0] B HSYNC >= 1CLK 1CLK DOTCLK ENABLE DB[17:0] Figure 67 : Timing Diagram of 18/16bit RGB Interface 98 B3 B2 B1 B0 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY 6BIT RGB INTERFACE In order to transfer data on 6bit RGB Interface there should be three transfers. Bit Assignment 1st transfer Input Data Instruction Bit (IB) 2nd transfer 3rd transfer DB17 DB16 DB15 DB14 DB13 DB12 DB17 DB16 DB15 DB14 DB13 DB12 DB17 DB16 DB15 DB14 DB13 DB12 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 * 262,144 color display is possible using the 18-bit system interface Figure 68 : Bit Assignment of GRAM Data on 6bit RGB Interface Timing Diagram 1 Frame VSYNC >= 1H A Back Porch Front Porch 1H HSYNC DOTCLK ENABLE DB[17:12] B HSYNC >= 3CLK 1CLK DOTCLK ENABLE DB[17:12] R G BR G B R G BR G B R G BR G B R G BR G B R G B R G B R G B R G BR G B Figure 69 : Timing Diagram of 6bit RGB Interface [NOTES] 1. Three clocks are regarded as one clock for transfer when data is transferred in 6-bit interface. 2. VSYNC, HSYNC, ENABLE, DOTCLK, and DB[17:12] should be transferred in units of three clocks. 99 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY Transfer Synchronization VSYNC ENABLE (EPL=0) DOTCLK DB[17:12] 1st 2nd Transfer Synchronization 1st 2nd 3rd 1st 2nd 3rd Figure 70 : Transfer Synchronization Function in 6-bit RGB Interface mode NOTE: The figure above shows Transfer Synchronization function for 6bit RGB Interface. S6D0144 has a transfer counter internally to count 1st, 2nd and 3rd data transfer of 6bit RGB Interface. The transfer counter is reset on the falling edge of VSYNC and enters the 1st data transmission state. Transfer mismatch can be corrected at every VSYNC signal assertion. In this method, when data is consecutively transferred in for displaying motion pictures, the effect of transfer mismatch will be reduced and recovered by normal operation. NOTE: The internal display is operated in units of three DOTCLKs. When DOTCLK is not input in units of pixels, clock mismatch occurs and the frame, which is operated, and the next frame are not displayed correctly. 100 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY INTERFACE SWAPPING FOR MEMORY ACCESS DISPLAY MODES AND GRAM ACCESS CONTROL Display mode and RAM Access is controlled as shown below. For each display status, display mode control and RAM Access control are combined properly. Table 64 : DISPLAY MODE & RAM ACCESS CONTROL Display Status GRAM Access (RM) Display Mode (DM) 1. Still Picture Display 2. Motion Picture Display 3. Rewrite Still Picture while Motion Picture is being displayed System Interface (RM = 0) Internal Clock Operation (DM[1:0] = 00) RGB Interface (RM = 1) External Clock Operation (DM[1:0] = 01) System Interface (RM = 0) External Clock Operation (DM[1:0] = 01) [NOTE 1] Only system interface can set Instruction register. [NOTE 2] When the RGB Interface is being operated do not change the RGB Interface mode (RIM). Internal Clock Operation mode with System Interface (1) Every operation in Internal Clock Operation mode is done in synchronization with the internal clock which is generated by internal OSC. The signals input through RGB interface are all meaningless. Access to internal GRAM is done via system interface. External Clock Operation mode with RGB Interface (2) In External Clock Operation mode, frame sync signal (VSYNC), line sync signal (HSYNC) and DOTCLK are used for display operation. Display data is transferred in the unit of pixel through DB bus and saved to GRAM. External Clock Operation mode with System Interface (3) Write GRAM data via system interface even in External Clock Operation mode. There should not be any data transmission on RGB interface in this case. To restart data transmission on RGB interface, set RM to “1”, set memory address properly and write index of 22h for GRAM write operation. With the combination of Window Address function, motion picture and still picture may be saved in separated GRAM regions respectively. In this case motion picture and still picture are displayed simultaneously. 101 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY GRAM ACCESS VIA RGB INTERFACE AND SPI All the data for display is written to the internal GRAM in S6D0144 when RGB interface is in use. In this method, data, including motion picture and screen update frame, can only be transferred via RGB interface. With Window Address function, power consumption can be reduced and high-speed access can be achieved while motion pictures are being displayed. Data for display that is not in the motion picture area or the screen update frame can be written via System Interface. GRAM can be accessed via SPI even when RGB interface is in use. To do that ENABLE should be inactive state to stop data writing via RGB interface, because the write operation to GRAM is always performed in synchronization with DOTCLK while ENABLE is active state. Then you may write any data through SPI. After this access to GRAM via SPI, a waiting time is needed for a write/read bus cycle before the next RAM access starts via RGB interface. When a RAM write conflict occurs, data writing is not guaranteed. VSYNC ENABLE DOTCLK DB[17:0] SPI Index R22 RM=0 Updating Moving Picture Addr Set Index R22 Updating of area other than Moving Picture area Addr Set RM=1 Index R22 Updating Moving Picture [NOTE] EPL = "0" 2006/01/01 00:00 Still Picture Display Area Motion Picture Display Area Figure 71 : GRAM Access through RGB Interface and SPI 102 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY TRANSITION SEQUENCES BETWEEN DISPLAY MODES Transitions between Internal Clock Operation mode and External Clock Operation mode should follow the mode transition sequence shown below. Internal Clock Operation External Clock Operation Address Set Internal Clock Operation Mode Set ( DM[1:0] = "00", RM = "0" ) Ensure RGB Interface Signals Internal Clock Operation ( VSYNC, HSYNC, DOTCLK, ENABLE) External Clock Operation Mode Set ( DM[1:0] = "01", RM = "1" ) Wait more than 1 frame RGB Interface Signals are ignored ( VSYNC, HSYNC, DOTCLK, ENABLE) External Clock Operation The changes of DM, RM becomes valid after 1 frame display Internal Clock Operation WDR Set (R22h) Internal Clock Operation The changes of DM, RM becomes valid after 1 frame display External Clock Operation Wait more than 1 frame Input GRAM Data on RGB Interface External Clock Operation Transition from Internal Clock Operation to External Clock Operation Transition from External Clock Operation to Internal Clock Operation Figure 72 : Transition between Internal Clock Operation Mode and External Clock Operation Mode 103 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY PANEL CONTROL INTERFACE INTERCONNECTION BETWEEN PANEL AND S6D0144 G160 G158 G156 G159 G157 G155 128RGB x 160DOT TFT-LCD PANEL G5 G3 G1 G6 G4 G2 S6D0144 SYSTEM INTERFACE Figure 73 : System structure 104 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY TIMING DIAGRAMS Frame Inversion & Line Inversion 4 3 2 1 BP1 FP1 BP0 160 FP0 159 158 5 4 3 2 1 BP1 BP0 FP0 FP1 1 Frame 160 159 158 5 4 3 2 ( Line Number ) 1 1 Frame FLM Frame Inverted VCOM Line Inverted VCOM Figure 74 : VCOM waveforms and LCD inversion (BP = 2, FP = 2) 105 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY Source Output & Gate Clock RTN RTN (DISP_CK) 1.5 DISP_CK Sn (SD = 1, REV = 0) VCOM normal 0.5 DISP_CK SDT EQ inversed negative polarity positive polarity Floating G[n-1] G[n] G[n+1] GNO G[n+2] [NOTE] DISP_CK : OSCK_CK divided by DIV[1:0](DM = 2’b00) or DOTCLK divided by 8(DM = 2’b01 and RIM[1] = 1’b1) Figure 75 : Source Output & Gate Clock Timing (EQ = 2’b11, GNO = 2’b01, DIV = 2’b00) 106 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY Interlaced Scanning Function FP BP FP BP VCOM G1 G2 G3 G4 G5 --- G156 G157 G158 G159 G160 Figure 76 : normal scanning method (Line Inversion) FP BP FP BP VCOM G1 G2 G3 G4 G5 --- G156 G157 G158 G159 G160 Figure 77 : 3-field interlaced scanning method 107 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY GAMMA ADJUSTMENT FUNCTION The S6D0144 provides the gamma adjustment function to display 262,144 colors simultaneously. The gamma adjustment executed by the gradient adjustment register and the micro-adjustment register that determines 8 grayscale levels. Furthermore, since the gradient adjustment register and the micro-adjustment register have the positive polarities and negative polarities, adjust them to match LCD panel respectively. Graphics RAM (GRAM) MSB ----------------------------------------------------------- LSB Positive polarity register VRP03 VRP14 VRP13 PKP02 PKP01 PKP00 PKP12 PKP11 PKP10 PKP22 PKP21 PKP20 PKP32 PKP31 PKP30 PKP42 PKP41 PKP40 PKP52 PKP51 PKP50 PRP02 PRP01 PRP00 B05 B04 B03 B02 B01 PRP12 PRP11 PRP10 VRP02 VRP01 VRP00 V0 VRP10 V1 VRP12 VRP11 8 Negative polarity register VRN14 B00 PKN02 PKN01 PKN00 PKN12 PKN11 PKN10 PKN22 PKN21 PKN20 PKN32 PKN31 PKN30 PKN42 PKN41 PKN40 PKN52 PKN51 PKN50 PRN02 PRN01 PRN00 PRN12 PRN11 PRN10 VRN03 VRN02 VRN01 VRN00 VRN13 VRN12 VRN11 VRN10 Grayscale amplifier 64 G05 G04 G03 G02 G01 G00 6 6 B03 B02 B01 B00 6 64-grayscale control <R> 64-grayscale control <G> 64-grayscale control <B> LCD driver LCD driver LCD driver V63 R G LCD Figure 78 : Grayscale control 108 B05 B04 B S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY STRUCTURE OF GRAYSCALE AMPLIFIER The structure of the grayscale amplifier is shown as below. Determine 8-level (VIN0-VIN7) by the gradient adjuster and the micro adjustment register. Each level is split by the internal ladder resistance and level between V0 to V63 is generated. Figure 79 : Structure of grayscale amplifier 109 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY Figure 80 : Structure of Ladder / 8 to 1 selector 110 S6D0144 PRELIMINARY S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY GAMMA ADJUSTMENT REGISTER Grayscale Voltage Grayscale Voltage Grayscale Voltage This block has the register to set up the grayscale voltage adjusting to the gamma specification of the LCD panel. These registers can independently set up to positive/negative polarities and there are 3 types of register groups to adjust gradient and amplitude on number of the grayscale, characteristics of the grayscale voltage. (Average <R><G><B> is common.) The following figure indicates the operation of each adjusting register. Figure 81 : The operation of adjusting register a) Gradient adjustment resistor The gradient adjustment resistors are used to adjust the gradient in the middle of the grayscale characteristics for the voltage without changing the dynamic range. To accomplish the adjustment, it controls the variable resistor (VRHP (N) / VRLP (N)) of the ladder resistor for the grayscale voltage generator. Also, there is an independent resistor on the positive/negative polarities in order for corresponding to asymmetry drive. b) Amplitude adjustment resistor The amplitude-adjusting resistor is to adjust amplitude of the grayscale voltage. To accomplish the adjustment, it controls the variable resistor (VRP(N)0) of the ladder resistor for the grayscale voltage generator located at upper side of the ladder resistor and it controls the variable resistor (VRP(N)1) of the ladder resistor for the grayscale voltage generator located at lower side of the ladder resistor. Also, there is an independent resistor on the positive/negative polarities as well as the gradient-adjusting resistor. c) Micro adjustment resistor The micro adjustment resistor is to make subtle adjustment of the grayscale voltage level. To accomplish the adjustment, it controls the each reference voltage level by the 8 to 1 selector towards the 8-leveled reference voltage generated from the ladder resistor. Also, there is an independent resistor on the positive/negative polarities as well as other adjusting resistors. 111 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY Register Table 65 : Gamma correction registers Positive polarity Negative polarity S6D0144 PRELIMINARY Set-up contents PRP0[2:0] PRN0[2:0] Variable resistor VRHP(N) PRP1[2:0] PRN1[2:0] Variable resistor VRLP(N) VRP0[3:0] VRN0[3:0] Variable resistor VRP(N)0 VRP1[4:0] VRN1[4:0] Variable resistor VRP(N)1 PKP0[2:0] PKN0[2:0] The voltage of grayscale number 1 is selected by the 8 to 1 selector PKP1[2:0] PKN1[2:0] The voltage of grayscale number 8 is selected by the 8 to 1 selector PKP2[2:0] PKN2[2:0] The voltage of grayscale number 20 is selected by the 8 to 1 selector PKP3[2:0] PKN3[2:0] The voltage of grayscale number 43 is selected by the 8 to 1 selector PKP4[2:0] PKN4[2:0] The voltage of grayscale number 55 is selected by the 8 to 1 selector PKP5[2:0] PKN5[2:0] The voltage of grayscale number 62 is selected by the 8 to 1 selector Gradient adjustment Amplitude adjustment Micro-adjustment 112 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY LADDER RESISTOR / 8-to-1 SELECTOR This block outputs the reference voltage of the grayscale voltage. There are two ladder resistors including the variable resistor and the 8 to 1 selector selecting voltage generated by the ladder resistance voltage. The variable and 8 to 1 resistors are controlled by the gamma resistor. Also, there are pins that connect to the external volume resistor. In addition, it allows compensating the dispersion of length from one panel to another. VARIABLE RESISTOR There are 2 types of the variable resistors that are for the gradient adjustment (VRHP (N) / VRLP (N)) and for the amplitude adjustment (VRP(N)0 / VRP(N)1). The resistance value is set by the gradient adjusting resistor and the amplitude adjustment resistor as below. Table 66 : Gradient Adjustment Register value PRP(N) [2:0] Resistance value VRHP(N)/VRLP(N) 000 001 010 011 100 101 110 111 0R 4R 8R 12R 16R 20R 24R 28R Table 67 : Amplitude Adjustment(1) Register value VRP(N)0 [3:0] Resistance value VRP(N)0 0000 0001 0010 . . . 1101 1110 1111 0R 2R 4R . . . 26R 28R 30R Table 68 : Amplitude Adjustment(2) Register value VRP(N)1 [4:0] , VR1C=0 Resistance value VRP(N)1 00000 00001 00010 . . . 11101 11110 11111 0R 1R 2R . . . 29R 30R 31R 113 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY Table 69 : Amplitude Adjustment(3) 114 Register value VRP(N)1 [4:0] , VR1C=1 Resistance value VRP(N)1 00000 00001 00010 . . . 01101 01110 01111 10000 . . . 11101 11110 11111 0R 2R 4R . . . 26R 28R 30R Setting disabled . . . Setting disabled Setting disabled Setting disabled S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY 8-to-1 SELECTOR In the 8 to 1 selector, the voltage level must be selected given by the ladder resistance and the micro-adjusting register. And output the voltage the six types of the reference voltage, the VIN1- to VIN6. Following figure explains the relationship between the micro-adjusting register and the selecting voltage. Table 70 : Relationship between Micro-adjustment Register and Selected Voltage Register value Selected voltage PKP(N) [2:0] VINP(N)1 VINP(N)2 VINP(N)3 VINP(N)4 VINP(N)5 000 KVP(N)1 KVP(N)9 KVP(N)17 KVP(N)25 KVP(N)33 001 KVP(N)2 KVP(N)10 KVP(N)18 KVP(N)26 KVP(N)34 010 KVP(N)3 KVP(N)11 KVP(N)19 KVP(N)27 KVP(N)35 011 KVP(N)4 KVP(N)12 KVP(N)20 KVP(N)28 KVP(N)36 100 KVP(N)5 KVP(N)13 KVP(N)21 KVP(N)29 KVP(N)37 101 KVP(N)6 KVP(N)14 KVP(N)22 KVP(N)30 KVP(N)38 110 KVP(N)7 KVP(N)15 KVP(N)23 KVP(N)31 KVP(N)39 111 KVP(N)8 KVP(N)16 KVP(N)24 KVP(N)32 KVP(N)40 VINP(N)6 KVP(N)41 KVP(N)42 KVP(N)43 KVP(N)44 KVP(N)45 KVP(N)46 KVP(N)47 KVP(N)48 115 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY Table 71 : Gamma Adjusting Voltage Formula (Positive polarity) 1 Pins Formula KVP0 GVDD - ∆V *VRP0 / SUMRP KVP1 GVDD - ∆V * (VRP0 + 5R) / SUMRP KVP2 GVDD - ∆V * (VRP0 + 9R) / SUMRP KVP3 GVDD - ∆V * (VRP0 + 13R) / SUMRP KVP4 GVDD - ∆V * (VRP0 + 17R) / SUMRP KVP5 GVDD - ∆V * (VRP0 + 21R) / SUMRP KVP6 GVDD - ∆V * (VRP0 + 25R) / SUMRP KVP7 GVDD - ∆V * (VRP0 + 29R) / SUMRP KVP8 GVDD - ∆V * (VRP0 + 33R) / SUMRP KVP9 GVDD - ∆V * (VRP0 + 33R + VRHP) / SUMRP KVP10 GVDD - ∆V * (VRP0 + 34R + VRHP) / SUMRP KVP11 GVDD - ∆V * (VRP0 + 35R + VRHP) / SUMRP KVP12 GVDD - ∆V * (VRP0 + 36R + VRHP) / SUMRP KVP13 GVDD - ∆V * (VRP0 + 37R + VRHP) / SUMRP KVP14 GVDD - ∆V * (VRP0 + 38R + VRHP) / SUMRP KVP15 GVDD - ∆V * (VRP0 + 39R + VRHP) / SUMRP KVP16 GVDD - ∆V * (VRP0 + 40R + VRHP) / SUMRP KVP17 GVDD - ∆V * (VRP0 + 45R + VRHP) / SUMRP KVP18 GVDD - ∆V * (VRP0 + 46R + VRHP) / SUMRP KVP19 GVDD - ∆V * (VRP0 + 47R + VRHP) / SUMRP KVP20 GVDD - ∆V * (VRP0 + 48R + VRHP) / SUMRP KVP21 GVDD - ∆V * (VRP0 + 49R + VRHP) / SUMRP KVP22 GVDD - ∆V * (VRP0 + 50R + VRHP) / SUMRP KVP23 GVDD - ∆V * (VRP0 + 51R + VRHP) / SUMRP KVP24 GVDD - ∆V * (VRP0 + 52R + VRHP) / SUMRP KVP25 GVDD - ∆V * (VRP0 + 68R + VRHP) / SUMRP KVP26 GVDD - ∆V * (VRP0 + 69R + VRHP) / SUMRP KVP27 GVDD - ∆V * (VRP0 + 70R + VRHP) / SUMRP KVP28 GVDD - ∆V * (VRP0 + 71R + VRHP) / SUMRP KVP29 GVDD - ∆V * (VRP0 + 72R + VRHP) / SUMRP KVP30 GVDD - ∆V * (VRP0 + 73R + VRHP) / SUMRP KVP31 GVDD - ∆V * (VRP0 + 74R + VRHP) / SUMRP KVP32 GVDD - ∆V * (VRP0 + 75R + VRHP) / SUMRP KVP33 GVDD - ∆V * (VRP0 + 80R + VRHP) / SUMRP KVP34 GVDD - ∆V * (VRP0 + 81R + VRHP) / SUMRP KVP35 GVDD - ∆V * (VRP0 + 82R + VRHP) / SUMRP KVP36 GVDD - ∆V * (VRP0 + 83R + VRHP) / SUMRP KVP37 GVDD - ∆V * (VRP0 + 84R + VRHP) / SUMRP KVP38 GVDD - ∆V * (VRP0 + 85R + VRHP) / SUMRP KVP39 GVDD - ∆V * (VRP0 + 86R + VRHP) / SUMRP KVP40 GVDD - ∆V * (VRP0 + 87R + VRHP) / SUMRP KVP41 GVDD - ∆V * (VRP0 + 87R + VRHP + VRLP) / SUMRP KVP42 GVDD - ∆V * (VRP0 + 91R + VRHP + VRLP) / SUMRP KVP43 GVDD - ∆V * (VRP0 + 95R + VRHP + VRLP) / SUMRP KVP44 GVDD - ∆V * (VRP0 + 99R + VRHP + VRLP) / SUMRP KVP45 GVDD - ∆V * (VRP0 + 103R + VRHP + VRLP) / SUMRP KVP46 GVDD - ∆V * (VRP0 + 107R + VRHP + VRLP) / SUMRP KVP47 GVDD - ∆V * (VRP0 + 111R + VRHP + VRLP) / SUMRP KVP48 GVDD - ∆V * (VRP0 + 115R + VRHP + VRLP) / SUMRP KVP49 GVDD - ∆V * (VRP0 + 120R + VRHP + VRLP) / SUMRP SUMRP: Total of the positive polarity ladder resistance = 128R + VRHP + VRLP + VRP0+VRP1 ∆V: Potential difference between GVDD-VGS 116 Micro-adjusting register value Reference voltage PKP0[2:0] = “000” PKP0[2:0] = “001” PKP0[2:0] = “010” PKP0[2:0] = “011” PKP0[2:0] = “100” PKP0[2:0] = “101” PKP0[2:0] = “110” PKP0[2:0] = “111” PKP1[2:0] = “000” PKP1[2:0] = “001” PKP1[2:0] = “010” PKP1[2:0] = “011” PKP1[2:0] = “100” PKP1[2:0] = “101” PKP1[2:0] = “110” PKP1[2:0] = “111” PKP2[2:0] = “000” PKP2[2:0] = “001” PKP2[2:0] = “010” PKP2[2:0] = “011” PKP2[2:0] = “100” PKP2[2:0] = “101” PKP2[2:0] = “110” PKP2[2:0] = “111” PKP3[2:0] = “000” PKP3[2:0] = “001” PKP3[2:0] = “010” PKP3[2:0] = “011” PKP3[2:0] = “100” PKP3[2:0] = “101” PKP3[2:0] = “110” PKP3[2:0] = “111” PKP4[2:0] = “000” PKP4[2:0] = “001” PKP4[2:0] = “010” PKP4[2:0] = “011” PKP4[2:0] = “100” PKP4[2:0] = “101” PKP4[2:0] = “110” PKP4[2:0] = “111” PKP5[2:0] = “000” PKP5[2:0] = “001” PKP5[2:0] = “010” PKP5[2:0] = “011” PKP5[2:0] = “100” PKP5[2:0] = “101” PKP5[2:0] = “110” PKP5[2:0] = “111” - VINP0 VINP1 VINP2 VINP3 VINP4 VINP5 VINP6 VINP7 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY Table 72 : Gamma Voltage Formula (Positive Polarity) 2 Grayscale voltage V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 [NOTE] Formula VINP0 VINP1 V1-(V1-V8)*(28/96) V1-(V1-V8)*(42/96) V1-(V1-V8)*(60/96) V1-(V1-V8)*(69/96) V1-(V1-V8)*(78/96) V1-(V1-V8)*(87/96) VINP2 V8-(V8-V20)*(2/24) V8-(V8-V20)*(4/24) V8-(V8-V20)*(6/24) V8-(V8-V20)*(8/24) V8-(V8-V20)*(10/24) V8-(V8-V20)*(12/24) V8-(V8-V20)*(14/24) V8-(V8-V20)*(16/24) V8-(V8-V20)*(18/24) V8-(V8-V20)*(20/24) V8-(V8-V20)*(22/24) VINP3 V20-(V20-V43)*(1/23) V20-(V20-V43)*(2/23) V20-(V20-V43)*(3/23) V20-(V20-V43)*(4/23) V20-(V20-V43)*(5/23) V20-(V20-V43)*(6/23) V20-(V20-V43)*(7/23) V20-(V20-V43)*(8/23) V20-(V20-V43)*(9/23) V20-(V20-V43)*(10/23) V20-(V20-V43)*(11/23) Grayscale voltage V32 V33 V34 V35 V36 V37 V38 V39 V40 V41 V42 V43 V44 V45 V46 V47 V48 V49 V50 V51 V52 V53 V54 V55 V56 V57 V58 V59 V60 V61 V62 V63 Formula V20-(V20-V43)*(12/23) V20-(V20-V43)*(13/23) V20-(V20-V43)*(14/23) V20-(V20-V43)*(15/23) V20-(V20-V43)*(16/23) V20-(V20-V43)*(17/23) V20-(V20-V43)*(18/23) V20-(V20-V43)*(19/23) V20-(V20-V43)*(20/23) V20-(V20-V43)*(21/23) V20-(V20-V43)*(22/23) VINP4 V43-(V43-V55)*(2/24) V43-(V43-V55)*(4/24) V43-(V43-V55)*(6/24) V43-(V43-V55)*(8/24) V43-(V43-V55)*(10/24) V43-(V43-V55)*(12/24) V43-(V43-V55)*(14/24) V43-(V43-V55)*(16/24) V43-(V43-V55)*(18/24) V43-(V43-V55)*(20/24) V43-(V43-V55)*(22/24) VINP5 V55-(V55-V62)*(9/96) V55-(V55-V62)*(18/96) V55-(V55-V62)*(27/96) V55-(V55-V62)*(36/96) V55-(V55-V62)*(54/96) V55-(V55-V62)*(68/96) VINP6 VINP7 Keep the following conditions. AVDD – V0 > 0.5V AVDD – V8 > 1.1V 117 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY Table 73 : Gamma Adjusting Voltage Formula (Negative polarity) 1 Pins KVN0 KVN1 KVN2 KVN3 KVN4 KVN5 KVN6 KVN7 KVN8 KVN9 KVN10 KVN11 KVN12 KVN13 KVN14 KVN15 KVN16 KVN17 KVN18 KVN19 KVN20 KVN21 KVN22 KVN23 KVN24 KVN25 KVN26 KVN27 KVN28 KVN29 KVN30 KVN31 KVN32 KVN33 KVN34 KVN35 KVN36 KVN37 KVN38 KVN39 KVN40 KVN41 KVN42 KVN43 KVN44 KVN45 KVN46 KVN47 KVN48 KVN49 Formula GVDD - ∆V *VRN0 / SUMRN GVDD - ∆V * (VRN0 + 5R) / SUMRN GVDD - ∆V * (VRN0 + 9R) / SUMRN GVDD - ∆V * (VRN0 + 13R) / SUMRN GVDD - ∆V * (VRN0 + 17R) / SUMRN GVDD - ∆V * (VRN0 + 21R) / SUMRN GVDD - ∆V * (VRN0 + 25R) / SUMRN GVDD - ∆V * (VRN0 + 29R) / SUMRN GVDD - ∆V * (VRN0 + 33R) / SUMRN GVDD - ∆V * (VRN0 + 33R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 34R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 35R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 36R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 37R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 38R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 39R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 40R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 45R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 46R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 47R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 48R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 49R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 50R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 51R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 52R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 68R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 69R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 70R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 71R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 72R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 73R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 74R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 75R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 80R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 81R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 82R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 83R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 84R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 85R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 86R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 87R + VRHN) / SUMRN GVDD - ∆V * (VRN0 + 87R + VRHN + VRLN) / SUMRN GVDD - ∆V * (VRN0 + 91R + VRHN + VRLN) / SUMRN GVDD - ∆V * (VRN0 + 95R + VRHN + VRLN) / SUMRN GVDD - ∆V * (VRN0 + 99R + VRHN + VRLN) / SUMRN GVDD - ∆V * (VRN0 + 103R + VRHN + VRLN) / SUMRN GVDD - ∆V * (VRN0 + 107R + VRHN + VRLN) / SUMRN GVDD - ∆V * (VRN0 + 111R + VRHN + VRLN) / SUMRN GVDD - ∆V * (VRN0 + 115R + VRHN + VRLN) / SUMRN GVDD - ∆V * (VRN0 + 120R + VRHN + VRLN) / SUMRN Micro-adjusting register value PKP0[2:0] = “000” PKP0[2:0] = “001” PKP0[2:0] = “010” PKP0[2:0] = “011” PKP0[2:0] = “100” PKP0[2:0] = “101” PKP0[2:0] = “110” PKP0[2:0] = “111” PKP1[2:0] = “000” PKP1[2:0] = “001” PKP1[2:0] = “010” PKP1[2:0] = “011” PKP1[2:0] = “100” PKP1[2:0] = “101” PKP1[2:0] = “110” PKP1[2:0] = “111” PKP2[2:0] = “000” PKP2[2:0] = “001” PKP2[2:0] = “010” PKP2[2:0] = “011” PKP2[2:0] = “100” PKP2[2:0] = “101” PKP2[2:0] = “110” PKP2[2:0] = “111” PKP3[2:0] = “000” PKP3[2:0] = “001” PKP3[2:0] = “010” PKP3[2:0] = “011” PKP3[2:0] = “100” PKP3[2:0] = “101” PKP3[2:0] = “110” PKP3[2:0] = “111” PKP4[2:0] = “000” PKP4[2:0] = “001” PKP4[2:0] = “010” PKP4[2:0] = “011” PKP4[2:0] = “100” PKP4[2:0] = “101” PKP4[2:0] = “110” PKP4[2:0] = “111” PKP5[2:0] = “000” PKP5[2:0] = “001” PKP5[2:0] = “010” PKP5[2:0] = “011” PKP5[2:0] = “100” PKP5[2:0] = “101” PKP5[2:0] = “110” PKP5[2:0] = “111” - SUMRN: Total of the negative polarity ladder resistance = 128R + VRHN + VRLN + VRN0+VRN1 ∆V: Potential difference between GVDD-VGS 118 Reference voltage VINN0 VINN1 VINN2 VINN3 VINN4 VINN5 VINN6 VINN7 S6D0144 PRELIMINARY Grayscale voltage V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 [NOTE] 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY Table 74 : Gamma Voltage Formula (Negative Polarity) 2 Formula Grayscale voltage VINN0 VINN1 V1-(V1-V8)*(28/96) V1-(V1-V8)*(42/96) V1-(V1-V8)*(60/96) V1-(V1-V8)*(69/96) V1-(V1-V8)*(78/96) V1-(V1-V8)*(87/96) VINN2 V8-(V8-V20)*(2/24) V8-(V8-V20)*(4/24) V8-(V8-V20)*(6/24) V8-(V8-V20)*(8/24) V8-(V8-V20)*(10/24) V8-(V8-V20)*(12/24) V8-(V8-V20)*(14/24) V8-(V8-V20)*(16/24) V8-(V8-V20)*(18/24) V8-(V8-V20)*(20/24) V8-(V8-V20)*(22/24) VINN3 V20-(V20-V43)*(1/23) V20-(V20-V43)*(2/23) V20-(V20-V43)*(3/23) V20-(V20-V43)*(4/23) V20-(V20-V43)*(5/23) V20-(V20-V43)*(6/23) V20-(V20-V43)*(7/23) V20-(V20-V43)*(8/23) V20-(V20-V43)*(9/23) V20-(V20-V43)*(10/23) V20-(V20-V43)*(11/23) V32 V33 V34 V35 V36 V37 V38 V39 V40 V41 V42 V43 V44 V45 V46 V47 V48 V49 V50 V51 V52 V53 V54 V55 V56 V57 V58 V59 V60 V61 V62 V63 Formula V20-(V20-V43)*(12/23) V20-(V20-V43)*(13/23) V20-(V20-V43)*(14/23) V20-(V20-V43)*(15/23) V20-(V20-V43)*(16/23) V20-(V20-V43)*(17/23) V20-(V20-V43)*(18/23) V20-(V20-V43)*(19/23) V20-(V20-V43)*(20/23) V20-(V20-V43)*(21/23) V20-(V20-V43)*(22/23) VINN4 V43-(V43-V55)*(2/24) V43-(V43-V55)*(4/24) V43-(V43-V55)*(6/24) V43-(V43-V55)*(8/24) V43-(V43-V55)*(10/24) V43-(V43-V55)*(12/24) V43-(V43-V55)*(14/24) V43-(V43-V55)*(16/24) V43-(V43-V55)*(18/24) V43-(V43-V55)*(20/24) V43-(V43-V55)*(22/24) VINN5 V55-(V55-V62)*(9/96) V55-(V55-V62)*(18/96) V55-(V55-V62)*(27/96) V55-(V55-V62)*(36/96) V55-(V55-V62)*(54/96) V55-(V55-V62)*(68/96) VINN6 VINN7 Keep the following conditions. AVDD – V0 > 0.5V AVDD – V8 > 1.1V 119 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY OUTPUT LEVEL AS THE FUNCTION OF GRAM DATA V0 Negative Polarity Output Level Positive Polarity V63 000000 RAM data (common charactersics to RGB) Figure 82 : Relationship between RAM data and output voltage 120 111111 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY V0 Sn (GRAM DATA = 1) V63 V0 Sn (GRAM DATA = 0) Black White V63 VcomH Black Vcom White VcomL Negative Polarity Positive Polarity (a) For Normally Black Panel (REV = 0) V0 Sn (GRAM DATA = 1) V63 V0 Sn (GRAM DATA = 0) Black V63 White VcomH Black Vcom White VcomL Negative Polarity Positive Polarity (b) For Normally White Panel (REV = 1) Figure 83 : Relationship between source output and Vcom 121 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY THE 8-COLOR DISPLAY MODE The S6D0144 incorporates 8-color display mode. During the 8-color mode all the gray scale levels (V1~V62) are halt. So that it attempts to lower power consumption. During the 8-color mode, the Gamma micro adjustment register, PKP and PKN are invalid. Since V1-V62 is stopped, the RGB data in the GRAM should be set to 000000 or 111111 before set the mode. Graphics RAM (GRAM) MSB ----------------------------------------------------------- LSB Positive polarity register VRP14 PKP02 PKP01 PKP00 PKP12 PKP11 PKP10 PKP22 PKP21 PKP20 PKP32 PKP31 PKP30 PKP42 PKP41 PKP40 PKP52 PKP51 PKP50 PRP02 PRP01 PRP00 PRP12 PRP11 PRP10 VRP03 VRP02 VRP01 VRP00 VRP13 VRP12 VRP11 VRP10 B05 Negative polarity register VRN14 PKN01 PKN00 PKN12 PKN11 PKN10 PKN22 PKN21 PKN20 PKN32 PKN31 PKN30 PKN42 PKN41 PKN40 PKN52 PKN51 PKN50 PRN02 PRN01 PRN00 PRN12 PRN11 PRN10 VRN03 VRN02 VRN01 VRN00 VRN13 VRN12 VRN11 VRN10 B03 B02 B01 B00 GVDD 8 PKN02 B04 Binary amplifier 2 G05 G04 G03 G02 G01 G00 6 6 B04 B03 B02 6 64-grayscale control <R> 64-grayscale control <G> 64-grayscale control <B> LCD driver LCD driver LCD driver AVSS R G LCD Figure 84 : 8-color display control 122 B05 B B01 B00 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY Figure 85 : Set up procedure for the 8-color mode 123 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY INSTRUCTION SET UP FLOW DISPLAY ON / OFF SEQUENCE <Display off> <Display on> EQ1-0=00 Power setting Display on GON= 1 DTE= 1 D1-0= 10 Display off GON= 0 DTE= 0 D1-0= 01 Wait (more than 2 frames) Wait (more than 2 frames) Display off GON= 1 DTE= 0 D1-0= 10 Display off GON= 1 DTE= 0 D1-0= 01 Wait (more than 2 frames) Display off GON= 1 DTE= 0 D1-0= 11 Display off GON= 0 DTE= 0 D1-0= 00 Wait (more than 2 frames) Power off SAP2-0= 000 AP2-0= 000 Display on GON= 1 DTE= 1 D1-0= 11 Display OFF Display ON Continue to the display on flow Continue to the display on flow Figure 86 : DISPLAY ON / OFF SEQUENCE 124 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY D-STAND-BY / STAND-BY / SLEEP SEQUENCE Figure 87 : D-STAND-BY/STAND-BY / SLEEP SEQUENCE 125 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY OSCILLATION CIRCUIT The S6D0144 can provide R-C oscillation. S6D0144 internal oscillator does not need to attach the external resistor. The appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the oscillator frequency control register setting. Since R-C oscillation stops during the standby mode, power consumption can be reduced. Internal Clock mode only Leave this pin Open S6D0144 EX_CLK Figure 88 : Oscillation Circuit 126 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY APPLICATION CIRCUIT The following figure indicates a schematic diagram of application circuit for S6D0144. 0.22~1uF BV=25V R < 9 ohm 0.22~1uF BV=16.5V R R R R 0.22~1uF BV=16.5V < 25 ohm < 25 ohm < 25 ohm < 25 ohm R < 6 ohm 0.22~1uF BV=25V 1.65~3.3V I/O Power 1.0uF BV=10V 2.5~3.3V Analog Power 1.0uF BV=10V 0.22~1uF BV=10V Note1 Note2 0.22~1uF BV=10V 1.0uF BV=10V Note1 Leave this pin open when VCOMG=0, BT 0 and BT 3 Note2 When VCOMH is externally adjusted, attach these Resistor. Total resistance > 100K ohm Recommend to reduce resistance to acquire the smallest current consumption. 1.0uF BV=10V 1.0uF BV=10V 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm R< R< R< R< R< R< R< R< R< R< 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm R< R< R< R< R< R< R< R< R< 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm R< R< R< R< R< R< R< R< R< R< R< 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm R < 22 ohm R < 7 ohm R < 8 ohm R < 8 ohm R < 10 ohm R < 10 ohm R < 10 ohm R < 10 ohm R < 100 ohm R < 100 ohm R < 10 ohm R < 9 ohm 0.22~1uF BV=10V 1.0uF BV=10V R< R< R< R< R< Note1 R < 25 ohm R < 25 ohm R < 42 ohm R < 25 ohm R < 7 ohm R < 9 ohm R < 10 ohm R < 10 ohm R < 10 ohm R < 10 ohm DUMMY <1> VCOMOUT <3> DUMMY <1> VGH <6> DUMMYR1 <1> DUMMYR2 <1> C22+ <2> C22- <2> C21+ <2> C21- <2> DUMMY <1> VGL <11> DUMMY <5> NDT_EN <1> TEST_IN0 <1> TEST_IN1 <1> TEST_IN2 <1> TEST_IN3 <1> TEST_IN4 <1> IM0 <1> IM1 <1> IM2 <1> IM3 <1> RESETB <1> TEST_MODE0 <1> TEST_MODE1 <1> TEST_MODE2 <1> DB17 <1> DB16 <1> DB15 <1> DB14 <1> DB13 <1> DB12 <1> DB11 <1> DB10 <1> DB9 <1> FLM/TEST_OUT0 <1> TEST_OUT1 <1> TEST_OUT2 <1> DB8 <1> DB7 <1> DB6 <1> DB5 <1> DB4 <1> DB3 <1> DB2 <1> DB1 <1> DB0 <1> TEST_OUT3 <1> TEST_OUT4 <1> SDO <1> SDI <1> VSYNC <1> HSYNC <1> DOTCLK <1> ENABLE <1> RWB_RDB <1> E_WRB <1> RS <1> CSB <1> DSTB_EN <1> EX_CLK <1> VGS <2> VSS <10> VSSC <7> VSSA <7> VDD <5> VDDM <5> RVDD <5> VDD3 <5> DUMMY <1> MTPD <8> MTPG <8> VCI <5> VCI1 <6> VCOML <2> VCOMH <2> VCOMR <1> GVDD <2> AVDD <8> VCL <6> C11- <5> C11+<5> C23- <5> C23+ <5> DUMMY <1> VCOMOUT <3> DUMMY <1> DUMMY DUMMY DUMMY DUMMY G1 G3 G5 G157 G159 DUMMY DUMMY VCOMOUT VCOMOUT VCOMOUT VCOMOUT DUMMY DUMMY DUMMY SOUT1 SOUT2 SOUT382 SOUT383 SOUT384 DUMMY DUMMY VCOMOUT VCOMOUT VCOMOUT VCOMOUT DUMMY DUMMY G160 G158 G6 G4 G2 DUMMY DUMMY DUMMY DUMMY Note1 Figure 89 : Application Circuit 127 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Table 75 : Absolute Maximum Rating (VSS = 0V) Item Symbol Rating Unit Supply voltage for logic block VDD - VSS -0.3 ~ 3.3 V Supply voltage for I/O block VDD3 - VSS -0.3 ~ 5.0 VCI - VSS -0.3 ~ 5.0 V AVDD – VSS -0.3 ~ 6.5 V VGH - VSS -0.3 ~ 22.0 VSS – VGL -0.3 ~ 22.0 VSS - VCL -0.3 ~ 5.0 |VGH – VGL| -0.3 ~ 33 Input Voltage range Vin - 0.3 to VDD3 +0.3 V Maximum rewritable time of MTP tmtp 1000 times Operating temperature Topr -40 ~ +85 °C Storage temperature Tstg -55 ~ +110 °C Supply voltage for step-up circuit LCD Supply Voltage range [NOTE] Absolute maximum rating is the limit value beyond which the IC may be broken. They do not assure operations Operating temperature is the range of device-operating temperature. They do not guarantee chip performance. Absolute maximum rating is guaranteed when our company’s package used. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 128 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY DC CHARACTERISTICS Table 76 : DC Characteristics Characteristic Symbol CONDITION MIN ( VSS = 0V, TA = -40°C ~ 85°C ) TYP MAX Unit Note VDD 1.40 1.60 V *1 VDD3 1.65 3.3 V *1 VGH +7 16.5 V VGL -13.5 -7 V AVDD 3.5 5.5 V Input high voltage VIH 0.8VDD3 VDD3 V *2 Input low voltage VIL 0 0.2VDD3 V *2 Output high voltage VOH IOH = -1.0mA 0.8VDD3 VDD3 V *3 Output low voltage VOL IOL = 10mA 0.0 0.2VDD3 V *3 Operating voltage LCD driving voltage Input leakage current IIL VIN = VSS or VDD3 -1.0 1.0 µA *2 Output leakage current IOL VIN = VSS or VDD3 -3.0 3.0 µA *2 *4 Operating frequency fosc Internal reference power supply voltage VCI st 1 step-up output efficiency AVDD VDD3=2.8V ILOAD=1.0mA, VCI=2.8V T.B.D. 240 T.B.D. kHz 2.5 - 3.3 V 90 95 % 90 95 % 90 95 % 90 95 % BT=000 nd 2 step-up output efficiency VGH ILOAD=0.2mA, VCI=2.8V BT=000 rd 3 step-up output efficiency VGL ILOAD=0.1mA, VCI=2.8V BT=000 th 4 step-up output efficiency VCL ILOAD=0.2mA, VCI=2.8V BT=000 [NOTE] 1. VSS= 0V 2. Applied pins; IM, CSB, E_WRB, RWB_RDB, RS, DB, DSTB_EN, RESETB. 3. Applied pins; DB 4. Target frame frequency = 60 Hz, Display line = 160, Back porch = 3, Front porch = 5 5. Internal RTN[4:0] register = “11000”, Internal DIV[1:0] register = “00” 129 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY Characteristic LCD gate driver output on resistance Output voltage deviation (Mean value) LCD source driver output voltage range Table 77 : DC Characteristics for LCD driver outputs (AVDD=5.0V, VSS = 0V, TA = -40°C ~ 85°C) Symbol CONDITION MIN TYP MAX Unit Note Ron ∆Vo tSD2 tSD3 tSD4 Istby_VDD3 Standby mode current Deep standby mode current [NOTE] 130 2.5 ㏀ 4.2V ≤ Vso ±20 ±55 mV 0.8V < Vso < 4.2V ±10 ±30 mV Vso ≤ 0.8V ±20 ±55 mV 0.1 - AVDD-0.1 V - - 80 µs - - 50 µs - - 40 µs - - 30 µs - - TBD µA AVDD = 5.0V SAP = “010” AVDD = 5.0V SAP = “011” AVDD = 5.0V SAP = “100” AVDD = 5.0V SAP = “101” Standby mode, VDD3=2.8V, VDD=1.5V TBD µA Istby_VCI VCI=2.8V TBD µA TBD µA TBD µA TBD µA 100 µA 3 mA Idstby_VDD3 Deep standby mode, Idstby_VDD VDD3=2.8V, VDD=0V VCI=2.8V IVDD Current consumption during setting MTP - Istby_VDD Idstby_VCI Current consumption during normal operation VGH–VGL=30.0V, VGH=16.5V, VGL=-13.5V, Vgo=VGH - 0.5V Vso tSD1 LCD source driver delay (Cload=18pF,Rload=11Khom) S6D0144 PRELIMINARY IVCI - - No load, VDD3=2.8, VDD=1.5V, VCI=2.8V IMTPG MTPG=19V 0.6 TBD mA *1 IMTPD MTPD=16V 0.6 TBD mA *1 1. Simulation result., with common power condition VDD3=2.8, VDD=1.5V, VCI=2.8V S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY 1H period 1H period CL VCOM 95% 95% 5% 5% Sn tSDx tSDx Figure 90 : DC characteristics 131 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY AC CHARACTERISTICS 68-SYSTEM 18/16/9/8BIT INTERFACE RS RWB VIH VIH VIL VIL tAS68 tAH68 CSB tWHW68, tWHR68 E VIH VIH VIL VIL tR DB VIL tF tCYCW68, tCYCR68 tWDS68 twDH68 VIH WRITE DATA VIL VIH VIL tRDD68 DB tWLW68, tWLR68 trDH68 VOH VOL READ DATA VOH VOL [NOTE] tWLW68 and tWLR68 are determined by the overlap period of low CSB and high E. Parameter tCYCW68 tCYCR68 tR, tF tWLW68 tWLR68 tWHW68 tWHR68 tAS68 tAH68 tWDS68 tWDH68 tRDD68 tRDH68 132 Description Min Max Cycle time (Write) 100 Cycle time (Read) 500 Pulse rise / fall time 25 Pulse Width Low (Write) 40 Pulse Width Low (Read) 250 Pulse Width High (Write) 40 Pulse Width High (Read) 200 RS, RWB to CSB, E setup time 0 RS, RWB to CSB, E hold time 0 Write data setup time 60 Write data hold time 2 Read data delay time 200 Read data hold time 5 Figure 91 : AC characteristics of 68-system interface Unit ns ns ns ns ns ns ns ns ns ns ns ns ns S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY 80-SYSTEM 18/16/9/8BIT INTERFACE RS VIH VIH VIL VIL tAS80 tAH80 CSB tWLW80, tWLR80 WRB RDB VIH VIH VIL tR tCYCW80, tCYCR80 tWDS80 twDH80 VIH VIL WRITE DATA tRDD80 DB VIH VIL tF DB tWHW80, tWHR80 VIH VIL trDH80 VOH VOL READ DATA VOH VOL [NOTE] tWLW80 and tWLR80 are determined by the overlap period of low CSB and low WRB or low CSB and low RDB Parameter tCYCW80 tCYCR80 tR, tF tWLW80 tWLR80 tWHW80 tWHR80 tAS80 tAH80 tWDS80 tWDH80 tRDD80 tRDH80 Description Min Max Cycle time (Write) 100 Cycle time (Read) 500 Pulse rise / fall time 25 Pulse Width Low (Write) 40 Pulse Width Low (Read) 250 Pulse Width High (Write) 40 Pulse Width High (Read) 200 RS to CSB, WRB (or RDB) setup time 0 RS to CSB, WRB (or RDB) hold time 0 Write data setup time 60 Write data hold time 2 Read data delay time 200 Read data hold time 5 Figure 92 : AC characteristics or 80-system interface Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 133 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY RGB INTERFACE tDCYC tDWH DOTCLK tDR VIH VIL tDWL VIH tDF VIL tSYNCS VSYNC HSYNC tENS tENH ENABLE tDS DB (PD) Parameter tDCYC tDWL tDWH tDR / tDF tSYNCS tENS tENH tDS tDH 134 tDH INPUT DATA INPUT DATA Description Min DOTCLK period 80 DOTCLK pulse width low 40 DOTCLK pulse width high 40 DOTCLK rising / falling time VSYNC, HSYNC setup 0 ENABLE setup 30 ENABLE hold 20 Input Data setup 30 Input Data hold 20 Figure 93 : AC Characteristics of RGB Interface Max 25 - Unit ns ns ns ns ns ns ns ns ns S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY SERIAL PERIPHERAL INTERFACE Transfer Start CSB Transfer End tCSS tCSH VIL VIH VIL tscyc SCL VIH tF VIL tSCHW, tSCHR tR tSIDH VIH VIH VIL VIL INPUT DATA INPUT DATA tSODD SDO VIH VIL tSIDS SDI tSCLW, tSCLR VOH tSODH OUTPUT DATA OUTPUT DATA VOL Parameter tscyc (write) tscyc (read) tR, tF tSCHW tSCHR tSCLW tSCLR tCSS tCSH tSIDS tSIDH tSODD tSODH VOH VOL Description Serial clock write cycle time Serial clock read cycle time Serial clock rise / fall time Pulse width high for write Pulse width high for read Pulse width low for write Pulse width low for read Chip Select setup time Chip Select hold time Serial input data setup time Serial input data hold time Serial output data delay time Serial output data hold time Min Max 100 500 40 230 60 230 20 60 40 30 5 20 130 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 94 : AC Characteristics of Serial Peripheral Interface 135 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY RESETB tRES RESETB VIL VIL [NOTE] Reset low pulse width shorter than 7us do not make reset. It means undesired short pulse such as glitch, bouncing noise or electrostatic discharge do not cause irregular system reset. Please refer to the table below. Parameter tRES Description Reset low pulse width Min Max 20 - Unit us Figure 95 : AC characteristics (RESET timing) Table 78 : Reset Operation Regarding tRES Pulse Width tRES Pulse Action Shorter than 7 us No reset Longer than 20 us Reset Between 7 us and 20 us Not determined User may or may not use RESETB pin. In order to use it, user should satisfy the conditions described in the above tables. But when not wants to use RESETB, user may float it because internally generated POR (Power-On-Reset) is used. The RESETB is pulled-up internally. 136 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY FIGURES Figure 1 : Block Diagram of S6D0144 ........................................................................................................................ 7 Figure 2 : Pad Configuration....................................................................................................................................... 8 Figure 3 : COG align key .......................................................................................................................................... 10 Figure 4 : GRAM Address and Display Image.......................................................................................................... 25 Figure 5 : Gate Clock Generation order selection using GS and SM (NL = 5’b10100, SCN = 5’b00000) ............... 31 Figure 6 : Gate Clock Generation order selection using GS and SM (NL = 5’b01100, SCN = 5’b00000) ............... 31 Figure 7 : Image mirroring using SS register (SS = “1”) ........................................................................................... 32 Figure 8 : Interlaced scanning methods ................................................................................................................... 34 Figure 9 : 260k color data transfer on 8-bit parallel bus (MDT = 2’b10)................................................................... 35 Figure 10 : 65k color data transfer on 8-bit parallel bus by 3-times Data Transfer (MDT = 2’b11) .......................... 35 Figure 11 : 260k color data transfer on 16-bit parallel bus (MDT = 2’b10)............................................................... 36 Figure 12 : 260k color data transfer on 16-bit parallel bus (MDT = 2’b11)............................................................... 36 Figure 13 : BP & FP in External Clock Operation Mode (DM[0] = “1”) ..................................................................... 41 Figure 14 : BP & FP in Internal Clock Operation Mode (DM[0] = “0”) ...................................................................... 41 Figure 15 : Formula for the frame frequency ............................................................................................................ 42 Figure 16 : Memory Data Write Sequence ............................................................................................................... 54 Figure 17 : Memory Data Read Sequence ............................................................................................................... 55 Figure 18 : Gate Scan Position Control .................................................................................................................... 58 Figure 19 : Window Address Function...................................................................................................................... 60 Figure 20 : Split Screen Driving Function ................................................................................................................. 61 Figure 21 : Partial Display Set Up Flow.................................................................................................................... 63 Figure 22 : Example of Data Update with Window Address Function...................................................................... 64 Table 59 : Pumping Clock Control ............................................................................................................................ 71 Table 60 : VCOMH Control....................................................................................................................................... 72 Figure 25 : MTP Initializae, Erase & Program Flow of S6D0144 ............................................................................. 73 Figure 27 : MTP Read Flow of S6D0144.................................................................................................................. 74 Figure 27 : Configuration of the Internal Power-Supply Circuit ................................................................................ 77 Figure 28 : Pattern diagram and an example of waveforms..................................................................................... 78 Figure 29 : Set up Flow of Power Supply ................................................................................................................. 79 Figure 30 : Voltage regulation function..................................................................................................................... 80 Figure 31 : VCOMH control function......................................................................................................................... 81 Figure 32 : System Interface and RGB Interface...................................................................................................... 82 Figure 33 : Bit Assignment of Instructions on 68-18bit CPU Interface ..................................................................... 84 Figure 34 : Bit Assignment of GRAM Data on 68-18bit CPU Interface .................................................................... 84 Figure 35 : Timing Diagram of 68-18bit CPU Interface ............................................................................................ 84 Figure 36 : Bit Assignment of Instructions on 68-16bit CPU Interface ..................................................................... 85 Figure 37 : Bit Assignment of GRAM Data on 68-16bit CPU Interface .................................................................... 85 Figure 38 : Timing Diagram of 68-16bit CPU Interface ............................................................................................ 85 Figure 39 : Bit Assignment of Instructions on 68-9bit CPU Interface ....................................................................... 86 Figure 40 : Bit Assignment of GRAM Data on 68-9bit CPU Interface ...................................................................... 86 Figure 41 : Timing Diagram of 68-9bit CPU Interface .............................................................................................. 86 Figure 42 : Bit Assignment of Instructions on 68-8bit CPU Interface ....................................................................... 87 Figure 43 : Bit Assignment of GRAM Data on 68-8bit CPU Interface ...................................................................... 87 Figure 44 : Timing Diagram of 68-8bit CPU Interface .............................................................................................. 87 Figure 45 : Bit Assignment of Instructions on 80-18bit CPU Interface ..................................................................... 88 Figure 46 : Bit Assignment of GRAM Data on 80-18bit CPU Interface .................................................................... 88 Figure 47 : Timing Diagram of 80-18bit CPU Interface ............................................................................................ 88 Figure 48 : Bit Assignment of Instructions on 80-16bit CPU Interface ..................................................................... 89 Figure 49 : Bit Assignment of GRAM Data on 80-16bit CPU Interface .................................................................... 89 Figure 50 : Timing Diagram of 80-16bit CPU Interface ............................................................................................ 89 Figure 51 : Bit Assignment of Instructions on 80-9bit CPU Interface ....................................................................... 90 137 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY Figure 52 : Bit Assignment of GRAM Data on 80-9bit CPU Interface ......................................................................90 Figure 53 : Timing Diagram of 80-9bit CPU Interface...............................................................................................90 Figure 54 : Bit Assignment of Instructions on 80-8bit CPU Interface .......................................................................91 Figure 55 : Bit Assignment of GRAM Data on 80-8bit CPU Interface ......................................................................91 Figure 56 : Timing Diagram of 80-8bit CPU Interface...............................................................................................91 Figure 57 : Bit Assignment of Instructions on SPI ....................................................................................................93 Figure 58 : Bit Assignment of GRAM Data on SPI ...................................................................................................93 Figure 59 : Basic Timing Diagram of Data Transfer through SPI .............................................................................94 Figure 60 : Timing Diagram of Consecutive Data-Write through SPI .......................................................................94 Figure 61 : Timing Diagram of Register / Status Read through SPI.........................................................................94 Figure 62 : Timing Diagram of GRAM-Data Read through SPI ................................................................................95 Figure 63 : RGB Interface .........................................................................................................................................96 Figure 64 : Bit Assignment of GRAM Data on 18bit RGB Interface .........................................................................97 Figure 65 : Timing Diagram of 18/16bit RGB Interface.............................................................................................97 Figure 66 : Bit Assignment of GRAM Data on 16bit RGB Interface .........................................................................98 Figure 67 : Timing Diagram of 18/16bit RGB Interface.............................................................................................98 Figure 68 : Bit Assignment of GRAM Data on 6bit RGB Interface ...........................................................................99 Figure 69 : Timing Diagram of 6bit RGB Interface....................................................................................................99 Figure 70 : Transfer Synchronization Function in 6-bit RGB Interface mode .........................................................100 Figure 71 : GRAM Access through RGB Interface and SPI ...................................................................................102 Figure 72 : Transition between Internal Clock Operation Mode and External Clock Operation Mode ...................103 Figure 73 : System structure...................................................................................................................................104 Figure 74 : VCOM waveforms and LCD inversion (BP = 2, FP = 2).......................................................................105 Figure 75 : Source Output & Gate Clock Timing (EQ = 2’b11, GNO = 2’b01, DIV = 2’b00) ..................................106 Figure 76 : normal scanning method (Line Inversion) ............................................................................................107 Figure 77 : 3-field interlaced scanning method.......................................................................................................107 Figure 78 : Grayscale control..................................................................................................................................108 Figure 79 : Structure of grayscale amplifier ............................................................................................................109 Figure 80 : Structure of Ladder / 8 to 1 selector .....................................................................................................110 Figure 81 : The operation of adjusting register .......................................................................................................111 Figure 82 : Relationship between RAM data and output voltage ...........................................................................120 Figure 83 : Relationship between source output and Vcom ...................................................................................121 Figure 84 : 8-color display control...........................................................................................................................122 Figure 85 : Set up procedure for the 8-color mode.................................................................................................123 Figure 86 : DISPLAY ON / OFF SEQUENCE.........................................................................................................124 Figure 87 : D-STAND-BY/STAND-BY / SLEEP SEQUENCE ................................................................................125 Figure 88 : Oscillation Circuit ..................................................................................................................................126 Figure 89 : Application Circuit .................................................................................................................................127 Figure 90 : DC characteristics.................................................................................................................................131 Figure 91 : AC characteristics of 68-system interface ............................................................................................132 Figure 92 : AC characteristics or 80-system interface ............................................................................................133 Figure 93 : AC Characteristics of RGB Interface ....................................................................................................134 Figure 94 : AC Characteristics of Serial Peripheral Interface .................................................................................135 Figure 95 : AC characteristics (RESET timing).......................................................................................................136 138 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY TABLES Table 1 : S6D0144 Pad Dimensions .......................................................................................................................... 9 Table 2 : Pad Center Coordinates ............................................................................................................................ 11 Table 3 : Pad Center Coordinates ............................................................................................................................ 12 Table 4 : Pad Center Coordinates ............................................................................................................................ 13 Table 5 : Pad Center Coordinates ............................................................................................................................ 14 Table 6 : Pad Center Coordinates ............................................................................................................................ 15 Table 7 : Pad Center Coordinates ............................................................................................................................ 16 Table 8 : Power supply pin description..................................................................................................................... 17 Table 9 : Power supply pin description (continued).................................................................................................. 18 Table 10 : System interface pin description.............................................................................................................. 19 Table 11 : RGB interface pin description (Continued) .............................................................................................. 20 Table 12 : Display pin description............................................................................................................................. 21 Table 13 : Oscillator and internal power regulator pin description ........................................................................... 21 Table 14 : DUMMY pin description ........................................................................................................................... 22 Table 15 : Register Selection (80/68-8/9/16/18bit CPU Interface) ........................................................................... 23 Table 16 : Register Selection (Serial Peripheral Interface) ...................................................................................... 23 Table 17 : Instruction table 1 .................................................................................................................................... 27 Table 18 : Instruction table 2 .................................................................................................................................... 28 Table 19 : DPL and DOTCLK polarity ...................................................................................................................... 30 Table 20 : EPL, ENABLE and RAM access ............................................................................................................. 30 Table 21 : NL bit and Drive Duty (SCN = “00000”)................................................................................................... 33 Table 22 : LCD inversion selection ........................................................................................................................... 34 Table 23 : LCD interlaced scanning method control ................................................................................................ 34 Table 24 : Multiple Data Transfer Mode Control....................................................................................................... 35 Table 25 : Address Direction Setting ........................................................................................................................ 37 Table 26 : Non-Displayed Area Control.................................................................................................................... 38 Table 27 : Gate Clock Control .................................................................................................................................. 38 Table 28 : Color Depth Control ................................................................................................................................. 39 Table 29 : Source Output Control in operation ......................................................................................................... 39 Table 30 : Source Output Control ............................................................................................................................. 39 Table 31 : Blank Period Control with FP and BP...................................................................................................... 40 Table 32 : Frame Frequency Control........................................................................................................................ 42 Table 33 : Clock Cycles per horizontal line .............................................................................................................. 42 Table 34 : RM and GRAM Access Interface............................................................................................................. 43 Table 35 : DM and Display Operation Mode ............................................................................................................ 43 Table 36 : RIM and RGB Interface Mode ................................................................................................................. 44 Table 37 : Current and Slew Rate Control................................................................................................................ 45 Table 38 : Step-Up Control ....................................................................................................................................... 46 Table 39 : Step-Up Control ....................................................................................................................................... 46 Table 40 : Current Control ........................................................................................................................................ 47 Table 41 : Operation Mode Summary ...................................................................................................................... 47 Table 42 : VCI1 voltage setting................................................................................................................................. 49 Table 43 : Internal Reference Voltage Control ......................................................................................................... 50 Table 44 : VCOMH Control....................................................................................................................................... 51 Table 45 : GVDD Control.......................................................................................................................................... 51 Table 46 : Vcom Amplitude Control .......................................................................................................................... 52 Table 47 : VcomH Control ........................................................................................................................................ 52 Table 48 : GRAM Address Range ............................................................................................................................ 53 Table 49 : Gate Scan Position Control ..................................................................................................................... 58 Table 50 : Split Screen Driving Function with SPT = 0............................................................................................. 62 Table 51 : Split Screen Driving Function with SPT = 1............................................................................................. 62 139 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY Table 52 : RADJ and Internal oscillator oscillation frequency ..................................................................................65 Table 53 : VGH,VGL DC/DC converter operation mode ..........................................................................................66 Table 54 : AVDD DC/DC converter operation while low power mode......................................................................66 Table 55 : VGH DC/DC converter operation while low power mode ........................................................................66 Table 56 : Equalization Control.................................................................................................................................67 Table 57 : Source Output Delay Control ...................................................................................................................67 Table 58 : Non-Overlap Period Control.....................................................................................................................68 Table 59 : Discharge Circuit Operation.....................................................................................................................74 Table 60 : Interface mode selection..........................................................................................................................75 Table 61 : System Interfaces of S6D0144 ................................................................................................................83 Table 62 : Start Byte Format.....................................................................................................................................92 Table 63 : RS and RWB Bit Function........................................................................................................................92 Table 64 : DISPLAY MODE & RAM ACCESS CONTROL .....................................................................................101 Table 65 : Gamma correction registers...................................................................................................................112 Table 66 : Gradient Adjustment ..............................................................................................................................113 Table 67 : Amplitude Adjustment(1)........................................................................................................................113 Table 68 : Amplitude Adjustment(2)........................................................................................................................113 Table 69 : Amplitude Adjustment(3)........................................................................................................................114 Table 70 : Relationship between Micro-adjustment Register and Selected Voltage ..............................................115 Table 71 : Gamma Adjusting Voltage Formula (Positive polarity) 1 .......................................................................116 Table 72 : Gamma Voltage Formula (Positive Polarity) 2.......................................................................................117 Table 73 : Gamma Adjusting Voltage Formula (Negative polarity) 1 .....................................................................118 Table 74 : Gamma Voltage Formula (Negative Polarity) 2 .....................................................................................119 Table 75 : Absolute Maximum Rating .....................................................................................................................128 Table 76 : DC Characteristics .................................................................................................................................129 Table 77 : DC Characteristics for LCD driver outputs.............................................................................................130 Table 78 : Reset Operation Regarding tRES Pulse Width .....................................................................................136 140 S6D0144 PRELIMINARY 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY REVISION HYSTORY S6D0144 Specification Revision History Version 0.0 0.1 0.2 0.3 Content Author Date Original 1. MDT function added. 2. PAD specification modified. 3. NL register description added. 4. Non-inversion mode added. 5. RIM description modified. 6. PREGB function deleted. 7. Register VR1C[R11h] added. 8. Register SVC added. 9. Register EXCLK_EN deleted. 10. Register RADJ bit width reduced. 1. VCM, VDV, VCOMG register modified. 2. Pad center coordinates added. 3. Pin description modified. - VSSO deleted. - AVSS VSSA - VSSA VSSC - IOVCCDUM Deleted - IOGNDDUM Deleted - TEST_MODE TEST_MODE2-0 - TEST_OUT TEST_OUT4-0 - RVDD pin description modified. - Pin TEST_IN4-0 added. 1. PAD configuration added. 2. PAD center coordinate added. 3. Pin description modified. - SDI pin description - SDO pin description - TEST_OUT4-1 pin description - TEST_MODE2-0 pin description - TEST_IN4-0 pin description - MTPD/MTPG pin description - PregB(DSTB_EN) pin description 4. PAD name changed. - TEST_OUT0 FLM/TEST_OUT0 - DUMMY EX_CLK - PregB DSTB_EN - MVDD VDDM 5. Application circuit Preliminary version added. 6. Table 53 “RADJ and Internal oscillator oscillation frequency” revised. 7. VRP0/VRN0 bit width changed. (Instruction table error) 8. R12h SVC register field changed. / description modified 9. R12h VCIREX_EN Deleted 10. Register for MTP function (R73h, RB3h, RB4h, RBDh) added. 11. R02h FL register description modified. 12. R07h PT register decription modified. 13. Deep Stand-by IN/OUT sequence added. J.S. Kang September 8, 2005 J.S. Kang September 26, 2005 H.J. Kim October 07, 2005 H.J. Kim October 26, 2005 141 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY 0.4 0.5 142 1. Output Bump size changed - 20x105 um^2 21x105 um^2 2. Pin name corrected. - Pin configuration : VSSO VSS - PAD Coordinates : VSSO VSS - Application circuit : VSSO VSS 3. PAD configuration “ Top View description” added. 4. R70h, R71h “Note” added. 5. COG align mark Coordinate added. 6. Pattern diagram changed - VREG1OUT “Note” added - VREGP VREFS - SVC3-0 added 7. Set up flow of Power Supply - SVC3-0 added 8. Oscillation circuit pin name changed OSC_MON EX_CLK 1. MTP Flow diagrams are added. 2. BP, FP Timing diagrams are added. 3. R01h NL register description modified. - NL = 5’b10011 NL=5’b10100 4. R42h SE1 register description modified. - SS1[7:0] ≤ SE1[7:0] ≤”13F”h SS1[7:0] ≤ SE1[7:0] ≤”9F”h 5. Timing Diagram FIG 75 modified - VCOM toggle timing inserted. 6. Interlace Scanning Function FIG 77, FIG 78 modified. 7. Absolue maximum rating added. - MTP maximum rewritable time added. 8. DC characteristic added. - MTP current specification added. - RON measurement condition modified. 9. R12h SVC table revised. - SVC[3-0]=”1100”~”1111” setting disable. 10. PAD name changed. - TEST_MODE2 TEST_MODE 11. Application circuit modified. - Increasing readability 12. VCOM setting section added. 13. EX_CLK pin description modified. - Operation clock range added. S6D0144 PRELIMINARY H.J. Kim October 27, 2005 J.S. Kang November 9, 2005 S6D0144 PRELIMINARY 0.6 0.7 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY 1. Figures of GS, SM are modified. 2. Graphic Operation Table (Table 36) is removed. 3. GRAM Data Alignment in 22h Description is removed. 4. Notation of equality is changed(“==” “=”) 5. Panel IF Timing Parameters using DOTCLK are removed. 6. PT Description is modified 7. Direction of TEST_MODE, NDT_EN is described. 8. INDEX width is expaned (7bits 8bits) 9. Relationship between DCCLK and DISP_CK is described. 10. Panel IF Timing Diagrams(Figure75, 77, 78) are modified. 11. Timing Diagram of BP, FP (Figure13) is modified. 12. RESET Initial Values are described. 13. VCOM Amplitude Control Table is modified. 14. Set-up Flow of Power Supply figure is modified. 15. Pattern Diagram And An Example Of Waveforms figure is moidfied. 16. Deep Stand-by IN/OUT sequence is modified. 17. DC Characteristics for LCD driver outputs Table is modified. - SAP=001 setting is removed. 18. RWB_RDB, E_WRB pin coordinates are changed. - PAD Center Coordinate Table is modified. - Application Circuit Figure is modified. - PAD Configuration Figure is modified. 19. Application Circuit is modified. - VCOMR external resistance is reduced. 20. MTPG, MTPD(21p) - Voltage range modified. 21. DC characteristic - MTPG, MTPD voltage condition added. - SAP=010 60us → 80us. 22. SAP - SAP=001 removed. 23. R13h PON description is revised. 24. R69h NLDC description is revised. 25. Voltage Regulation Function (Figure31) modified. 1.P27 Gamma control Gamma control register → Gamma control 2. P48 VR1C bit IB14 → IB15 3. P56 PRP5[2:0]~PRP2[2:0], PRN5[2:0]~PRN2[2:0] removed 4. P114 100000 → 10000 5. P116 SUMRN removed 6. P118 SUMRP removed 7. P117 table changed 8. P75 Interface mode selection function. - RBEh register set is added. 9. P106 Figure75 is modified - NO → GNO 10. P54 table is inserted - R22H → R22h 11. P31 Figure6 is modified. 12. P27 Table17 is modifed. J.S Kang December 12, 2005 C.W Park January 6, 2006 143 128-RGB X 160-DOT 1-CHIP DRIVER IC FOR 262,144-COLOR TFT-LCD DISPLAY S6D0144 PRELIMINARY NOTICE Precautions for Light Light has characteristics to move electrons in the integrated circuitry of semiconductors, therefore may change the characteristics of semiconductor devices when irradiated with light. Consequently, the users of the packages which may expose chips to external light such as COB, COG, TCP and COF must consider effective methods to block out light from reaching the IC on all parts of the surface area, the top, bottom and the sides of the chip. Follow the precautions below when using the products. 1. Consider and verify the protection of penetrating light to the IC at substrate (board or glass) or product design stage. 2. Always test and inspect products under the environment with no penetration of light. 144