M464S6453CKS PC133/PC100 SODIMM Revision History Revision 0.0 (Sept. 2001) Revision 0.1 (Feb. 2002) - Typo in SPD 127byte corrected This is to advise Samsung customers that, until August 1, 2003, in accordance with certain terms of an agreement, Samsung is prohibited from selling any DRAM products configured in "Multi-Die Plastic" format for use as components in general and scientific computers, such as mainframes, servers, work stations or desk top personal computers (hereinafter "Prohibited Computer Use"). Applications such as mobile, including cell phones, telecom, including televisions and display monitors, or non-desktop computer systems, including laptops, notebook computers, are, however, permissible. "Multi-Die Plastic" is defined as two or more Dram die encapsulated within a single plastic leaded package Rev. 0.1 Feb. 2002 M464S6453CKS PC133/PC100 SODIMM M464S6453CKS SDRAM SODIMM 64Mx64 SDRAM SODIMM based on 64Mx8, 4Banks, 8K Refresh,3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION FEATURE The Samsung M464S6453CKS is a 64M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung • Performance range M464S6453CKS consists of eight CMOS 64M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a 144-pin glass-epoxy substrate. Three 0.1uF decoupling capacitors are mounted on Part No. M464S6453CKS-L7A/C7A Max Freq. (Speed) 133MHz(7.5ns @CL=3) M464S6453CKS-L1H/C1H M464S6453CKS-L1L/C1L 100MHz (10ns @ CL=2) 100MHz (10ns @ CL=3) • • • • • Burst mode operation Auto & self refresh capability (8192 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V ± 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock • Serial presence detect with EEPROM • PCB : Height (1,200mil), double sided component the printed circuit board in parallel for each SDRAM. The M464S6453CKS is a Small Outline Dual In-line Memory Module and is intended for mounting into 144-pin M46S6453CKS edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. PIN CONFIGURATIONS (Front side/back side) Pin Front Pin Back Pin Front Pin Back 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 VSS DQ32 DQ33 DQ34 DQ35 V DD DQ36 DQ37 DQ38 DQ39 VSS DQM4 DQM5 V DD A3 A4 A5 VSS DQ40 DQ41 DQ42 DQ43 V DD DQ44 DQ45 51 53 55 57 59 DQ14 DQ15 V SS NC NC DQ46 DQ47 V SS NC NC V SS DQ0 DQ1 DQ2 DQ3 VD D DQ4 DQ5 DQ6 DQ7 V SS DQM0 DQM1 VD D A0 A1 A2 V SS DQ8 DQ9 DQ10 DQ11 VD D DQ12 DQ13 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 52 54 56 58 60 Pin 95 97 99 101 103 105 107 Voltage Key 109 CLK0 62 CKE0 111 VD D 64 VDD 113 RAS 66 CAS 115 WE 68 CKE1 117 CS0 70 A12 119 CS1 72 *A13 121 DU 74 CLK1 123 V SS 76 V SS 125 NC 78 NC 127 NC 80 NC 129 VD D 82 VDD 131 DQ16 84 DQ48 133 DQ17 86 DQ49 135 DQ18 88 DQ50 137 DQ19 90 DQ51 139 V SS 92 V SS 141 DQ20 94 DQ52 143 PIN NAMES Front Pin Back DQ21 DQ22 DQ23 VDD A6 A8 V SS A9 A10/AP VDD DQM2 DQM3 V SS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 V SS **SDA VDD 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 DQ53 DQ54 DQ55 V DD A7 BA0 VSS BA1 A11 V DD DQM6 DQM7 VSS DQ56 DQ57 DQ58 DQ59 V DD DQ60 DQ61 DQ62 DQ63 VSS **SCL V DD Pin Name Function A0 ~ A12 Address input (Multiplexed) BA0 ~ BA1 Select bank DQ0 ~ DQ63 Data input/output CLK0 ~ CLK1 Clock input CKE0 ~ CKE1 Clock enable input CS0 ~ CS1 Chip select input RAS Row address strobe CAS Column address strobe WE Write enable DQM0 ~ 7 DQM VD D Power supply (3.3V) VSS Ground SDA Serial data I/O SCL Serial clock DU Don′t use NC No connection * These pins are not used in this module. ** These pins should be NC in the system which does not support SPD. SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. Rev. 0.1 Feb. 2002 M464S6453CKS PC133/PC100 SODIMM PIN CONFIGURATION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. A0 ~ A12 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12, Column address : CA0 ~ CA9 BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM0 ~ 7 Data input/output mask Makes data output Hi-Z, tS H Z after the clock and masks the output. Blocks data input when DQM active. (Byte masking) D Q0 ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins. VDD /V SS Power supply/ground Power and ground for the input buffers and the core logic. Rev. 0.1 Feb. 2002 M464S6453CKS PC133/PC100 SODIMM FUNCTIONAL BLOCK DIAGRAM CKE1 CKE0 CS1 CS0 DQM0 DQM4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS0 CS1 CKE0CKE1 DQ0 DQ1 DQ2 DQ3 U0 DQ4 DQ5 DQ6 DQ7 DQM1 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM CS0 CS1 CKE0 CKE1 DQ0 DQ1 DQ2 DQ3 U4 DQ4 DQ5 DQ6 DQ7 DQM5 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM CS0 CS1 CKE0CKE1 DQ0 DQ1 DQ2 DQ3 U1 DQ4 DQ5 DQ6 DQ7 DQM2 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQM CS0 CS1 CKE0 CKE1 DQ0 DQ1 DQ2 DQ3 U5 DQ4 DQ5 DQ6 DQ7 DQM6 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM CS0 CS1 CKE0CKE1 DQ0 DQ1 DQ2 DQ3 U2 DQ4 DQ5 DQ6 DQ7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM CS0 CS1 CKE0 CKE1 DQ0 DQ1 DQ2 DQ3 U6 DQ4 DQ5 DQ6 DQ7 DQM7 DQM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQM CS0 CS1 CKE0CKE1 DQ0 DQ1 DQ2 DQ3 U3 DQ4 DQ5 DQ6 DQ7 A0 ~ A12, BA0 & 1 SDRAM U0 ~ U7 RAS SDRAM U0 ~ U7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQM CS0 CS1 CKE0 CKE1 DQ0 DQ1 DQ2 DQ3 U7 DQ4 DQ5 DQ6 DQ7 Serial PD SCL SDRAM U0 ~ U7 CAS 47KΩ WE WP SA0 SA1 SA2 SDA SDRAM U0 ~ U7 CKE0 & 1 SDRAM U0 ~ U7 10Ω DQn Every DQ pin of SDRAM • VDD CLK0/1 Three 0.1 uF X7R 0603 Capacitors per each SDRAM Vss To all SDRAMs • • U0/U4 U1/U5 U2/U6 U3/U7 Rev. 0.1 Feb. 2002 M464S6453CKS PC133/PC100 SODIMM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VI N, V OUT -1.0 ~ 4.6 V Voltage on VD D supply relative to Vss V DD , VDDQ -1.0 ~ 4.6 V TS T G -55 ~ +150 °C Power dissipation PD 16 W Short circuit current I OS 50 mA Storage temperature Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions (Voltage referenced to V SS = 0V, TA = 0 to 70 °C) Parameter Symbol Min Typ Max Unit Supply voltage VD D 3.0 3.3 3.6 V Input high voltage VI H 2.0 3.0 V DDQ +0.3 V 1 Input low voltage VIL -0.3 0 0.8 V 2 Output high voltage VO H 2.4 - - V IO H = -2mA Output low voltage V OL - - 0.4 V IOL = 2mA ILI -10 - 10 uA 3 Input leakage current Note Notes : 1. V IH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns. 2. V IL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ V IN ≤ V DDQ . Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE (V DD = 3.3V, T A = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV) Parameter Symbol Min Max Unit Input capacitance (A0 ~ A12 , BA0 ~ BA1) CIN1 45 90 pF Input capacitance (RAS, CAS, WE) CIN2 45 90 pF Input capacitance (CKE0 ~ CKE1) CIN3 35 60 pF Input capacitance (CLK0 ~ CLK1) CIN4 25 45 pF Input capacitance (CS0 ~ CS1) CIN5 35 60 pF Input capacitance (DQM0 ~ DQM7) CIN6 10 25 pF Data input/output capacitance (DQ0 ~ DQ63) COUT 15 30 pF Rev. 0.1 Feb. 2002 M464S6453CKS PC133/PC100 SODIMM DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Operating current (One bank active) Precharge standby current in power-down mode Symbol Active standby current in non power-down mode (One bank active) -7A -1H -1L 960 960 960 I CC1 Burst length = 1 tRC ≥ tRC (min) IO = 0 mA ICC2 P CKE ≤ V IL(max), t C C = 10ns 32 IC C 2PS CKE & CLK ≤ V IL(max), t C C =∞ 32 ICC2 N CKE ≥ V I H(min), CS ≥ VI H(min), t C C = 10ns Input signals are changed one time during 20ns ICC2NS CKE ≥ V I H(min), CLK ≤ V IL(max), t C C =∞ Input signals are stable Precharge standby current in non power-down mode Active standby current in power-down mode Version Test Condition Unit Note mA 1 mA 320 mA 160 CKE ≤ V IL(max), t C C = 10ns 96 IC C 3PS CKE & CLK ≤ V IL(max), t C C =∞ 96 ICC3 N CKE ≥ V I H(min), CS ≥ VI H(min), t C C = 10ns Input signals are changed one time during 20ns 480 mA ICC3NS CKE ≥ V I H(min), CLK ≤ V IL(max), t C C =∞ Input signals are stable 400 mA ICC3 P mA I CC4 IO = 0 mA Page burst 4Banks activated tCCD = 2CLKs 1120 1040 1040 mA 1 Refresh current I CC5 tRC ≥ tRC (min) 1840 1760 1760 mA 2 Self refresh current I CC6 CKE ≤ 0.2V Operating current (Burst mode) C 48 mA L 24 mA Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noted, input swing level is CMOS(VIH/V IL=V DDQ/V SSQ) Rev. 0.1 Feb. 2002 M464S6453CKS PC133/PC100 SODIMM AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70 °C) Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value Unit 2.4/0.4 V 1.4 V tr/tf = 1/1 ns 1.4 V See Fig. 2 3.3V Vtt = 1.4V 1200 Ω 50Ω VOH (DC) = 2.4V, I OH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output 870Ω Output Z0 = 50Ω 50pF 50pF (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Version Symbol -7A -1H -1L Unit Note Row active to row active delay t RRD (min) 15 20 20 ns 1 RAS to CAS delay t RCD (min) 20 20 20 ns 1 tRP (min) 20 20 20 ns 1 tRAS (min) 45 50 50 ns 1 Row precharge time Row active time tRAS (max) Row cycle time tR C(min) Last data in to row precharge tR D L(min) Last data in to Active delay 100 ns 1 2 CLK 2,5 t D A L(min) 2 CLK + 20 ns - 5 Last data in to new col. address delay tC D L(min) 1 CLK 2 Last data in to burst stop t B D L(min) 1 CLK 2 Col. address to col. address delay t CCD (min) 1 CLK 3 ea 4 Number of valid output data 65 70 us CAS latency=3 2 CAS latency=2 1 70 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. Rev. 0.1 Feb. 2002 M464S6453CKS PC133/PC100 SODIMM AC CHARACTERISTICS (AC operating conditions unless otherwise noted) REFER TO THE INDIVIDUAL COMPONENT, NOT THE WHOLE MODULE. Parameter -7A Symbol Min CLK cycle time CAS latency=3 tC C CAS latency=2 CLK to valid output delay CAS latency=3 Output data hold time CAS latency=3 7.5 -1H Max 1000 10 tSAC CAS latency=2 tO H CAS latency=2 Min 10 -1L Max 1000 10 Min 10 Unit Note ns 1 ns 1,2 ns 2 Max 1000 12 - 5.4 6 6 - 6 6 7 3 3 3 3 3 3 CLK high pulse width tC H 2.5 3 3 ns 3 CLK low pulse width tC L 2.5 3 3 ns 3 Input setup time tSS 1.5 2 2 ns 3 Input hold time tSH 0.8 1 1 ns 3 CLK to output in Low-Z tSLZ 1 1 1 ns 2 CLK to output in HiZ CAS latency=3 tSHZ CAS latency=2 5.4 6 6 6 6 7 ns Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. Rev. 0.1 Feb. 2002 M464S6453CKS PC133/PC100 SODIMM SIMPLIFIED TRUTH TABLE Command Register Mode register set Auto refresh Refresh CKEn-1 CKEn CS RAS CAS WE DQM H X L L L L X OP code L L L H X X H Entry Self refresh Exit H BA0,1 L H L H H H H X X X X L H H X V Read & column address Auto precharge disable H X L H L H X V Write & column address Auto precharge disable Auto precharge enable X L H L L X H X L H H L X H X L L H L X H L Exit L H Entry H L Precharge power down mode Exit L Column address (A 0 ~ A 8) V L Column address (A 0 ~ A 8) H All banks Entry L DQM H No operation command H H H X X X L V V V X X X X H X X X L H H H H X X X L V V V X X H X X X L H H H 3 Row address H Auto precharge enable Clock suspend or active power down 3 3 L Bank selection 1,2 X X H Note 3 H Precharge A 12, A11 A9 ~ A 0 L Bank active & row addr. Burst stop A 1 0/AP X V L X H 4 4,5 4 4,5 6 X X X X X X X V X X X 7 (V=Valid, X=Don′t care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA 1 : Bank select addresses. If both BA0 and BA 1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA 1 are "High" at read, write, row active and precharge, bank D is selected. If A10 /AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) Rev. 0.1 Feb. 2002 M464S6453CKS PC133/PC100 SODIMM PACKAGE DIMENSIONS Units : Inches (Millimeters) 2.66 (67.60) 2.50 (63.60) 0.24 (6.0) 0.79 (20.00) 0.16 ± 0.039 (4.00 ± 0.10) 1 59 61 0.91 (23.20) 0.13 (3.30) 143 2-φ 0.07 (1.80) 1.29 (32.80) 0.18 (4.60) 0.083 (2.10) 0.10 (2.50) 1.20 (30.48) 2-R 0.078 Min (2.00 Min) Z Y 0.15 (3.70) 60 62 144 (4.00 Min) 0.157 Min 0.125 Min (3.20 Min) 0.150 Max (3.80 Max) 0.04 ± 0.0039 (1.00 ± 0.10) 0.16 ± 0.0039 (4.00 ± 0.10) 0.06 ± 0.0039 (1.50 ± 0.1) Detail Z 0.100 Min (2.540 Min) 2 0.024 ± 0.001 (0.600 ± 0.050) 0.008 ±0.006 (0.200 ±0.150) 0.03 TYP (0.80 TYP) Detail Y Tolerances : ±.006(.15) unless otherwise specified The used device is 64Mx8 SDRAM, TSOP SDRAM Part No. : K4S510832C Rev. 0.1 Feb. 2002 M464S6453CKS PC133/PC100 SODIMM M464S6453CKS-L7A/L1H/L1L, C7A/C1H/C1L(Intel SPD 1.2B ver. based) •Organization : 64MX64 •Composition : 64MX8 *8 •Used component part # : K4S510832C-L7A/C7A/L1H/C1H/L1L/C1L •# of rows in module : 2 rows •# of banks in component : 4 banks •Feature : 1,200 mil height & double sided •Refresh : 8K/64ms •Contents : Byte # Function described Function Supported -7A 0 # of bytes written into serial memory at module manufacturer 1 Total # of bytes of SPD memory device 2 Fundamental memory type 3 4 5 -1H -1L Hex value -7A -1H Note -1L 128bytes 80h 256bytes (2K-bit) 08h SDRAM 04h # of row address on this assembly 13 0Dh 1 # of column address on this assembly 10 0Ah 1 # of module Rows on this assembly 2 Rows 02h 6 Data width of this assembly 64 bits 40h 7 ...... Data width of this assembly - 00h 8 Voltage interface standard of this assembly LVTTL 01h 9 SDRAM cycle time from clock @CAS latency of 3 7.5ns 10ns 10ns 75h A0h A0h 2 10 SDRAM access time from clock @CAS latency of 3 5.4ns 6ns 6ns 54h 60h 60h 2 11 DIMM configuration type 12 Refresh rate & type 13 Primary SDRAM width 14 Error checking SDRAM width 15 Minimum clock delay for back-to-back random column address 16 SDRAM device attributes : Burst lengths supported 17 SDRAM device attributes : # of banks on SDRAM device 18 SDRAM device attributes : CAS latency 19 SDRAM device attributes : CS latency 20 SDRAM device attributes : Write latency Non parity 00h 7.8us, support self refresh 82h x8 08h None 00h tCCD = 1CLK 01h 1, 2, 4, 8 & full page 8Fh 4 banks 04h 2&3 06h 0 CLK 01h 0 CLK 01h 00h 0Eh 21 SDRAM module attributes Non-buffered/Non-Registered & redundant addressing 22 SDRAM device attributes : General +/- 10% voltage toleance, Burst Read Single bit Write precharge all, auto precharge 23 SDRAM cycle time @CAS latency of 2 10ns 10ns 12ns A0h A0h C0h 2 24 SDRAM access time @CAS latency of 2 6ns 6ns 7ns 60h 60h 70h 2 25 SDRAM cycle time @CAS latency of 1 - 00h 2 26 SDRAM access time @CAS latency of 1 - 00h 2 27 Minimum row precharge time (=tRP ) 20ns 14h 28 Minimum row active to row active delay (t R R D) 29 Minimum RAS to CAS delay (=tRCD ) 30 Minimum activate precharge time (=tRAS ) 31 Module Row density 32 Command and Address signal input setup time 1.5ns 2ns 2ns 15h 20h 20h 33 Command and Address signal input hold time 0.8ns 1ns 1ns 08h 10h 10h 34 Data signal input setup time 1.5ns 2ns 2ns 15h 20h 20h 15ns 20ns 20ns 0Fh 20ns 45ns 50ns 14h 14h 14h 50ns 2Dh 2 Rows of 256MB 32ns 32ns 40h Rev. 0.1 Feb. 2002 M464S6453CKS PC133/PC100 SODIMM SERIAL PRESENCE DETECT INFORMATION Byte # 35 36~61 Function described Data signal input hold time SPD data revision code 63 Checksum for bytes 0 ~ 62 64 Manufacturer JEDEC ID code Hex value Note -7A -1H -1L -7A -1H -1L 0.8ns 1ns 1ns 08h 10h 10h Superset information (maybe used in future) 62 65~71 Function Supported - 00h Intel 1.2B 12h - ...... Manufacturer JEDEC ID code D3h 3Ah Samsung CEh 6Ah Samsung 00h Onyang Korea 01h Manufacturer part # (Memory module) M 4Dh Manufacturer part # (DIMM Configuration) 4 34h Blank 20h ...... Manufacturer part # (Data bits) 6 36h ...... Manufacturer part # (Data bits) 4 34h 78 Manufacturer part # (Mode & operating voltage) S 53h 79 Manufacturer part # (Module depth) 6 36h 80 ...... Manufacturer part # (Module depth) 4 34h 81 Manufacturer part # (Refresh, #of banks in Comp. & Inter- 5 35h 82 Manufacturer part # (Composition component) 3 33h 83 Manufacturer part # (Component revision) C 43h 84 Manufacturer part # (Package type) K 4Bh 85 Manufacturer part # (PCB revision & type) S 53h 86 Manufacturer part # (Hyphen) "-" 2Dh 87 Manufacturer part # (Power) 88 Manufacturer part # (Minimum cycle time) 7 1 1 37h 31h 31h 89 Manufacturer part # (Minimum cycle time) A H L 41h 48h 4Ch 90 Manufacturer part # (TBD) 91 Manufacturer revision code (For PCB) 92 ...... Manufacturer revision code (For component) 93 Manufacturing date (Year) 94 Manufacturing date (Week) 72 Manufacturing location 73 74 75 Manufacturer part # (Data bits) 76 77 95~98 Assembly serial # 99~12 Manufacturer specific data (may be used in future) 126 System frequency for 100MHz 127 Reserved 128+ Unused storage locations L/C 4Ch/43h Blank 20h S 53h C-die (4th Gen.) 43h - - 3 - - 3 - - 4 Undefined - 5 100MHz 64h 6 Detailed PC100 Information Undefined CFh CFh - CDh 6 5 Note : 1. The bank select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung ′s own Assembly Serial # system. All modules may have different unique serial #. 5. These bytes are Undefined and can be used for Samsung’s own purpose. 6. These values apply to PC100 applications only, per Intel PC66/PC100 SPD standards. Rev. 0.1 Feb. 2002