SAMSUNG M390S2858DT1-C7A

M390S2858DT1
PC133 Registered DIMM
M390S2858DT1 SDRAM DIMM
128Mx72 SDRAM DIMM with PLL & Register based on Stacked 128Mx4, 4Banks 8K Ref., 3.3V SDRAMs with SPD
GENERAL DESCRIPTION
FEATURE
The Samsung M390S2858DT1 is a 128M bit x 72 Synchronous Dynamic RAM high density memory module. The Samsung M390S2858DT1 consists of eighteen CMOS Stacked
128Mx4 bit Synchronous DRAMs in two TSOP-II 400mil packages, three 18-bits Drive ICs for input control signal, one PLL
in 24-pin TSSOP package for clock and one 2K EEPROM in 8pin TSSOP package for Serial Presence Detect on a 168-pin
glass-epoxy substrate. Two 0.22uF and one 0.0022uF decoupling capacitors are mounted on the printed circuit board in
parallel for each SDRAM. The M390S2858DT1 is a Dual Inline Memory Module and is intented for mounting into 168-pin
edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high
bandwidth, high performance memory system applications.
• Performance range
Part No.
M390S2858DT1-C7C
M390S2858DT1-C7A
•
•
•
•
•
Burst mode operation
Auto & self refresh capability (8192 Cycles/64ms)
LVTTL compatible inputs and outputs
Single 3.3V ± 0.3V power supply
MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4 , 8 & Full page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
system clock
• Serial presence detect with EEPROM
• PCB : Height (1,700mil), double sided component
PIN CONFIGURATIONS (Front side/back side)
PIN NAMES
Pin
Front
Pin
Pin
Front
Pin
Back
Pin
Back
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
CB0
CB1
VSS
NC
NC
VDD
WE
DQM0
29 DQM1 57
58
CS0
30
59
31
DU
60
32
VSS
61
33
A0
62
34
A2
63
35
A4
64
36
A6
65
37
A8
38 A10/AP 66
67
39
BA1
68
40
VDD
69
41
VDD
42 CLK0 70
71
43
VSS
44
DU
72
73
45
CS2
46 DQM2 74
47 DQM3 75
76
48
DU
77
49
VDD
78
50
NC
79
51
NC
80
52
CB2
81
53
CB3
82
54
VSS
55 DQ16 83
56 DQ17 84
DQ18
DQ19
VDD
DQ20
NC
*VREF
*CKE1
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
*CLK2
NC
*WP
**SDA
**SCL
VDD
VSS
85
86 DQ32
87 DQ33
88 DQ34
89 DQ35
VDD
90
91 DQ36
92 DQ37
93 DQ38
94 DQ39
95 DQ40
96
VSS
97 DQ41
98 DQ42
99 DQ43
100 DQ44
101 DQ45
102 VDD
103 DQ46
104 DQ47
105 CB4
106 CB5
107
VSS
108
NC
NC
109
110 VDD
111 CAS
112 DQM4
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
DQM5
CS1
RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VDD
*CLK1
A12
VSS
CKE0
CS3
DQM6
DQM7
*A13
VDD
NC
NC
CB6
CB7
VSS
DQ48
DQ49
141 DQ50
142 DQ51
143 VDD
144 DQ52
NC
145
146 *VREF
147 REGE
VSS
148
149 DQ53
150 DQ54
151 DQ55
VSS
152
153 DQ56
154 DQ57
155 DQ58
156 DQ59
157 VDD
158 DQ60
159 DQ61
160 DQ62
161 DQ63
162
VSS
163 *CLK3
NC
164
165 **SA0
166 **SA1
167 **SA2
168 VDD
Front
Max Freq. (Speed)
133MHz(7.5ns @ CL=2)
133MHz (7.5ns @ CL=3)
Back
Pin Name
Function
A0 ~ A12
Address input (Multiplexed)
BA0 ~ BA1
Select bank
DQ0 ~ DQ63
Data input/output
CB0 ~ CB7
Check bit (Data-in/data-out)
CLK0
Clock input
CKE0
Clock enable input
CS0 ~ CS3
Chip select input
RAS
Row address strobe
CAS
Colume address strobe
WE
Write enable
DQM0 ~ 7
DQM
VDD
Power supply (3.3V)
VSS
Ground
*VREF
Power supply for reference
REGE
Register enable
SDA
Serial data I/O
SCL
Serial clock
SA0 ~ 2
Address in EEPROM
DU
Don′t use
NC
No connection
*WP
Write protection
* These pins are not used in this module.
** These pins should be NC in the system
which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
REV. 0.0 Jan. 2002
M390S2858DT1
PC133 Registered DIMM
PIN CONFIGURATION DESCRIPTION
Pin
Name
Input Function
CLK
System clock
Active on the positive going edge to sample all inputs.
CS
Chip select
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tss prior to valid command.
A0 ~ A12
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9, CA11
BA0 ~ BA1
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column address strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM0 ~ 7
Data input/output mask
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
REGE
Register enable
The device operates in the transparent mode when REGE is low. When REGE is high,
the device operates in the registered mode. In registered mode, the Address and control inputs are latched if CLK is held at a high or low logic level. the inputs are stored in
the latch/flip-flop on the rising edge of CLK. REGE is tied to VDD through 10K ohm
Resistor on PCB. So if REGE of module is floating, this module will be operated as registered mode.
DQ0 ~ 63
Data input/output
Data inputs/outputs are multiplexed on the same pins.
CB0 ~ 7
Check bit
Check bits for ECC.
VDD/VSS
Power supply/ground
Power and ground for the input buffers and the core logic.
REV. 0.0 Jan. 2002
M390S2858DT1
PC133 Registered DIMM
FUNCTIONAL BLOCK DIAGRAM
BCS1,B2CKE0
BCS0,B0CKE0
PCLK0
B0RAS,B0CAS,B0WE,B0BA0,B0BA1
B0A0~B0A12
BDQM0
DQ0~3
10Ω
PCLK1
CLK
CS1,CKE D0L
CTL
Add
DQM
DQ0~3
CLK
CS0,CKE D0U
CTL
Add
DQM
DQ0~3
CLK
CS1,CKE D1L
CTL
Add
DQM
DQ0~3
CLK
CS0,CKE D1U
CTL
Add
DQM
DQ0~3
CLK
CS1,CKE D2L
CTL
Add
DQM
DQ0~3
CLK
CS0,CKE D2U
CTL
Add
DQM
DQ0~3
CLK
CS1,CKE D3L
CTL
Add
DQM
DQ0~3
CLK
CS0,CKE D3U
CTL
Add
DQM
DQ0~3
CLK
CS1,CKE D4L
CTL
Add
DQM
DQ0~3
CLK
CS0,CKE D4U
CTL
Add
DQM
DQ0~3
BDQM4
DQ32~35
CLK
CS1,CKE D9U
CTL
Add
DQM
DQ0~3
D9L
10Ω
DQ4~7
DQ36~39
10Ω
CLK
CS0,CKE D10L
CTL
Add
DQM
DQ0~3
CLK
CS1,CKED10U
CTL
Add
DQM
DQ0~3
CLK
CS0,CKE D11L
CTL
Add
DQM
DQ0~3
CLK
CS1,CKED11U
CTL
Add
DQM
DQ0~3
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D12L
CLK
CS1,CKED12U
CTL
Add
DQM
DQ0~3
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D13L
CLK
CS1,CKED13U
CTL
Add
DQM
DQ0~3
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D14L
CLK
CS1,CKED14U
CTL
Add
DQM
DQ0~3
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D15L
CLK
CS1,CKE D15U
CTL
Add
DQM
DQ0~3
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D16L
CLK
CS1,CKED16U
CTL
Add
DQM
DQ0~3
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D17L
CLK
CS1,CKED17U
CTL
Add
DQM
DQ0~3
10Ω
PCLK2
BDQM1
DQ8~11
10Ω
PCLK3
BDQM5
DQ40~43
10Ω
DQ12~15
10Ω
PCLK4
DQ44~47
10Ω
CB0~3
CB4~7
10Ω
10Ω
BCS3,B3CKE0
BCS2,B1CKE0
PCLK5
BDQM2
DQ16~19
CLK
CS1,CKE D5L
CTL
Add
DQM
DQ0~3
CLK
CS0,CKE D5U
CTL
Add
DQM
DQ0~3
CLK
CS1
CTL
Add
DQM
DQ0~3
CLK
CS0,CKE D6U
CTL
Add
DQM
DQ0~3
BDQM6
DQ48~51
10Ω
10Ω
PCLK6
DQ20~23
D6L
DQ52~55
10Ω
10Ω
PCLK7
BDQM3
DQ24~27
10Ω
PCLK8
CLK
CS1,CKE D7L
CTL
Add
DQM
DQ0~3
CLK
CS0,CKE D7U
CTL
Add
DQM
DQ0~3
CLK
CS1,CKE D8L
CTL
Add
DQM
DQ0~3
CLK
CS0,CKE D8U
CTL
Add
DQM
DQ0~3
BDQM7
DQ56~59
10Ω
B1RAS,B1CAS,B1WE,B1BA0,B1BA1
B1A0~B1A12
DQ28~31
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
10Ω
DQ60~63
10Ω
VSS
VDD
74ALVCF162835
10Ω
G
AGND
AVDD
B0A3~B0A10,B0BA0
B1A3~B1A10,B1BA0
A3~A10,BA0
CLK1,2,3
VDD
12pF
CDCF2510
10kΩ
PCLK9
REGE
LE
10Ω
OE
74ALVCF162835
CS2,CS3
CKE0
BCS2,BCS3
B0CKE0,B1CKE0
B2CKE0,B3CKE0
BDQM2,3,6,7
DQM2,3,6,7
LE
12pF
PCLK0
PCLK1
PCLK2
PCLK3
PCLK4
PCLK5
PCLK6
PCLK7
PCLK8
PCLK9
FBOUT
*1
Cb
Note
1. The actual values of Cb will depend upon the PLL chosen.
OE
A0,A1,A2
B0A0,B0A1,B0A2
B1A0,B1A1,B1A2
B0RAS, B0CAS, B0WE
B1RAS, B1CAS, B1WE
BCS0,BCS1
BDQM0,1,4,5
74ALVCF162835
RAS,CAS,WE
CS0,CS1
DQM0,1,4,5
LE
CLK
FBIN
CLK0
B0A11,B0A12.B0BA1
B1A11,B1A12.B1BA1
A11,A12,BA1
IY0
IY1
IY2
IY3
IY4
IY5
IY6
IY7
IY8
IY9
OE
Serial PD
SCL
47KΩ
WP
A0
SDA
A1
A2
SA0 SA1 SA2
REV. 0.0 Jan. 2002
M390S2858DT1
PC133 Registered DIMM
STANDARD TIMING DIAGRAM WITH PLL & REGISTER (CL=2, BL=4)
*2
REG
*1
*3 D
Control Signal(RAS,CAS,WE)
OUT
*1. Register Input
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
RAS
CAS
WE
*2. Register Output
RAS
td
tr
td
tr
CAS
WE
*3. SDRAM
CAS latency(refer to *1)
=2CLK+1CLK
1CLK
tSAC
tRAC(refer to *1)
DQ
Qa0
tRAC(refer to *2)
Row Active
Read
Command
Qa1
Qa2
Qa3
Db0
Db1
CAS latency(refer to *2)
=2CLK
Precharge
Command
Db2
Db3
tRDL
Row Active
Write
Command
Precharge
Command
td, tr = Delay of register (74ALVCF162835)
Notes : 1. In case of module timing, command cycles delayed 1CLK with respect to external input timing at the address and input signal
because of the buffering in register (74ALVCF162835). Therefore, Input/Output signals of read/write function should be
issued 1CLK earlier as compared to Unbuffered DIMMs.
2. DIN is to be issued 1clock after write command in external timing because DIN is issued directly to module.
: Don′t care
REV. 0.0 Jan. 2002
M390S2858DT1
PC133 Registered DIMM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
VIN, VOUT
-1.0 ~ 4.6
V
Voltage on VDD supply relative to Vss
VDD, VDDQ
-1.0 ~ 4.6
V
TSTG
-55 ~ +150
°C
Power dissipation
PD
36
W
Short circuit current
IOS
50
mA
Storage temperature
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VDD
3.0
3.3
3.6
V
Input high voltage
VIH
2.0
3.0
VDDQ+0.3
V
1
Input low voltage
VIL
-0.3
0
0.8
V
2
Output high voltage
VOH
2.4
-
-
V
IOH = -2mA
Output low voltage
VOL
-
-
0.4
V
IOL = 2mA
ILI
-10
-
10
uA
3
Input leakage current
Note
Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0 ~ A12)
CIN1
-
15
pF
Input capacitance (RAS, CAS, WE)
CIN2
-
15
pF
Input capacitance (CKE0)
CIN3
-
15
pF
Input capacitance (CLK0)
CIN4
-
20
pF
Input capacitance (CS0, CS2)
CIN5
-
15
pF
Input capacitance (DQM0 ~ DQM7)
CIN6
-
15
pF
Input capacitance (BA0 ~ BA1)
CIN7
-
15
pF
Data input/output capacitance (DQ0 ~ DQ63)
COUT
-
22
pF
Data input/output capacitance (CB0 ~ CB7)
COUT1
-
22
pF
REV. 0.0 Jan. 2002
M390S2858DT1
PC133 Registered DIMM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Operating current
(One bank active)
Precharge standby current in
power-down mode
Symbol
ICC1
Burst length =1
tRC ≥ tRC(min)
IO = 0 mA
-7C
-7A
2840
2660
CKE ≤ VIL(max), tCC = 10ns
422
ICC2PS
CKE & CLK ≤ VIL(max), tCC = ∞
74
ICC2N
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
ICC2P
Precharge standby current in
non power-down mode
Unit
Note
mA
1
mA
3
mA
3
mA
3
1070
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
362
CKE ≤ VIL(max), tCC = 10ns
566
ICC3PS
CKE & CLK ≤ VIL(max), tCC = ∞
218
ICC3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
1430
mA
3
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
902
mA
3
ICC2NS
Active standby current in
power-down mode
Version
Test Condition
ICC3P
Active standby current in
non power-down mode
ICC3NS
ICC4
IO = 0mA
Page Burst
4 Banks activated
tCCD=2CLK
3020
3020
mA
1
Refresh current
ICC5
tRC ≥ tRC(min)
5000
4640
mA
2
Self refresh current
ICC6
CKE ≤ 0.2V
mA
3
Operating current
(Burst mode)
458
Notes : 1. Measured with outputs open.
2. Refresh period is 64ms.
3. Measured with 1 PLL & 3 Drive ICs.
4. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ)
REV. 0.0 Jan. 2002
M390S2858DT1
PC133 Registered DIMM
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
Unit
2.4/0.4
V
1.4
V
tr/tf = 1/1
ns
1.4
V
See Fig. 2
3.3V
Vtt = 1.4V
1200Ω
50Ω
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
870Ω
Output
Z0 = 50Ω
50pF
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Version
Symbol
-7C
-7A
Unit
Note
Row active to row active delay
tRRD(min)
15
15
ns
1
RAS to CAS delay
tRCD(min)
15
20
ns
1
Row precharge time
tRP(min)
15
20
ns
1
Row active time
tRAS(min)
45
45
ns
1
tRAS(max)
Row cycle time
tRC(min)
Last data in to row precharge
tRDL(min)
Last data in to Active delay
100
ns
1
2
CLK
2,5
tDAL(min)
2 CLK + tRP
-
5
Last data in to new col. address delay
tCDL(min)
1
CLK
2
Last data in to burst stop
tBDL(min)
1
CLK
2
Col. address to col. address delay
tCCD(min)
1
CLK
3
CAS latency=3
2
ea
4
CAS latency=2
1
Number of valid output data
Notes :
60
us
65
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
REV. 0.0 Jan. 2002
M390S2858DT1
PC133 Registered DIMM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.
Parameter
-7C
Symbol
Min
CLK cycle time
CAS latency=3
tCC
CAS latency=2
CLK to valid
output delay
CAS latency=3
Output data
hold time
CAS latency=3
7.5
-7A
Max
1000
7.5
tSAC
CAS latency=2
tOH
CAS latency=2
Min
7.5
Unit
Note
ns
1
ns
1,2
ns
2
Max
1000
10
5.4
5.4
5.4
6
3
3
3
3
CLK high pulse width
tCH
2.5
2.5
ns
3
CLK low pulse width
tCL
2.5
2.5
ns
3
Input setup time
tSS
1.5
1.5
ns
3
Input hold time
tSH
0.8
0.8
ns
3
CLK to output in Low-Z
tSLZ
1
1
ns
2
CLK to output
in Hi-Z
CAS latency=3
CAS latency=2
tSHZ
5.4
5.4
5.4
6
ns
Notes : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
REV. 0.0 Jan. 2002
M390S2858DT1
PC133 Registered DIMM
SIMPLIFIED TRUTH TABLE
Command
Register
Mode register set
Auto refresh
Refresh
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
H
X
L
L
L
L
X
OP code
L
L
L
H
X
X
H
Entry
Self
refresh
Exit
H
BA0,1
L
H
L
H
H
H
H
X
X
X
X
L
H
H
X
V
Read &
column address
Auto precharge disable
H
X
L
H
L
H
X
V
Write &
Column Address
Auto precharge disable
Auto precharge enable
X
L
H
L
L
X
H
X
L
H
H
L
X
H
X
L
L
H
L
X
H
L
Exit
L
H
Entry
H
L
Precharge power down mode
Exit
Column
address
(A0~A9, A11)
L
V
L
Column
address
(A0~A9, A11)
H
All banks
Entry
L
DQM
H
No operation command
H
H
X
H
X
X
X
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
H
X
X
X
L
H
H
H
3
Row address
H
Auto precharge enable
Clock suspend or
active power down
3
3
L
Bank selection
1,2
X
X
H
Note
3
H
Precharge
A12,A11,
A 9 ~ A0
L
Bank active & row addr.
Burst stop
A10/AP
X
V
L
X
H
4
4,5
4
4,5
6
X
X
X
X
X
X
X
V
X
X
X
7
(V=Valid, X=Don′t care, H=Logic high, L=Logic low)
Notes : 1. OP Code : Operand code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
REV. 0.0 Jan. 2002
M390S2858DT1
PC133 Registered DIMM
PACKAGE DIMENSIONS
Units : Inches (Millimeters)
5.250
(133.350)
0.054
(1.372)
5.014
(127.350)
0.118
(3.000)
R 0.079
(R 2.000)
0.250
(6.350)
.450
(11.430)
0.700
(17.780)
PLL
B
A
.118DIA ± 0.004
(3.000DIA ± 0.100)
0.350
(8.890)
REG
C
0.100 Min
REG
0.250
(6.350)
1.450
(36.830)
2.150
(54.61)
(2.540 Min)
0.118
(3.000)
1.700
(43.18)
0.157 ± 0.004
(4.000 ± 0.100)
4.550
(115.57)
0.254 Max
(6.452 Max)
0.157 Min
(3.99 Min)
REG
0.100 Min
0.250
(6.350)
0.250
(6.350)
0.123 ± 0.005
(3.125 ± 0.125)
0.079 ± 0.004
(2.000 ± 0.100)
Detail A
(2.540 Min)
0.050 ± 0.0039
(1.270 ± 0.10)
0.039 ± 0.002
(1.000 ± 0.050)
0.123 ± 0.005
(3.125 ± 0.125)
0.079 ± 0.004
(2.000 ± 0.100)
Detail B
0.008 ± 0.006
(0.200 ± 0.150)
0.050
(1.270)
Detail C
Tolerances : ± 0.005(.13) unless otherwise specified
SDRAM Part No. : K4S510632D
- The used device is stacked 128Mx4 SDRAM
- Staktek’s stacking technology is Samsung’s stacking technology of choice
This module is based on JEDEC PC133 Specification
REV. 0.0 Jan. 2002
M390S2858DT1
PC133 Registered DIMM
M390S2858DT1-C7A/C7C
•Organization : 128MX72
•Composition : 128MX4 * 18ea
•Used component part # : K4S510632D-TC75/C7C
•# of banks in module : 2 Rows
•# of banks in component : 4 banks
•Feature : 1,700 mil height & double sided
•Refresh : 8K/64ms
•Contents :
Byte #
Function described
Function Supported
-7C
-7A
Hex value
-7C
Note
-7A
0
# of bytes written into serial memory at module manufacturer
1
Total # of bytes of SPD memory device
128bytes
80h
256bytes (2K-bit)
08h
2
Fundamental memory type
SDRAM
04h
3
# of row address on this assembly
13
0Dh
1
4
# of column address on this assembly
11
0Bh
1
5
# of module Rows on this assembly
2 Rows
02h
6
Data width of this assembly
72 bits
48h
7
...... Data width of this assembly
-
00h
8
Voltage interface standard of this assembly
LVTTL
01h
9
SDRAM cycle time from clock @CAS latency of 3
7.5ns
75h
2
10
SDRAM access time from clock @CAS latency of 3
5.4ns
54h
2
11
DIMM configuration type
ECC
02h
12
Refresh rate & type
7.8us, support self refresh
82h
13
Primary SDRAM width
x4
04h
14
Error checking SDRAM width
x4
04h
15
Minimum clock delay for back-to-back random column address
tCCD = 1CLK
01h
16
SDRAM device attributes : Burst lengths supported
1, 2, 4, 8 & full page
8Fh
17
SDRAM device attributes : # of banks on SDRAM device
4 banks
04h
18
SDRAM device attributes : CAS latency
2&3
06h
19
SDRAM device attributes : CS latency
0 CLK
01h
20
SDRAM device attributes : Write latency
0 CLK
01h
21
SDRAM module attributes
Registered/Buffered DQM,
1Fh
address & control inputs and
On-card PLL
+/- 10% voltage tolerance,
22
SDRAM device attributes : General
0Eh
Burst Read Single bit Write
precharge all, auto precharge
23
SDRAM cycle time @CAS latency of 2
7.5ns
10ns
75h
A0h
2
24
SDRAM access time @CAS latency of 2
5.4ns
6ns
54h
60h
2
25
SDRAM cycle time @CAS latency of 1
-
-
00h
00h
2
26
SDRAM access time @CAS latency of 1
-
-
00h
00h
2
27
Minimum row precharge time (=tRP)
15ns
20ns
0Fh
14h
0Fh
28
Minimum row active to row active delay (tRRD)
15ns
15ns
0Fh
29
Minimum RAS to CAS delay (=tRCD)
15ns
20ns
0Fh
14h
30
Minimum activate precharge time (=tRAS)
45ns
45ns
2Dh
2Dh
31
Module Row density
2 Rows of 512MB
80h
32
Command and Address signal input setup time
1.5ns
15h
33
Command and Address signal input hold time
0.8ns
08h
34
Data signal input setup time
1.5ns
15h
REV. 0.0 Jan. 2002
M390S2858DT1
PC133 Registered DIMM
SERIAL PRESENCE DETECT INFORMATION
Byte #
Function described
Function Supported
-7C
35
36~61
Data signal input hold time
Superset information (maybe used in future)
62
SPD data revision code
63
Checksum for bytes 0 ~ 62
64
65~71
-7A
Hex value
-7C
0.8ns
08h
-
00h
JEDEC 2
Note
-7A
02h
-
ECh
2Dh
Manufacturer JEDEC ID code
Samsung
CEh
...... Manufacturer JEDEC ID code
Samsung
00h
Onyang Korea
01h
4Dh
72
Manufacturing location
73
Manufacturer part # (Memory module)
M
74
Manufacturer part # (DIMM Configuration)
3
33h
75
Manufacturer part # (Data bits)
Blank
20h
76
...... Manufacturer part # (Data bits)
9
39h
77
...... Manufacturer part # (Data bits)
0
30h
78
Manufacturer part # (Mode & operating voltage)
S
53h
79
Manufacturer part # (Module depth)
2
32h
80
...... Manufacturer part # (Module depth)
8
38h
81
Manufacturer part # (Refresh, #of banks in Comp. & Inter-
5
35h
82
Manufacturer part # (Composition component)
8
38h
83
Manufacturer part # (Component revision)
D
44h
54h
84
Manufacturer part # (Package type)
T
85
Manufacturer part # (PCB revision & type)
1
31h
86
Manufacturer part # (Hyphen)
"-"
2Dh
87
Manufacturer part # (Power)
88
Manufacturer part # (Minimum cycle time)
7
7
37h
37h
89
Manufacturer part # (Minimum cycle time)
C
A
43h
41h
90
Manufacturer part # (TBD)
91
Manufacturer revision code (For PCB)
92
...... Manufacturer revision code (For component)
93
Manufacturing date (Year)
94
Manufacturing date (Week)
95~98
Assembly serial #
99~125
Manufacturer specific data (may be used in future)
C
43h
Blank
20h
1
31h
D-die (5th Gen.)
44h
-
-
3
-
-
3
-
-
4
Undefined
-
5
100MHz
64h
126
System frequency for 100MHz
127
Intel Specification details
Detailed 100MHz Information
8Fh
128+
Unused storage locations
Undefined
-
5
Note : 1. The row select address is excluded in counting the total # of addresses.
2. This value is based on the component specification.
3. These bytes are programmed by code of Date Week & Date Year with BCD format.
4. These bytes are programmed by Samsung ′s own Assembly Serial # system. All modules may have different unique serial #.
5. These bytes are Undefined and can be used for Samsung’s own purpose.
REV. 0.0 Jan. 2002