VBUS054CD-FHI www.vishay.com Vishay Semiconductors 4-Line BUS-Port ESD-Protection - Flow Through Design FEATURES nc. 10 nc. GND 8 9 nc. 7 • Compact LLP2513-11L package nc. 6 • Low package height < 0.6 mm • 4-line ESD-protection 11 21326 1 2 • Low leakage current IR < 0.1 μA 3 4 • Low load capacitance CD = 0.8 pF 5 D1 + D1 - GND D2 + D2 - • Ideal for high speed data line like - HDMI, DisplayPort, eSATA - USB, 1394/firewire 21324 • ESD-protection acc. IEC 61000-4-2 ± 15 kV contact discharge ± 15 kV air discharge MARKING (example only) • Soldering can be checked by standard vision inspection. No X-ray necessary YYXX 20720 • e4 - precious metal (e.g. Ag, Au, NiPd, NiPdAu) (no Sn) Dot = pin 1 marking YY = type code (see table below) XX = date code • Material categorization: For definitions of compliance please see www.vishay.com/doc?99912 ORDERING INFORMATION ORDERING CODE TAPED UNITS PER REEL (8 mm TAPE ON 7" REEL) MINIMUM ORDER QUANTITY VBUS054CD-FHI-GS08 3000 15 000 DEVICE NAME VBUS054CD-FHI PACKAGE DATA DEVICE NAME PACKAGE NAME VBUS054CD-FHI LLP2513-11L TYPE CODE WEIGHT MOLDING COMPOUND FLAMMABILITY RATING MOISTURE SENSITIVITY LEVEL SOLDERING CONDITIONS 9X 5.5 mg UL 94 V-0 MSL level 1 (according J-STD-020) 260 °C/10 s at terminals ABSOLUTE MAXIMUM RATINGS PARAMETER TEST CONDITIONS SYMBOL VALUE Peak pulse current Acc. IEC 61000-4-5; tP = 8/20 μs; single shot IPPM 3.5 A Peak pulse power Acc. IEC 61000-4-5; tP = 8/20 μs; single shot PPP 45 W Contact discharge acc. IEC 61000-4-2; 10 pulses VESD ± 15 kV Air discharge acc. IEC 61000-4-2; 10 pulses VESD ± 15 kV Junction temperature TJ - 40 to + 125 °C TSTG - 55 to + 150 °C ESD immunity Operating temperature Storage temperature Rev. 1.4, 31-May-12 UNIT Document Number: 81882 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS054CD-FHI www.vishay.com Vishay Semiconductors ELECTRICAL CHARACTERISTICS (pin 1, 2, 4 or 5 to pin 3) (Tamb = 25 °C, unless otherwise specified) PARAMETER TEST CONDITIONS/REMARKS SYMBOL MIN. TYP. MAX. UNIT Number of lines which can be protected Nchannel - - 4 lines Max. reverse working voltage VRWM - - 5 V Reverse voltage at IR = 0.1 μA VR 5 - - V Reverse current at VRWM = 5 V IR - < 0.01 0.1 μA at IR = 1 mA VBR 6.9 7.9 8.7 V at IPP = 1 A VC - 9.1 11 V at IPP = IPPM = 3.5 A VC - 11.6 13 V at IPP = 1 A VF - 1.6 2.4 V at IPP = 3.5 A VF - 3.5 5 V at VR = 0 V; f = 1 MHz CD - 0.8 1 pF Protection paths Reverse stand-off voltage Reverse breakdown voltage Reverse clamping voltage Forward clamping voltage Capacitance APPLICATION NOTE The VBUS054CD-FHI is a four-line ESD-protection device with the characteristic of a Z-diode with a high ESD-immunity and a very low capacitance which makes it usable for high frequency applications like USB2.0 or HDMI. With the VBUS054CD-FHI four high speed data lines can be protected against transient voltage signals like ESD (Electro Static Discharge). Connected to the data line (pin 1, 2 and pin 4, 5) and to ground (pin 3, 8 and 11) negative transients will be clamped close below the ground level while positive transients will be clamped close above the 5 V working range. The clamping behaviour of the VBUS054CD-FHI is bidirectional but asymmetrical (BiAs) and so it offers the best protection for applications running up to 5 V. Pin configuration: • Pin 3, 8 and 11 are internally shorted and have to be connected to ground • Pin 1, 2 and 4, 5 are the inputs for the data lines D1+ and D1- and D2+ and D2• Pin 6, 7 and 9, 10 are not connected internally USB/HDMI Interface nc. 7 nc. 6 4 5 D1 + D1 - 11 21326 1 2 3 D2 + D2 - 10 matched pair nc. GND 8 9 matched pair nc. 10 9 D1 + D1 - GND D2 + D2 - 8 7 6 4 5 11 1 2 3 D1 + D1 - GND D2 + D2 - I/O Port Connector 21328 FLOW THROUGH DESIGN Modern digital transmission lines can be clocked up to 480 Mbit/s (USB2.0) or 1.65 Gbit/s (HDMI). At such high data rates the transmission lines like cables or the line traces on the PCBs have to be very homogeneous regarding their surge impedance. This requires well defined trace dimensions as trace width and distance which have to be calculated depending on the requested surge impedance (e.g. 50 ) and the PCB material and layer dimensions. Any device connected to the data lines - like ESD-protection devices - have to be connected with minimal changes in these trace dimensions and distances. With the package in the so called “Flow Through Design” this is possible. The lines are running straight along the PCB while the VBUS054CD-FHI is placed on top without any vias or loops. Rev. 1.4, 31-May-12 Document Number: 81882 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS054CD-FHI www.vishay.com Vishay Semiconductors TYPICAL CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) 100 120 % Rise time = 0.7 ns to 1 ns Discharge Current IESD 100 % 10 80 % 1 IF (mA) 60 % 53 % 0.1 40 % Pin 3 to Pin 1, 2, 4 or 5 27 % 0.01 20 % 0.001 0.5 0% - 10 0 10 20 30 40 50 60 70 80 90 100 0.6 0.7 0.8 Fig. 1 - ESD Discharge Current Wave Form acc. IEC 61000-4-2 (330 /150 pF) 0.9 1 1.1 VF (V) 22349 Time (ns) 20557 Fig. 4 - Typical Forward Current IF vs. Forward Voltage VF 9 8 µs to 100 % 100 % 8 7 80 % VR (V) 6 IPPM 60 % 20 µs to 50 % 40 % Pin 1, 2, 4 or 5 to Pin 3 5 4 3 2 20 % 1 0% 0 10 20 30 0 0.01 40 Time (µs) 20548 Fig. 2 - 8/20 μs Peak Pulse Current Wave Form acc. IEC 61000-4-5 2.0 1 10 100 1000 10 000 IR (µA) Fig. 5 - Typical Reverse Voltage VR vs. Reverse Current IR 14 f = 1 MHz Measured acc. IEC 61000-4-5 (8/20µs - wave form) 1.8 12 Pin 1, 2, 4 or 5 to Pin 3 1.6 10 1.4 1.2 VC (V) CD (pF) 0.1 22350 VR at Pin 2 or Pin 3 = 0 V 1.0 8 6 0.8 0.6 VC 4 VR at Pin 2 or Pin 3 = 3.3 V Pin 3 to Pin 1, 2, 4 or 5 0.4 2 0.2 0 0 0 22348 1 2 3 4 VR at Pin 1 and Pin 4 (V) Fig. 3 - Typical Capacitance CD vs. Reverse Voltage VR Rev. 1.4, 31-May-12 0 5 21477 1 2 3 4 5 IPP (A) Fig. 6 - Typical Peak Clamping Voltage VC vs. Peak Pulse Current IPP Document Number: 81882 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS054CD-FHI www.vishay.com Vishay Semiconductors 100 Acc. IEC 61000-4-2 + 8 kV contact discharge 80 VC-ESD (V) 60 40 20 0 - 20 - 10 0 10 20 30 40 50 60 70 80 90 22352 t (ns) Fig. 7 - Typical Clamping Performance at + 8 kV Contact Discharge (acc. IEC 61000-4-2) 20 0 VC-ESD (V) - 20 - 40 Acc. IEC 61000-4-2 - 8 kV contact discharge - 60 - 80 - 100 - 120 - 10 0 10 20 30 40 50 60 70 80 90 t (ns) 22353 Fig. 8 - Typical Clamping Performance at - 8 kV Contact Discharge (acc. IEC 61000-4-2) 200 150 Positive discharge VC-ESD (V) 100 Acc. IEC 61000-4-2 contact discharge 50 0 VC-ESD - 50 - 100 Negative discharge - 150 - 200 0 22354 5 10 15 20 VESD (kV) Fig. 9 - Typical Peak Clamping Voltage at ESD Contact Discharge (acc. IEC 61000-4-2) Rev. 1.4, 31-May-12 Document Number: 81882 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS054CD-FHI www.vishay.com Vishay Semiconductors PACKAGE DIMENSIONS in millimeters (inches): LLP2513-11L 0.5 (0.020) bsc 0.28 (0.011) 0.19 (0.007) 0.4 (0.016) 0.25 (0.010) 0.22 (0.009) 2 (0.079) ref. 1.4 (0.055) 0.5 (0.020) 2.55 (0.100) 2.45 (0.096) 0.6 (0.024) 0.152 (0.006) ref. 0 (0.000) 0.05 (0.002) 1.3 (0.051) Pin 1 marking 0.4 (0.016) 0.15 (0.006) 0.5 (0.020) 0.25 (0.010) 0.22 (0.009) 4 x 0.5 = 2 (0.079) 0.37 (0.015) Foot print recommendation: Solder resist mask Document no.:S8-V-3906.04-009 (4) Created - Date: 15. April 2008 Rev. 2 - Date: 09. Sep. 2008 Solder pad 21382 Rev. 1.4, 31-May-12 Document Number: 81882 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS054CD-FHI www.vishay.com Vishay Semiconductors Pin 1 - Location LLP1713 Top view Pad layout - view from top seen at bottom side Pin 1 - Location LLP2513 Top view Pad layout - view from top seen at bottom side Pin 1 - Location LLP3313 Top view Rev. 1.4, 31-May-12 Pad layout - view from top seen at bottom side Document Number: 81882 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000