SEMTECH SC1157CS.TR

PROGRAMMABLE SYNCHRONOUS DC/DC
CONTROLLER FOR ADVANCED PROCESSORS
Preliminary - August 7, 2000
SC1157
TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com
DESCRIPTION
FEATURES
•= Low cost / full featured
•= Synchronous operation
•= 4 Bit VID DAC programmable output
The SC1157 is a low-cost, full featured, synchronous
voltage-mode controller designed for use in single
ended power supply applications where efficiency is of
primary concern. Synchronous operation allows for the
elimination of heat sinks in many applications. The
SC1157 is ideal for implementing DC/DC converters
needed to power advanced microprocessors such as
Pentium® ll (Klamath), in both single and multiple processor configurations. Internal level-shift, high-side
drive circuitry, and preset shoot-thru control, allows for
use of inexpensive n-channel power switches.
(1% tolerance)
•= Designed to meet Intel VRM8.2 (Pentium® II)
•= 1.5% Reference
APPLICATIONS
•= Pentium® II Core Supply
•= Multiple Microprocessor Supplies
•= Voltage Regulator Modules (VRM)
•= Programmable Power Supplies
•= High Efficiency DC/DC Conversion
SC1157 features include an integrated 4-bit VID DAC,
temperature compensated voltage reference, triangle
wave oscillator, current limit comparator, frequency
shift over-current protection, and an internally compensated error amplifier.
ORDERING INFORMATION
The SC1157 operates at a fixed 140KHz, providing an
optimum compromise between efficiency, external
component size, and cost.
(1)
(2)
DEVICE
PACKAGE
SC1157CS.TR
SO-16NB
TEMP. RANGE (TJ)
0 - 125°C
Note:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices.
(2) “NB” indicates 150 MIL body.
PIN CONFIGURATION
BLOCK DIAGRAM
Top View
VCC
CS-
CS+
SHUTDOWN
CURRENT
LIMIT
REF
REF
70mV
BSTH
+
LEVEL SHIFT AND
HIGH SIDE DRIVE
VID3
VID2
VID1
DH
+
D/A
ERROR
AMP
+
VID0
VOSENSE
R
Q
OSCILLATOR
GND
SHOOT-THRU
CONTROL
S
BSTL
(16-Pin SOIC)
SYNCHRONOUS
MOSFET DRIVE
DL
PGND
Pentium is a registered trademark of Intel Corporation
© 2000 SEMTECH CORP.
1
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC
CONTROLLER FOR ADVANCED PROCESSORS
SC1157
Preliminary - August 7, 2000
ABSOLUTE MAXIMUM RATINGS
Parameter
VCC to GND
PGND to GND
BST to GND
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering) 10 sec
ESD Rating (Human Body Model)
Symbol
VIN
Maximum
-0.3 to 7
±1
-0.3 to 15
Units
V
V
V
θJC
30
°C/W
θJA
130
°C/W
TA
0 to 70
°C
TSTG
-65 to +150
°C
TLEAD
300
°C
ESD
1.5
kV
ELECTRICAL CHARACTERISTICS
Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; FB = VO; 0mV < (CS(+) - CS(-)) < 60mV; TJ = 25oC
PARAMETER
CONDITIONS
MIN
Output Voltage
MAX
UNITS
See Table 1.
Supply Voltage
VCC
Supply Current
VCC = 5.0
Load Regulation
TYP
4.5
8
(1)
IO = 0.3A to 15A
Line Regulation
All VID codes
Gain (AOL)
VOSENSE to VO
(1)
7
V
15
mA
1
%
+0.15
%
35
dB
Current Limit Voltage
60
70
80
mV
Oscillator Frequency
125
140
155
kHz
Buffered Reference Voltage
IREF ≤=1mA
Oscillator Max Duty Cycle
90
1.25
V
95
%
DH Sink/Source Current
BSTH - DH = 4.5V, DH - PGNDH = 3V
1
A
DL Sink/Source Current
BSTL - DL = 4.5V, DL - PGNDL = 3V
1
A
Dead Time
VID Pin Source current
VIDx < 2.4V
50
100
ns
30
100
uA
NOTE:
(1) Specification refers to application circuit (Figure 1.).
(2) This device is ESD sensitive. Use of standard ESD handling precautions is required.
2
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC
CONTROLLER FOR ADVANCED PROCESSORS
SC1157
Preliminary - August 7, 2000
PIN DESCRIPTION
Pin #
Pin Name
Pin Function
1
GND
Small Signal Analog and Digital Ground
2
REF
Buffered Reference output
3
VCC
Chip Supply Voltage
4
CS(-)
Current Sense Input (negative)
5
CS(+)
Current Sense Input (positive)
6
PGND
Power Ground for High and Low Side Drivers
7
DH
High Side Driver Output
8
DL
Low Side Driver Output
9
BSTL
Vcc for Low Side Driver (Boost)
10
BSTH
Vcc for High Side Driver (Boost)
11
SHUTDOWN
Logic Low shuts down the converter; High or open for normal operation.
12
VOSENSE
Top end of internal feedback chain
13
(1)
Programming Input (MSB)
(1)
Programming Input
(1)
Programming Input
(1)
Programming Input (LSB)
14
15
16
VID3
VID2
VID1
VID0
NOTE:
(1) All logic level inputs and outputs are open collector TTL compatible.
PIN CONFIGURATION
3
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC
CONTROLLER FOR ADVANCED PROCESSORS
SC1157
Preliminary - August 7, 2000
OUTPUT VOLTAGE TABLE
Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; FB = VO; 0mV < (CS(+) - CS(-)) < 60mV;
TJ = 0°C to 85°C
PARAMETER
Output Voltage(1)
CONDITIONS
IO = 2A in Application Circuit
(Figure 1)
VID
3210
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
MIN
TYP
MAX
1.287
1.337
1.386
1.436
1.485
1.535
1.584
1.634
1.683
1.733
1.782
1.832
1.881
1.931
1.980
2.030
1.300
1.350
1.400
1.450
1.500
1.550
1.600
1.650
1.700
1.750
1.800
1.850
1.900
1.950
2.000
2.050
1.313
1.364
1.414
1.465
1.515
1.566
1.616
1.667
1.717
1.768
1.818
1.869
1.919
1.970
2.020
2.070
UNITS
V
NOTE:
(1) All VID codes not specifically listed are invalid and cause shutdown exactly as if the shutdown pin had been
asserted.
THEORY OF OPERATION
The voltage at the VOSENSE pin is applied, through the internal precision resistor feedback chain, to the inverting
input of the error amplifier. The non-inverting input of the error amplifier is supplied with a DC voltage derived by
the DAC from the internal trimmed bandgap voltage reference. The output of the error amplifier is compared to the
triangular output of the internal oscillator to generate a fixed frequency, variable duty cycle pulse train. The internal
oscillator uses an on-chip capacitor and precision trimmed current sources to set the frequency to 100 kHz.
The generated pulse train is gated with the output of the current limit latch and the inhibit signal to produce a drive
signal for the upper FET. It is also inverted to produce a drive signal for the lower FET. These FET drive signals
are modified by the “shoot-through control” circuitry so that the top FET turn-on is delayed until the bottom FET has
turned off, and visa-versa.
The current limit latch is set (ending the upper FET drive pulse early) if the current limit comparator indicates an
overcurrent condition. The latch is reset at the start of each oscillator period.
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© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC
CONTROLLER FOR ADVANCED PROCESSORS
SC1157
Preliminary - August 7, 2000
OUTLINE DRAWING SO-16
Jedec MS-012AC
LAND PATTERN SO-16
ECN00-1243
5
© 2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320