ST7554 V.90 USB WORLD MODEM CONTROLLER SUMMARY DATA .. .. .. . GENERAL USB HOT PLUG & PLAY INTERFACE DIRECT INTERFACE TO ST MAFE+DAA CHIP-SET ST75951/ST952 FOR WORLDWIDE DAA DESIGN OR TO STLC7550 FOR TRADITIONAL DAA DESIGN WINDOWS 98 AND NT 5.0 SUPPORT TAPI 2.0 COMPLIANT SOFTWARE UPGRADABLE MINIMUM SYSTEM REQUIREMENTS: USB MOTHERBOARD, 166MHz PENTIUM PROCESSOR WITH MMX TECHNOLOGY, WINDOWS 98 AND 16MBYTES RAM OR WINDOWS NT 5.0 AND 32MBYTES RAM .. . .. .. .. .. .. . . .. . . DEVICE FEATURES SINGLE 9.216MHz CRYSTAL OSCILLATOR INTEGRATED ANALOG AND DIGITAL 3.3V REGULATORS DEDICATED PINS FOR RING, OFF-HOOK, CLID, LOOP CURRENT SENSE 0.5µm CMOS PROCESS TQFP48 (7 x 7 mm) PACKAGE DATA MODEM / FAX / VOICE V.90 V.34BIS, V.34, V.32BIS, V.32, V.22BIS, V.22, V.23, V.21 BELL 103 AND BELL 212A V.17, V.27TER, V.29, FAX CLASS 1 SUPPORT V.42, V.42BIS, MNP 2, 3, 4, 5 V.80 V.8 AND AUTO MODE VOICE / FAX / MODEM DISTINCTION ADPCM VOICE COMPRESSION/DECOMPRESSION VOICE DETECTION (SILENCE DETECTION) OTHER FEATURES VIRTUAL UART (460.8Kbps) AT HAYES COMMAND COMPATIBLE TIME INDEPENDENT ESCAPE SEQUENCE (TIES) COMMAND CALLER ID TQFP48 (7 x 7 x 1.40mm) (Full Plastic Quad Flat Pack) ORDER CODE : ST7554TQF7 .. . DTMF DETECTION AND GENERATION WAKE UP ON RING WORLD-WIDE PROGRAMMABLE SILICON DAA SUPPORT FOR ST75951/ST952 MAFE+DAA CHIP-SET .. . . .. UNIVERSAL SERIAL BUS SPECIFICATION 1.0, 12MBps FULL SPEED ON-CHIP USB TRANSCEIVER WITH DIGITAL PLL COMMUNICATION DEVICE CLASS AND VENDOR REQUESTS BUS OR SELF POWERED APPLICATION (PIN-PROGRAMMABLE) ONNOW POWER MANAGEMENT (D0, D2, D3) LOW POWER CONSUMPTION (SUSPEND MODE D2), WHOLE APPLICATION BELOW 500µA DESCRIPTION The ST7554 is a single chip host signal processing Modem/fax/voice controller that supports data rates up to 56Kbps. All data pump and protocol functions are executed on the host PC’s processor. This product has been developed in cooperation with Smart Link Ltd, who ported "USB-Modio", its host based Modem and system software into ST system and hardware platform. The ST7554 directly connects to ST high performance Modem analog frontend (MAFE) STLC7550 or to the highly integrated MAFE+DAA chip-set ST75951/ST952. The ST7554 also features an Universal Serial Bus (USB) interface for direct connection to the host PC for maximum flexibility and real plug & play operation. January 1999 This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/11 RI RESERVED HSDT HO RESERVED CLID CD LED RFC DISHS PULSE BUZEN 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 2/11 D- 1 36 DC D+ 2 35 TRxD GNDBUS 3 34 DAASEL VREGD 4 33 RESERVED VBUS 5 32 DGND VREGA 6 31 DOUT AGND 7 30 DIN PSM 8 29 MCLK XTALIN 9 28 FS XTALOUT 10 27 HC1 FLTPLL 11 26 PDOWN RESET 12 25 RESERVED 7554S-01.EPS ST7554 PIN CONNECTIONS ST7554 PIN LIST Name Pin Type Description XTALIN 9 I XTALOUT 10 O Crystal Output RESET 12 I Reset Function to initialise the device (active low) VBUS 5 I Positive Voltage Regulator Input, connected to USB VBUS GNDBUS 3 I Regulator Ground, connected to USB Ground (0V) (see Note 1) VREGA 6 I/O VREGD 4 I/O Positive Regulated Digital Input/Output Power Supply PSM 8 I Power Supply Mode (Bus-powered or Self-powered) D+ 2 I/O Positive Data Signal of Differential Data Bus conforming to USB Standard Specification 1.0 D- 1 I/O Negative Data Signal of Differential Data Bus conforming to USB Standard Specification 1.0 TRxD 35 I/O Transmit/Receive Data Led DC 36 I/O DC mask BUZEN 37 I/O Buzzer Amplifier Enable/Mute PULSE 38 I/O Pulse dialing DISHS 39 I/O Disconnect external phone RFC 40 I/O Refresh LED 41 I/O LED control CD 42 I/O Carrier Detect Led Crystal Input Positive Regulated Analog Input/Output Power Supply CLID 43 I/O Caller ID HO 45 I/O Hook Control HSDT 46 I/O Current sense RI 48 I/O Ring Indicator HC1 27 O Modem Codec Hardware Control mode selection PDOWN 26 O SSI Powerdown bit output (active low) MCLK 29 O SSI Master Clock Output DAASEL 34 I Select Silicon or Discrete DAA Configuration Mode FS 28 I SSI Frame Synchronisation Input DOUT 31 O SSI Serial Data Output DIN 30 I SSI Serial Data Input FLTPLL 11 OA DGND 32 I Digital Ground (0V) (see Note 1) AGND 7 I Analog Ground (0V) (see Note 1) RESERVED 13 to 25-33-44 - Not connected RESERVED 47 - Connect to digital ground DGND 7554S-01.TBL PLL filter analog output. Must be connected to analog ground AGND with 33pF capacitor Note 1 : Analog and digital ground pins must be tied together to USB ground GNDBUS. 3/11 ST7554 PIN DESCRIPTION 1.2 - Regulated Analog VDD Supply (VREGA) This pin is the analog power supply input (PSM = 0) or analog 3.3V power supply output (PSM = 1). This pin is the positive analog power supply for the external Codec and DAA. It is recommended to add a 1µF capacitor between VREGA and GNDA as close as possible to the IC pins. 1.3 - Regulated VDD Supply (VREGD) This pin is the digital power supply input (PSM = 0) or digital 3.3V power supply output (PSM = 1). This pin is the positive digital power supply for the external Codec and DAA. It is recommended to add a 1µF capacitor between VREGA and GNDA as close as possible to the IC pins. Figure 1 : ST7554 in Bus-Powered mode (PSM = 1) ST7554 8 PSM 5 VBUS from USB 3 GNDBUS 4 VREGD to other digital ICs 32 DGND 6 VREGA to other analog ICs 7 AGND Figure 2 : 7554S-02.EPS 1 - Power Supply (7 pins) 1.1 - Regulator Input Power Supply (VBUS) This pin must be connected to USB VBUS (+5V). It supplies the integrated analog USB transceiver. It is also the positive regulator power supply input (5V) when ST7554 is in bus-powered mode (PSM = 1) and it is used to internally generate the 3.3V supply for the digital and analog circuitry. ST7554 in Self Powered mode (PSM = 0) ST7554 8 PSM 1.5 - Ground (DGND, AGND and GNDBUS) DGND, AGND and GNDBUS are the digital, analog and USB ground return pins respectively. They should be connected together outside the chip to the GND pin of the USB plug. 4/11 5 VBUS from USB 3 GNDBUS 4 VREGD from 3.3V externally regulated supplies 32 DGND 6 VREGA 7 AGND 2 - USB Interface (D+ , D-) These pins are the positive and negative USB differential data lines. They shall be both connected to the USB plug or USB protection circuit via 27Ω series resistors for line impedance matching. 7554S-03.EPS 1.4 - Power Supply Mode (PSM) This pin controls the VREGD and VREGA power supply mode. When PSM = 1, the application is bus-powered. The 3.3V power supply is generated internally from VBUS. In this case VREGD and VREGA are outputs which can be used to supply 3.3V to external devices (see Figure 1). When PSM = 0, the application is self-powered. VBUS must be still connected to the VBUS Pin of the USB connector in order to supply the integrated USB transceiver. Anyway in this case VREGD and VREGA must be fed by a 3.3V externally regulated digital and analog power supplies (see Figure 2). ST7554 PIN DESCRIPTION (continued) based on ST75951 + ST952. Connect to DGND when using STLC7550 with discrete interface. 3 - Reset, Powerdown (RESET, PDOWN) RESET Pin initialises the internal counters and control registers to their default value. A minimum low pulse of 1ms is required to reset the chip. In a typical application RESET is connected to VBUS through a R, C network. This ensures that the chip is reset at each connection / disconnection to the USB bus (see Figure 3). PDOWN Pin shall be connected to the powerdown inputs of the external codec used on the SSI. When ST7554 is in Suspend mode, PDOWN is forced low so that the external codec is in powerdown. 5 - DAA Control Pins (IMP, DC, BUZEN, PULSE, DISHS, RFC, LED, CLID, HO, HSDT, RI) These pins control the World Wide software programmable DAA through ST75951/ST952. VBUS R 220kW 4 - Serial Synchronous Interface ST7554 has a Serial Syncronous Interface (SSI) dedicated to the connection of the STLC7550 or ST75951, ST high performance Modem Analog Front-End (MAFE). 4.1 - Data (DIN, DOUT) Digital data word input/output of SSI, to be connected to the data word pins of STLC7550 or ST75951. 4.2 - Master Clock (MCLK) This pin is the master clock output. 4.3 - Frame Synchronization (FS) The frame synchronization is used to synchronize data transfer between ST7554 and the external Codec. 4.4 - Hardware Control (HC1) HC1 must be connected to the corresponding pin of STLC7550 or ST75951, while their HC0 Pin shall be tied to the 3.3V VREGD digital supply. This pin selects data or control modes for the Modem Codec. 4.5 - DAA Selection (DAASEL) Connect to VREGD when using silicon DAA chipset 7554S-04.EPS 12 RESET C 10nF Figure 4 : Application schematic for the 9.216MHz external crystal XTAL IN XTAL OUT 9 10 R 1.8kW C 18pF AGND C 18pF 7554S-05.EPS Figure 3 : RC network for RESET 6 - Crystal (XTALIN, XTALOUT) These pins must be tied to the 9.216MHz external crystal. It is recommended to use a ±50ppm fundamental parallel resonator crystal. It is recommended to insert a 1.8kΩ resistor between XTALOUT and the crystal to limit its energy to 100µW for a 20Ω resonator (see Figure 4). For a SMD crystal the load capacitor is typically CLOAD = 12pF and this leads to an ideal value of C = 24pF for the capacitors between the crystal and analog ground (AGND). Anyway, in practice these capacitors shall be reduced down to C = 18pF each by considering parasitic capacitors on PCB and package (see Figure 4). After a reset or when leaving the suspend state, the 9.216MHz is asserted inside ST7554 only 3.5ms later in order to wait for it to be stable. AGND 7 - PLL Output Filter (FLTPLL) This pin must be connected to the analog ground (AGND) through a 33pF capacitor. 8 - Reserved Pins (18 pins) These pins must be left not connected except Pin 47 which should be connected to the digital ground DGND. 5/11 ST7554 ELECTRICAL SPECIFICATIONS Unless otherwise stated, electrical characteristics are specified over the operating range. Typical values are given for VBUS = +5V, VREGA = 3.3V, VREGD = 3.3V, Tamb = 25°C. Absolute Maximum Rating (AGND = DGND = USB GND = 0V, all voltages with respect to 0V) Symbol Parameter Value Unit DVDD Digital Power Supply -0.3, 6.0 V II Input Current per Pin -10, +10 mA IO Output Current per Pin -20, +20 mA VIA Analog Input Voltage -0.3, AVDD + 0.3 V VID Digital Input Voltage -0.3, DVDD + 0.3 V 0, +70 °C Toper Operating Temperature Tstg Storage Temperature Ptot Maximum Power Dissipation -55, +150 °C 200 mW Warning : Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranted at these extremes. Nominal DC Characteristics (Tamb = 0 to 70°C unless otherwise specified) Symbol Parameter Min. Typ. Max. Unit 4 5 TBD TBD 3.4 3.3 3.4 3.3 5.25 V mA µA V V V V mA mA mA mA mW mW mW POWER SUPPLY AND COMMON MODE VOLTAGE VBUS IVBUS IVBUSS VREGA VREGD IVREGA IVREGD PDLP PD PD Supply Voltage Supply Current Supply Current in Suspend Mode (PSM = 1) Analog regulated Output Power Supply (PSM =1) Analog regulated Input Power Supply (PSM =0) Digital regulated Output Power Supply (PSM =1) Digital regulated Input Power Supply (PSM =0) Analog regulated Output Current (PSM =1) Analog regulated Input Current (PSM =0) Digital regulated Output Current (PSM =1) Digital regulated Input Current (PSM =0) Low Power Mode (Suspend mode D2, wake-up on ring enabled) Operating Power (SSI in power-down) Operating Power (D0 power state) 3.4-10% 3.3-10% 3.4-10% 3.3-10% 3.4+10% 3.3+10% 3.4+10% 3.3+10% 40 TBD 20 20 TBD TBD TBD DIGITAL INTERFACE (except XTALIN, XTALOUT, PSM and RESET) (these inputs have hysteresis) VIH VIL VOH VOL ILEAK IOL IOH VHYST CIN High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current High Level Output Current (0 < VOL < VOLMax.) Low Level Output Current (VOHMin. < VOH < VREGD) Schmitt Trigger Hysteresis Input Capacitance 0.8 x VREGD 0.4 ±1 2 V V V V µA mA mA V pF 0.3 x VBUS ±1 V V µA V 0.2 x VREGD 0.85 x VREGD -2 0.8 3 PSM, RESET (these inputs have hysteresis) VIH VIL ILEAK VHYST High Level Input Voltage Low Level Input Voltage Input Leakage Current Schmitt Trigger Hysteresis 0.7 x VBUS 1 1.3 CRYSTAL OSCILLATOR (XTALIN, XTALOUT) VIH VIL IIH IIL 6/11 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current 0.8 x VREGA 0.2 x VREGA 20 -20 V V µA µA ST7554 UNIVERSAL SERIAL BUS INTERFACE (see Chapter 7 of USB rev 1.0 for complete Electrical Specification) Nominal DC Characteristics (D+, D-) Symbol Parameter Min. VDI Differential Input Sensitivity [(D+) - (D-)] 0.2 VCM Differential Common Mode Range 0.8 Typ. Max. Unit V 2.5 V VSE Single Ended Receiver Threshold 0.8 2 V VOH VOL High Level Output Static Voltage (RL of 15kΩ to GND) Low Level Output Static Voltage (RL of 1.5kΩ to 3.6V) 2.8 3.6 0.3 V V ILO Hi-Z State Data Line Leakage Current (0V < VIN < 3.3V) ±10 µA CIN Transceiver Capacitance (Pin to GND) 20 pF TBD Ω RD (2) Note 2 : Driver Output Resistance (steady state drive) TBD Excludes external resistor. In order to comply with USB Specifications 1.0, external series resistors of 27Ω ±1% each on D+ and Dare recommended AC Characteristics (D+, D-) (see Figure 5 for test scheme) Symbol Parameter Max. Unit 11.97 12.03 Mbps Rise Time between 10% and 90% (see Figure 6) 4 20 ns Fall Time 10% and 90% (see Figure 6) 4 20 ns 1.3 2 V tDR Average bit rate (12 M/s ± 0.05%) tR tF VCRS Min. Output Signal Crossover Voltage Figure 5 : Test Scheme for D+/D- Typ. Figure 6 : Rise and Fall Time Measures VREGD 1.5kW tR Test 27W D+ tF 90% 2 90% Test 27W 1 15kW 50pF 15kW 10% 10% 7554S-07.EPS 50pF 7554S-06.EPS D- 7/11 ST7554 TYPICAL APPLICATIONS Figure 7 : ST7554 Typical Application Diagram with ST75951/ST952 USB ST75951 ST952 POTS DAA POTS 7554S-08.EPS ST7554 Figure 8 : ST7554 Typical Application Diagram with STLC7550 USB STLC7550 7554S-09.EPS ST7554 8/11 L2 C6 C7 R8 C8 6 TOFF 32 LCOM 25 LCOM 18 SET AGND AGND1 14 IREF VREFN C20 C18 22 C21 C19 C17 C16 32 39 VCM 15 VDREF 38 VCMS R7 AGND2 23 G1 C23 C22 29 VCMP AIN 26 C10 26 D6 27 D5 G2 21 40 AVDD 19 VDR AOUT 27 U3 IC2 ST75951 VREFP 21 IDG 22 IDI 20 LINE RIN 5 4 30 D4 6 C25 C24 5 DVDD TSTD1 45 AUXIN 41 TSTA2 33 TSTA1 28 RING 15 GPIO3 17 GPIO2 18 GPIO1 19 GPIO0 20 DGND R11 R10 3 D6 D5 2 31 D3 DIN 46 DOUT 47 DVDD R12 D2 C9 IDC 16 TER2 9 17 TER1 10 COM D4 1 XTALOUT 11 OHC U2 34 D2 XTALIN 24 GAIN M/S 35 D1 SCLK D3 D2 31 FS Q2 R5 D1 30 LIM1 RESET 8 23 LINI PWRDWN R6 Q4 Q3 R4 Q1 44 4 16 9 26 FS 11 PDOWN 3 27 HC1 2 HC1 8 34 GPI 7 DAASEL D1 Q5 R9 B1 10 HC0 43 17 MCM C4 R3 R2 42 HM 14 18 TS RESERVED R1 T1 U1 47 RESERVED 7554S-10.EPS Line Plug C5 MCLK C3 RESERVED 28 31 30 2 3 D+ GNDBUS 43 AGND 45 48 7 DGND 32 1 D- R18 5 R17 VBUS 8 4 DIN 29 IC1 DVDD DOUT DVDD R14 XTALIN 12 ST7554 C15 CLID R15 C13 9 10 XTALOUT FLTPLL K1 6 10 C14 VREGA R16 C30 RESET C12 C11 41 LED D4 VREGD RI L1 IC3 ST952 LED R19 C31 AVDD PSM HO R0 Note : This is an example schematic. Details may change without notice. Refer to ST USB Dongle Modem documentation. C28 C29 L3 C26 GND R20 R19 C27 4 3 2 1 L4 U5 USB6 5 6 7 8 4 3 2 1 U4 USB Plug ST7554 TYPICAL APPLICATIONS (continued) Figure 9 : ST7554 Schematic Diagram with ST75951/ST952 9/11 10/11 R27 C37 U3 AGND 10 9 C4 R4 8 R26 AGND1 AGND C11 C16 20 VREFN R31 AGND2 33 27 C10 C14 C15 C17 32 VCM 21 AUXIN+ R33 R29 C8 C9 28 AUXIN- R30 Q2 2 19 31 AVDD C38 VREFP R25 R24 30 IN- 40 OUT- 6 3 GNDBUS 45 44 C18 C19 5 DVDD RESET 41 HC0 16 M/S 18 30 31 AGND DVDD Q1 R22 R28 39 OUT+ DGND C36 D3 U3 XTALOUT 1 9 XTALIN IC2 STLC7550 3 SCLK 29 IN+ 4 FS C35 R23 17 PWRDWN 3 R16 15 HC1 C32 R17 43 TSTD1 5 7 MCM VCM U3 42 TS 8 R8 2 D+ DIN 7 R21 14 1 7 DGND 32 5 D- R3 R2 VBUS DOUT C31 T1 R13 13 U3 8 DIN DOUT 7554S-11.EPS R20 B1 C28 6 C30 47 28 18 17 34 27 26 FS C39 R15 R1 MCLK 29 HC1 PDOWN 12 C1 4 DAASEL L6 R18 R19 AGND 45 HO IC1 ST7554 C3 RESERVED Line Plug 2 R11 XTALIN 48 RI 9 10 XTALOUT 41 LED 12 C2 RESERVED L5 7 1 4 K1 R9 C7 L1 RESERVED R12 T2 8 5 3 C21 C22 FLTPLL R32 D1 6 VREGA 10 C24 DVDD VREGD C27 6 DVDD C23 L4 RESET D5 D4 R10 C25 AVDD PSM R14 D2 Note : This is an example schematic. Details may change without notice. Refer to ST USB Dongle Modem documentation. C20 R5 DVDD G1 C13 C12 C6 L2 G2 R7 R6 GND C5 4 3 2 1 L3 U1 USB6 5 6 7 8 4 3 2 1 U4 USB Plug ST7554 TYPICAL APPLICATIONS (continued) Figure 10 : ST7554 Schematic Diagram with STLC7550 (in TQFP48 package) ST7554 PACKAGE MECHANICAL DATA 48 PINS - THIN PLASTIC QUAD FLAT PACK (TQFP) A A2 e 48 A1 37 36 12 25 E3 E1 E B 1 0,10 mm .004 inch SEATING PLANE c 24 Dimensions A A1 A2 B C D D1 D3 e E E1 E3 L L1 K Min. 0.05 1.35 0.17 0.09 0.45 Millimeters Typ. 1.40 0.22 9.00 7.00 5.50 0.50 9.00 7.00 5.50 0.60 1.00 Max. 1.60 0.15 1.45 0.27 0.20 0.75 Min. 0.002 0.053 0.007 0.004 0.018 PM-5B.EPS K 0,25 mm .010 inch GAGE PLANE Inches Typ. 0.055 0.009 0.354 0.276 0.216 0.0197 0.354 0.276 0.216 0.024 0.039 Max. 0.063 0.006 0.057 0.011 0.008 0.030 5B.TBL L D3 D1 D L1 13 0o (Min.), 7o (Max.) Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 1999 STMicroelectronics - All Rights Reserved Purchase of I2C Components of STMicroelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. 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