PROCESS CP341V Small Signal Transistors NPN - Low VCE(SAT) Transistor Chip PROCESS DETAILS Process EPITAXIAL PLANAR Die Size 18 x 18 MILS Die Thickness 7.1 MILS Base Bonding Pad Area 3.8 x 3.8 MILS Emitter Bonding Pad Area 3.8 x 3.8 MILS Top Side Metalization Al/Si - 30,000Å Back Side Metalization Au - 12,000Å GEOMETRY GROSS DIE PER 5 INCH WAFER 54,330 PRINCIPAL DEVICE TYPES CMLT3410 CMPT3410 CMST3410 CMUT3410 CXT3410 R2 (22-March 2010) w w w. c e n t r a l s e m i . c o m PROCESS CP341V Typical Electrical Characteristics R2 (22-March 2010) w w w. c e n t r a l s e m i . c o m