Rev. 1.0, Jul. 2010
KA100O015E-BJTT
MCP Specification
4Gb (256M x16) NAND Flash
+ 4Gb (64M x32 + 64M x32) 2/CS,2CKE DDP Mobile DDR SDRAM
datasheet
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SPECIFICATIONS WITHOUT NOTICE.
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-1-
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
Revision History
Revision No.
History
Draft Date
Remark
Editor
0.0
Initial issue.
- 4Gb NAND Flash V-die_ Ver 0.0
- 4Gb DDP Mobile DDR C-die_Ver 0.0
Jun. 10, 2010
Preliminay
H.J.Min
1.0
<Common>
- Finalized
<NAND Flash>_Ver 1.1
Revision 1.0v
1. Chapter 2.2 Recommended Operating Conditions revised.
Jul. 28, 2010
Final
J.S.Ahn
Revision 1.1v
1. Chapter 2.8 Read / Program / Erase Characteristics Parameter
reviesed.
<Mobile DDR SDRAM>_Ver 1.0
- Corrected errata.
- Revised DC characteristics.
-2-
KA100O015E-BJTT
Rev. 1.0
datasheet
MCP Memory
1. FEATURES
<Common>
• Operating Temperature : -25°C ~ 85°C
• Package : 137-ball FBGA Type - 10.5 x 13 x 1.2mmt, 0.8mm pitch
<NAND Flash>
• Voltage Supply
- 1.8V Device : 1.7V ~ 1.95V
• Organization
- Memory Cell Array :
(256M + 8M) x 16bit for 4Gb
(512M + 16M) x 16bit for 8Gb DDP
- Data Register : (2K + 64) x 16bit
• Automatic Program and Erase
- Page Program : (2K + 64)Word
- Block Erase : (128K + 4K)Word
• Page Read Operation
- Page Size : (2K + 64)Word
- Random Read : 60μs(Max.) (TBD)
- Serial Access : 42ns(Min.)
• Fast Write Cycle Time
- Page Program time : 420μs(Typ.) (TBD)
- Block Erase Time : 3ms(Typ.) (TBD)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology
-Endurance : TBD Program/Erase Cycles
with 4bit/256Word ECC for x16
• Command Driven Operation
• Unique ID for Copyright Protection
<Mobile DDR>
• VDD/VDDQ = 1.8V/1.8V
• Double-data-rate architecture; two data transfers per clock cycle.
• Bidirectional data strobe (DQS).
• Four banks operation.
• Differential clock inputs (CK and CK).
• MRS cycle with address key programs.
- CAS Latency (3)
- Burst Length (2, 4, 8, 16)
- Burst Type (Sequential & Interleave)
• EMRS cycle with address key programs.
- Partial Array Self Refresh (Full, 1/2, 1/4 Array)
- Output Driver Strength Control (Full, 1/2, 1/4, 1/8, 3/4, 3/8, 5/8, 7/8)
• Internal Temperature Compensated Self Refresh.
• All inputs except data & DM are sampled at the positive going edge of the
system clock (CK).
• Data I/O transactions on both edges of data strobe, DM for masking.
• Edge aligned data output, center aligned data input.
• No DLL; CK to DQS is not synchronized.
• DM for write masking only.
• Auto refresh duty cycle.
- 7.8us
• Clock stop capability
• 2/CS, 2CKE
Operating Frequency
DDR400
Speed @CL3
200MHz
1)
NOTE :
1) CAS Latency
Address configuration
Organization
/CS
CKE
Bank
Row
Column
64Mx32
CS0
CKE0
BA0,BA1
A0 - A13
A0 - A9
64Mx32
CS1
CKE1
BA0,BA1
A0 - A13
A0 - A9
- DM is internally loaded to match DQ and DQS identically.
-3-
KA100O015E-BJTT
datasheet
Rev. 1.0
MCP Memory
2. GENERAL DESCRIPTION
The KA100O015E is a Multi Chip Package Memory which combines 4G bit NAND Flash Memory and 4G bit DDP synchronous high data rate Dynamic
RAM.
NAND cell provides the most cost-effective solution for the solid state application market. A program operation can be performed in typical 420μs(TBD) on
the (2K+64)Word page and an erase operation can be performed in typical 3ms(TBD) on a (128K+4K)Word block. Data in the data register can be read
out at 42ns cycle time per Word. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller
automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the writeintensive systems can take advantage of the device′s extended reliability of TBD program/erase cycles by providing ECC(Error Correcting Code) with real
time mapping-out algorithm. The device is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable
applications requiring non-volatility.
In 4G bit DDP Mobile DDR, Synchronous design make a device controlled precisely with the use of system clock. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
The KA100O015E is suitable for use in data memory of mobile communication system to reduce not only mount area but also power consumption. This
device is available in 137-ball FBGA Type.
-4-
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
3. PIN CONFIGURATION
-
1
2
3
4
5
6
7
8
9
10
A
-
DNU
-
-
-
-
-
-
DNU
DNU
B
NC
CKE2d
/REn
CLEn
VCCn
/CEn
/WEn
VDDd
VSSd
NC
C
VSSd
A4d
/WPn
ALEn
VSSn
R/Bn
DQ31d
DQ30d
VDDQd
VSSQd
D
VDDd
A5d
A7d
A9d
DQ25d
DQ27d
DQ29d
DQ28d
VSSQd
VDDQd
E
A6d
A8d
CKE1d
DQ18d
DQS3d
DQ22d
DM3d
DQ26d
VDDQd
VSSQd
F
A12d
A11d
/CS2d
DQ17d
DQ19d
DQ24d
DQ23d
DM2d
VSSQd
VDDQd
G
NC
/RASd
DQ15d
DQ16d
DQS1d
DM1d
DQ9d
CKd
VDDQd
VSSQd
H
VDDd
/CASd
DQ20d
DQ21d
DQ13d
DQ12d
DQS2d
/CKd
VSSd
VDDd
J
VSSd
/CS1d
BA0d
DQ14d
DQ11d
DQ10d
DQS0d
DM0d
VSSQd
VDDQd
K
/WEd
BA1d
A10d
A0d
DQ7d
DQ8d
DQ6d
DQ4d
VDDQd
VSSQd
L
A1d
A2d
A3d
DQ0d
DQ1d
DQ2d
DQ3d
DQ5d
VDDQd
VSSQd
M
VDDd
VSSd
A13d
NC
IO3n
IO5n
IO14n
IO7n
VSSQd
VDDQd
N
IO0n
IO1n
IO2n
IO10n
VCCn
IO6n
IO13n
IO15n
VDDQd
VSSQd
P
NC
IO8n
IO9n
IO11n
IO12n
VSSn
IO4n
VDDd
VSSd
NC
R
DNU
DNU
-
-
-
-
-
-
DNU
DNU
137 FBGA: Top View (Ball Down)
NAND
Mobile DRAM
Power
Ground
NC/DNU
-5-
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
4. PIN DESCRIPTION
Pin Name
CKd,/CKd
CKE1d,CKE2d
/CS1d,/CS2d
/RASd
Pin Function(Mobile DRAM)
Pin Name
Pin Function(NAND Flash)
Differential System Clock
/CEn
Chip Enable
Clock Enable
/REn
Read Enable
Chip Select
/WPn
Write Protection
Row Address Strobe
/WEn
Write Enable
/CASd
Column Address Strobe
ALEn
Address Latch Enable
/WEd
Write Enable
CLEn
Command Latch Enable
A0d ~ A13d
BA0d ~ BA1d
DM0d ~ DM3d
DQS0d ~ DQS3d
DQ0d ~ DQ31d
VDDd
VDDQd
VSSd
VSSQd
Address Input
R/Bn
Bank Address Input
IO0n ~ IO15n
Ready/Busy Output
Data Input/Output
Input Data Mask
VCCn
Power Supply
Data Strobe
VSSn
Ground
Data Input/Output
Power Supply
Pin Name
Data Out Power
Ground
DNU
DQ Ground
NC
-6-
Pin Function
Do Not Use
No Connection
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
5. ORDERING INFORMATION
KA
1
00
O
0
15
E - B J T
T
Samsung
MCP Memory(3chips)
Mobile DDR Speed
T : 5ns (200Mhz@CL3)
Device Type
1 : NAND + SDRAM + SDRAM
Mobile DDR Speed
T : 5ns (200Mhz@CL3)
NOR Flash Density,Voltage,
Organization
00 : None
NAND Flash Speed
J : 42ns
Package(Pad finish+pb-free)
B : FBGA(HF,OSP LF)
NAND Density, Voltage,
Organization
O : 4G NAND, 1.8V/1.8, x16
Version
E : 6th Generation
UtRAM Density, Voltage, Organization
0 : None
DRAM Interface, Density, Voltage, Organization
15: MDDR*2, 2Gb*2, 1.8V/1.8V, x32(2/CS,2CK)
-7-
datasheet
KA100O015E-BJTT
Rev. 1.0
MCP Memory
6. FUNCTIONAL BLOCK DIAGRAM
VCCn
VSSn
/CEn
/REn
/WPn
/WEn
4Gb NAND
Flash Memory
IO0n to IO15n
ALEn
CLEn
R/Bn
VDDd VDDQd VSSd VSSQd
CKd,/CKd
CKE0d,CKE1d
/CS0d,/CS1d
/RASd
/CASd
/WEd
4Gb 2CS,2CKE DDP
Mobile DDR SDRAM
A0d~A12d
BA0d~BA1d
DM0d~DM3d
DQS0d~DQS3d
-8-
DQ0d to DQ31d
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
7. PACKAGE DIMENSION
137-Ball Fine pitch Ball Grid Array Package (measured in millimeters)
Units:millimeters
#A1 INDEX MARK
10.50±0.10
10.50±0.10
0.10 MAX
A
0.80 x 9 = 7.20
10 9 8 7 6 5 4 3 2 1
B
(Datum A)
0.32±0.05
3.60
0.80
1.10±0.10
TOP VIEW
137-∅0.45±0.05
∅ 0.20 M A B
-9-
BOTTOM VIEW
13.00±0.10
0.80 x 14 = 11.20
5.60
13.00±0.10
0.80
A
B
C
D
(Datum B) E
F
G
H
J
K
L
M
N
P
R
#A1
KA100O015E-BJTT
datasheet
Rev. 1.0
MCP Memory
4Gb (256M x16) NAND Flash V-die
- 10 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
VCC
VSS
A13 - A30*
X-Buffers
Latches
& Decoders
4,096M + 128M Bit for 4Gb
8,192M + 256M Bit for 8Gb DDP
NAND Flash
ARRAY
A0 - A12
Y-Buffers
Latches
& Decoders
Data Register & S/A
Y-Gating
Command
Command
Register
Control Logic
& High Voltage
Generator
CE
RE
WE
VCC
VSS
I/O Buffers & Latches
Output
Driver
Global Buffers
I/0 0
I/0 7
CLE ALE WP
[Figure 1] Functional Block Diagram
1 Block = 64 Pages
(256K + 8K) Byte
1 Page = (4K + 128)Bytes
1 Block = (4K + 128)Byte x 64 Pages
= (256K + 8K) Bytes
1 Device = (4K+128)B x 64Pages x 2,048 Blocks
= 4,224 Mbits for 4Gb
8 bit 1 Device = (4K+128)B x 64Pages x 4,096 Blocks
= 8,448 Mbits for 8Gb DDP
2,048 blocks for 4Gb
4,096 blocks for 8Gb DDP
4K Bytes
128 Bytes
I/O 0 ~ I/O 7
Page Register
4K Bytes
128 Bytes
[Figure 2] Array Organization
[Table 1] Array address (x8)
1st Cycle
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
Address
A0
A1
A2
A3
A4
A5
A6
A7
Column Address
2nd Cycle
A8
A9
A10
A11
A12
*L
*L
*L
Column Address
3rd Cycle
A13
A14
A15
A16
A17
A18
A19
A20
Row Address
4th Cycle
A21
A22
A23
A24
A25
A26
A27
A28
Row Address
5th Cycle
A29
*A30
*L
*L
*L
*L
*L
*L
Row Address
NOTE :
Column Address : Starting Address of the Register.
* L must be set to "Low".
* The device ignores any additional input of address cycles than required.
* A30 is Row address for 8G DDP.
In case of 4G Mono, A30 must be set to "Low"
- 11 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
VCC
VSS
A12 - A29*
X-Buffers
Latches
& Decoders
4,096M + 128M Bit for 4Gb
8,192M + 256M Bit for 8Gb DDP
NAND Flash
ARRAY
A0 - A11
Y-Buffers
Latches
& Decoders
Data Register & S/A
Y-Gating
Command
Command
Register
Control Logic
& High Voltage
Generator
CE
RE
WE
VCC
VSS
I/O Buffers & Latches
Global Buffers
Output
Driver
I/0 0
I/0 15
CLE ALE WP
[Figure 3] Functional Block Diagram
1 Block = 64 Pages
(128K + 4K)Word
1 Page = (2K + 64)Word
1 Block = (2K + 64)Word x 64 Pages
= (128K + 4K)Words
1 Device = (2K + 64)Word x 64Pages x 2,048 Blocks
= 4,224 Mbits for 4Gb
16 bit 1 Device = (2K + 64)Word x 64Pages x 4,096 Blocks
= 8,448 Mbits for 8Gb DDP
2,048 blocks for 4Gb
4,096 blocks for 8Gb DDP
2K Words
64 Words
I/O 0 ~ I/O 15
Page Register
2K Words
64 Words
[Figure 4] Array Organization
[Table 2] Array address (x16)
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8~I/O 15
Address
1st Cycle
A0
A1
A2
A3
A4
A5
A6
A7
*L
Column Address
2nd Cycle
A8
A9
A10
A11
*L
*L
*L
*L
*L
Column Address
3rd Cycle
A12
A13
A14
A15
A16
A17
A18
A19
*L
Row Address
4th Cycle
A20s
A21
A22
A23
A24
A25
A26
A27
*L
Row Address
5th Cycle
A28
*A29
*L
*L
*L
*L
*L
*L
*L
Row Address
NOTE :
Column Address : Starting Address of the Register.
* L must be set to "Low".
* The device ignores any additional input of address cycles than required.
* A29 is Row address for 8G DDP.
In case of 4G Mono, A29 must be set to "Low"
- 12 -
Column Address
Row Address
datasheet
KA100O015E-BJTT
Rev. 1.0
MCP Memory
1.0 PRODUCT INTRODUCTION
NAND Flash Memory has addresses multiplexed into 8 I/Os(x16 device case : lower 8 I/Os). This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing
WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup
and the other cycle for execution. Page Read and Page Program need the same five address cycles following the required command input. In Block
Erase operation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command
register. Table 3 defines the specific commands of the device.
In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another page without need
for transporting the data to and from the external buffer memory. Since the time-consuming serial access and data-input cycles are removed, system performance for solid-state disk application is significantly increased.
[Table 3] Command Sets
Function
1st Cycle
2nd Cycle
Read
00h
30h
Read ID
90h
-
Read for Copy Back
00h
35h
Reset
FFh
-
Page Program
80h
10h
Copy-Back Program
85h
10h
Block Erase
60h
D0h
Random Data Input 1)
85h
-
05h
E0h
70h
-
Random Data Output
1)
Read Status
NOTE :
1) Random Data Input/Output can be executed in a page.
Caution :
Any undefined command inputs are prohibited except for above command set of Table 3.
- 13 -
Acceptable Command during Busy
O
O
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
1.1 ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
VCC
-0.6 to + 2.45
VIN
-0.6 to + 2.45
Voltage on any pin relative to VSS
Unit
V
VI/O
-0.6 to Vcc + 0.3 (< 2.45V)
Storage Temperature
TSTG
-65 to +100
°C
Short Circuit Current
Ios
IOS
5
mA
NOTE :
1) Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
1.2 RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, TA=-30 to 85°C1))
Parameter
Symbol
Min
Typ.
Max
Unit
Supply Voltage
VCC
1.7
1.8
1.95
V
Supply Voltage
VSS
0
0
0
V
NOTE :
1) Data retention is not guaranteed out of Operating condition temerature range(-30 to 85°C).
1.3 DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions otherwise noted.)
Parameter
Operating
Current
Symbol
Test Conditions
Min
Page Read with Serial
Access
ICC1
tRC=42ns
CE=VIL, IOUT=0mA
-
Program
ICC2
-
-
Erase
ICC3
-
-
Stand-by Current(TTL)
ISB1
Stand-by Current(CMOS)
ISB2
Typ
Max
15
25
mA
4Gb,CE=VIH, WP=0V/VCC
-
-
1
8Gb DDP,CE=VIH, WP=0V/VCC
-
-
2
4Gb,CE=VCC-0.2, WP=0V/VCC
-
10
50
8Gb DDP,CE=VCC-0.2, WP=0V/VCC
-
20
100
Input Leakage Current
ILI
VIN=0 to Vcc(max)
-
-
±10
Output Leakage Current
ILO
VOUT=0 to Vcc(max)
-
-
±10
Input High Voltage
(1)
VIH
-
0.8xVCC
-
VCC+0.3
Input Low Voltage, All inputs
VIL(1)
-
-0.3
-
0.2xVcc
Output High Voltage Level
VOH
IOH=-100μA
Vcc-0.1
-
-
Output Low Voltage Level
VOL
IOL=100uA
-
-
0.1
Output Low Current(R/B)
IOL(R/B)
VOL=0.1V
3
4
-
NOTE :
1) VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.
2) Typical value is measured at Vcc=1.8V, TA=25°C. Not 100% tested.
- 14 -
Unit
μA
V
mA
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
1.4 VALID BLOCK
Parameter
Symbol
Min
Typ.
Max
Unit
4Gb
NVB
2,008
-
2,048
Blocks
8Gb DDP
NVB
4,016
-
4,096
Blocks
NOTE :
1) The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both
cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the
attached technical notes for appropriate management of invalid blocks.
2) The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with x8 : 4bit/ 512Byte, x16 : 4bit/256Word ECC.
3) Each mono chip in the device has maximum 40 invalid blocks.
1.5 AC TEST CONDITION
(:TA=0 to 70°C, Vcc=1.7V~1.95V unless otherwise noted)
Parameter
Value
Input Pulse Levels
0V to Vcc
Input Rise and Fall Times
5ns
Input and Output Timing Levels
Vcc/2
Output Load
1 TTL GATE and CL=30pF
1.6 CAPACITANCE(TA=25°C, VCC=1.8V, f=1.0MHz)
Item
Symbol
Test Condition
Min
Max
Unit
Input/Output Capacitance (Mono)
CI/O
VIL=0V
-
10
pF
Input Capacitance (Mono)
CIN
VIN=0V
-
10
pF
Input/Output Capacitance (DDP)
CI/O
VIL=0V
-
20
pF
Input Capacitance (DDP)
CIN
VIN=0V
-
20
pF
NOTE :
Capacitance is periodically sampled and not 100% tested.
1.7 MODE SELECTION
CLE
ALE
CE
RE
WP
H
L
L
WE
H
X
L
H
L
H
X
H
L
L
H
H
L
H
L
H
H
L
L
L
H
H
L
L
L
H
X
X
X
X
H
Mode
Read Mode
Write Mode
Command Input
Address Input(5clock)
Command Input
Address Input(5clock)
Data Input
X
Data Output
X
During Read(Busy)
X
X
X
X
X
H
During Program(Busy)
X
X
X
X
X
H
During Erase(Busy)
X
X
X
L
Write Protect
H
X
X
0V/V
X
X
X
(1)
X
NOTE :
1) X can be VIL or VIH.
2) WP should be biased to CMOS high or CMOS low for standby.
- 15 -
CC(2)
Stand-by
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
1.8 Read / Program / Erase Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
-
60
μs
410
930
μs
Read Time (Data Transfer from Cell to Register)
tR
Program Time
tPROG
-
Number of Partial Program Cycles
Nop
-
-
4
cycles
Block Erase Time
tBERS
-
4.5
16
ms
NOTE :
1) Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 1.8V Vcc and 25°C temperature.
1.9 AC Timing Characteristics for Command / Address / Data Input
Parameter
Min
Max
Unit
CLS 1)
21
-
ns
CLE Hold Time
tCLH
5
-
ns
CE Setup Time
t
CS 1)
21
-
ns
tCH
5
-
ns
WE Pulse Width
tWP
21
-
ns
ALE Setup Time
tALS 1)
21
-
ns
CLE Setup Time
CE Hold Time
Symbol
t
ALE Hold Time
tALH
5
-
ns
Data Setup Time
tDS 1)
20
-
ns
Data Hold Time
tDH
5
-
ns
Write Cycle Time
tWC
40
-
ns
WE High Hold Time
tWH
10
-
ns
tADL
100
-
ns
Address to Data Loading Time
2)
NOTE :
1) The transition of the corresponding control pins must occur only once while WE is held low
2) tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle
- 16 -
KA100O015E-BJTT
Rev. 1.0
datasheet
MCP Memory
1.10 AC Characteristics for Operation
Parameter
Symbol
Min
Max
Unit
ALE to RE Delay
tAR
10
-
ns
CLE to RE Delay
tCLR
10
-
ns
Ready to RE Low
tRR
20
-
ns
RE Pulse Width
tRP
21
-
ns
WE High to Busy
tWB
-
100
ns
tWW
100
-
ns
Read Cycle Time
tRC
42
-
ns
RE Access Time
tREA
-
30
ns
CE Access Time
tCEA
-
35
ns
RE High to Output Hi-Z
tRHZ
-
100
ns
WP Low to WE Low (disable mode)
WP High to WE Low (enable mode)
CE High to Output Hi-Z
tCHZ
-
30
ns
CE High to ALE or CLE Don’t Care
tCSD
0
-
ns
RE High to Output Hold
tROH
15
-
ns
CE High to Output Hold
tCOH
15
-
ns
RE High Hold Time
tREH
10
-
ns
Output Hi-Z to RE Low
tIR
0
-
ns
ns
RE High to WE Low
tRHW
100
-
WE High to RE Low
tWHR
60
-
Device Resetting Time(Read/Program/Erase)
tRST
-
NOTE :
1) If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5μs.
- 17 -
10/20/150
ns
(1)
μs
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
2.0 NAND FLASH TECHNICAL NOTES
2.1 Initial Invalid Block(s)
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information
regarding the initial invalid block(s) is called "initial invalid block information". Devices with initial invalid block(s) have the same quality level as devices
with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the performance of valid block(s) because it
is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the initial invalid block(s) via
address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with x8:4bit/
512Byte, x16:4bit/256Word ECC.
2.2 Identifying Initial Invalid Block(s)
All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The initial invalid block(s)
status is defined by the 1st byte(1st word) in the spare area. Samsung makes sure that Both of 1st and 2nd page of every initial invalid block has all 0h
data at the column address of 4096(x16:2048). Since the initial invalid block information is also erasable in most cases, it is impossible to recover the
information once it has been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the original initial invalid block
information and create the initial invalid block table via the following suggested flow chart(Figure 5). Any intentional erasure of the original initial invalid
block information is prohibited.
Start
Block address = 0
Check if the majority of
the 1stword of column
4096 of page#0 is filled
with‘0’
Increment Block Address
No
Yes
Check if the majority of
the 1stword of column
4096 of page#1 is filled
with‘0’
No
Yes
Update invalid block table
No
Last Block
Yes
End
[Figure 5] Flow chart to create initial invalid block table
- 18 -
datasheet
KA100O015E-BJTT
Rev. 1.0
MCP Memory
NAND Flash Technical Notes (Continued)
2.3 Error in write or read operation
Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data. Block replacement
should be done upon erase or program error.
Failure Mode
Status Read after Erase --> Block Replacement
Program Failure
Status Read after Program --> Block Replacement
Up to Four Bit-Failure
Verify ECC -> ECC Correction
Write
Read
ECC
Detection and Countermeasure sequence
Erase Failure
: Error Correcting Code --> RS Code or BCH Code etc.
Example) 4bit correction & 512-byte
NOTE :
A repetitive page read operation on the same block without erase may cause bit errors, which could be accumulated over time and exceed the coverage of ECC. Software
scheme such as caching into RAM is recommended.
Program Flow Chart
Start
Write 80h
Write Address
Write Data
Write 10h
Read Status Register
I/O 6 = 1 ?
or R/B = 1 ?
*
Program Error
No
Yes
No
I/O 0 = 0 ?
Yes
Program Completed
*
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
- 19 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Start
Start
Write 60h
Write 00h
Write Block Address
Write Address
Write D0h
Write 30h
Read Status Register
Read Data
I/O 6 = 1 ?
or R/B = 1 ?
*
Read Flow Chart
ECC Generation
No
Reclaim the Error
Yes
Erase Error
No
Page Read Completed
Erase Completed
: If erase operation results in an error, map out
the failing block and replace it with another block.
Block Replacement
1st
∼
(n-1)th
nth
{
Block A
1
an error occurs.
(page)
1st
∼
(n-1)th
nth
Buffer memory of the controller.
{
Verify ECC
Yes
I/O 0 = 0 ?
Yes
*
No
Block B
2
(page)
* Step1
When an error happens in the nth page of the Block ’A’ during erase or program operation.
* Step2
Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block ’B’)
* Step3
Then, copy the nth page data of the Block ’A’ in the buffer memory to the nth page of the Block ’B’.
* Step4
Do not erase or program to Block ’A’ by creating an ’invalid block’ table or other appropriate scheme.
- 20 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
NAND Flash Technical Notes (Continued)
2.4 Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB(least significant bit) page of the block to the MSB(most significant bit) pages
of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed.
Therefore, LSB doesn't need to be page 0.
Page 63
(64)
Page 63
:
Page 31
:
(32)
Page 31
:
Page 2
Page 1
Page 0
(1)
:
(3)
(2)
(1)
Page 2
Page 1
Page 0
Data register
(3)
(32)
(2)
Data register
From the LSB page to MSB page
DATA IN: Data (1)
(64)
Ex.) Random page program (Prohibition)
Data (64)
DATA IN: Data (1)
- 21 -
Data (64)
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
2.5 System Interface Using CE don’t-care.
≈
≈
CLE
≈
For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 4,224byte data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time
on the order of μ-seconds, de-activating CE during the data-loading and serial access would provide significant savings in power consumption.
I/Ox
≈
ALE
80h
Address(5Cycles)
tCS
≈
≈≈
WE
≈ ≈
≈
CE
≈ ≈
CE don’t-care
Data Input
tCH
Data Input
10h
tCEA
CE
CE
tREA
tWP
RE
WE
out
I/Ox
≈
CLE
≈
[Figure 6] Program Operation with CE don’t-care
CE don’t-care
≈
ALE
tR
≈
R/B
≈≈
≈ ≈ ≈
RE
≈
WE
I/Ox
≈ ≈
CE
00h
Address(5Cycle)
Data Output(serial access)
30h
[Figure 7] Read Operation with CE don’t-care.
- 22 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
NOTE :
Device
I/O
DATA
ADDRESS
I/Ox
Data In/Out
Col. Add1
Col. Add2
Row Add1
Row Add2
4Gb(x8)
I/O 0 ~ I/O 7
~4,224byte
A0~A7
A8~A12
A13~A20
A21~A28
A29
8Gb DDP(x8)
I/O 0 ~ I/O 7
~4,224byte
A0~A7
A8~A12
A13~A20
A21~A28
A29~A30
4Gb(x16)
I/O 0 ~ I/O 15
~2,112Word
A0~A7
A8~A11
A12~A19
A20~A27
A28
8Gb DDP(x16)
I/O 0 ~ I/O 15
~2,112Word
A0~A7
A8~A11
A12~A19
A20~A27
A28~A29
- 23 -
Row Add3
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
3.0 TIMING DIAGRAMS
3.1 Command Latch Cycle
CLE
tCLS
tCLH
tCS
tCH
CE
tWP
WE
tALH
tALS
ALE
tDH
tDS
I/Ox
Command
3.2 Address Latch Cycle
tCLS
CLE
tCS
tWC
tWC
tWC
tWC
CE
tWP
tWP
WE
tWH
tALH
tALS
tALS
tWP
tWP
tALH
tWH
tALS
tWH
tALH
tALS
tWH
tALH
tALS
tALH
ALE
tDS
I/Ox
tDH
Col. Add1
tDS
tDH
Col. Add2
- 24 -
tDS
tDH
Row Add1
tDS
tDH
Row Add2
tDS
tDH
Row Add3
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
3.3 Input Data Latch Cycle
tCLH
≈
CLE
tCH
≈
CE
tWC
≈
ALE
tALS
tWP
tWH
tDH
tDS
tDH
tDS
tDH
≈
tDS
tWP
≈
tWP
WE
I/Ox
DIN final
DIN 1
≈
DIN 0
3.4 * Serial Access Cycle after Read (CLE=L, WE=H, ALE=L)
tRC
≈
CE
tREH
tREA
≈
tREA
tRP
tCHZ
tREA
tCOH
RE
tRHZ
tRHZ
I/Ox
Dout
Dout
≈
tROH
≈
tRR
R/B
NOTE :
Transition is measured at ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
- 25 -
Dout
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
3.5 Status Read Cycle
tCLR
CLE
tCLS
tCLH
tCS
CE
tWP
tCH
WE
tCEA
tCHZ
tCOH
tWHR
RE
tDS
I/Ox
tDH
tRHZ
tREA
tIR
tRHOH
Status Output
70h
3.6 Read Operation
tCLR
CLE
CE
tWC
WE
tWB
tAR
ALE
tR
tRHZ
tRC
≈
RE
I/Ox
00h
Col. Add1
Col. Add2
Column Address
Row Add1
Row Add2 Row Add3
30h
Dout N
Row Address
Busy
R/B
- 26 -
Dout N+1
≈ ≈
tRR
Dout M
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
3.7 Read Operation (Intercepted by CE)
tCLR
CLE
CE
tCSD
WE
tCHZ
tWB
tCOH
tAR
ALE
tRC
tR
RE
tRR
I/Ox
00h
Col. Add1
Col. Add2
Column Address
Row Add1
Row Add2 Row Add3
Dout N
30h
Row Address
R/B
Busy
- 27 -
Dout N+1
Dout N+2
- 28 -
R/B
I/Ox
RE
ALE
WE
CE
CLE
00h
Col. Add1
Col. Add2
Column Address
Row Add2 Row Add3
Row Address
Row Add1
30h
tAR
Busy
tRR
tR
tWB
Dout N
tRC
Dout N+1
tRHW
05h
Col Add1
Col Add2
Column Address
E0h
tWHR
tCLR
Dout M
tREA
Dout M+1
KA100O015E-BJTT
datasheet
Rev. 1.0
MCP Memory
3.8 Random Data Output In a Page
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
3.9 Page Program Operation
CLE
CE
tWC
≈
tWC
tWC
WE
tWB
tADL
tPROG
tWHR
ALE
I/Ox
80h
Co.l Add1 Col. Add2
SerialData
Column Address
Input Command
Row Add1
Row Add2 Row Add3
Row Address
≈ ≈
RE
Din
Din
N
M
1 up to m Byte
Serial Input
70h
Program
Command
NOTE :
tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
- 29 -
I/O0
Read Status
Command
≈
R/B
10h
I/O0=0 Successful Program
I/O0=1 Error in Program
- 30 -
Col. Add1
Col. Add2
Serial Data
Column Address
Input Command
80h
Row Add2 Row Add3
Row Address
Row Add1
tWC
tADL
Din
M
85h
Col. Add1 Col. Add2
tADL
Serial Input Random Data Column Address
Input Command
Din
N
tWC
NOTE :
1) tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
R/B
I/Ox
RE
ALE
WE
tWC
≈
≈ ≈
CE
Din
K
Serial Input
Din
J
≈
≈ ≈
CLE
10h
Program
Command
tWB
tPROG
≈
Read Status
Command
70h
tWHR
I/O0
KA100O015E-BJTT
datasheet
Rev. 1.0
MCP Memory
3.10 Page Program Operation with Random Data Input
- 31 -
00h
tWC
Column Address
Row Address
Col Add1 Col Add2 Row Add1 Row Add2 Row Add3
35h
tR
tWB
Busy
Data 1
tRC
≈ ≈
Data N
85h
tADL
Column Address
Row Address
Col Add1 Col Add2 Row Add1 Row Add2 Row Add3 Data 1
Copy-Back Data
NOTE :
Input Command
1) tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
R/B
I/Ox
RE
ALE
WE
CE
≈
CLE
Data N 10h
tWB
70h
I/Ox
tWHR
Read Status Command
tPROG
I/O0=0 Successful Program
I/O0=1 Error in Program
Busy
≈
KA100O015E-BJTT
datasheet
Rev. 1.0
MCP Memory
3.11 Copy-Back Program Operation with Random Data Input
≈ ≈
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
3.12 Block Erase Operation
CLE
CE
tWC
WE
tWB
tBERS
tWHR
ALE
RE
I/Ox
60h
Row Add1 Row Add2 Row Add3
D0h
70h
I/O 0
Busy
R/B
Auto Block Erase
Setup Command
Erase Command
≈
Row Address
Read Status
Command
- 32 -
I/O0=0 Successful Erase
I/O0=1 Error in Erase
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
3.13 Read ID Operation
CLE
CE
WE
tAR
ALE
RE
tREA
I/Ox
00h
90h
Read ID Command
Address 1cycle
Device
Code
ECh
3rd cyc.
4th cyc.
5th cyc.
Maker Code Device Code
Device
Device Code (2nd Cycle)
3rd Cycle
4th Cycle
5th Cycle
4Gb(x8)
ACh
00h
26h
56h
8Gb DDP(x8)
A3h
01h
26h
5Ah
4Gb(x16)
BCh
00h
66h
56h
8Gb DDP(x16)
B3h
01h
66h
5Ah
3.13.1 ID Definition Table
90 ID : Access command = 90H
Description
1st Byte
2nd Byte
3rd Byte
4th Byte
5th Byte
Maker Code
Device Code
Internal Chip Number
Page Size, Block Size,Redundant Area Size, Organization
Plane Number, Plane Size, ECC Level
- 33 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
3rd ID Data
ITEM
Description
Internal Chip Number
1
2
4
8
Cell Type
2 Level Cell
4 Level Cell
8 Level Cell
16 Level Cell
Number of Simultaneously
Programmed Pages
1
2
4
8
Interleave Program
Between Multii-Chips
Not supported
supported
Cache Program
Not supported
supported
I/O #
7
6
5
0
0
1
1
4
3
2
0
0
1
1
0
1
0
1
3
2
1
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
4th ID Data
ITEM
Description
Page Size
(without Redundant Area)
1KB
2KB
4KB
8KB
Block Size
(without Redundant Area)
64KB
128KB
256KB
512KB
Redundant Area Size
(Byte/512byte)
8
16
Reserved
Reserved
Organization
X8
X16
Reserved
I/O #
7
6
5
0
0
1
1
4
1
0
0
0
1
1
0
1
0
1
1
0
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
3
2
0
1
0 or 1
5th ID Data
ITEM
Description
ECC level
1bit ECC/512Byte
2bit ECC/512Byte
4bit ECC/512Byte
Reserved
Plane Number
1
2
4
8
Plane Size
(without Redundant Area)
64KB
128KB
256KB
512KB
1Gb
2Gb
4Gb
8Gb
Reseved
Reserved
I/O #
7
6
5
4
0
0
1
1
0
0
0
0
1
1
1
1
0
- 34 -
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
datasheet
KA100O015E-BJTT
Rev. 1.0
MCP Memory
4.0 DEVICE OPERATION
4.1 PAGE READ
Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 4,224 bytes(2,112 Wrods) of data within the selected
page are transferred to the data registers in 60μs(tR) typically. The system controller can detect the completion of this data transfer(tR) by analyzing the
output of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in 42ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the data starting from the selected column address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data output command. The column address
of next data, which is going to be out, may be changed to the address which follows random data output command. Random data output can be operated
multiple times regardless of how many times it is done in a page.
≈
CLE
≈
CE
≈≈
WE
≈
ALE
RE
I/Ox
tR
≈
R/B
00h
Address(5Cycle)
Data Output(Serial Access)
30h
Col. Add.1,2 & Row Add.1,2,3
Data Field
Spare Field
[Figure 8] Read Operation
- 35 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
4.2 PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte(a word) or consecutive byte up to
4,224 Bytes(2,112 Words), in a single page program cycle. The number of consecutive partial page programming operation within the same page without
an intervening erase operation must not exceed 4 times for a single page. The addressing should be done in sequential order in a block. A page program
cycle consists of a serial data loading period in which up to 4,224 Bytes(2,112 Words) of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and then serial data
loading. The bytes(words) other than those to be programmed do not need to be loaded. The device supports random data input in a page. The column
address for the next data, which will be entered, may be changed to the address which follows random data input command(85h). Random data input
may be operated multiple times regardless of how many times it is done in a page.
The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate
the programming process. The internal write state controller automatically executes the algorithms and timings necessary for program and verify, thereby
freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only
the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/
O 0) may be checked(Figure 9). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register
remains in Read Status command mode until another valid command is written to the command register.
tPROG
R/B
"0"
I/Ox
80h
Address & Data Input
10h
Pass
I/O0
70h
Col. Add.1,2 & Row Add.1,2,3
"1"
Data
Fail
[Figure 9] Program & Read Status Operation
tPROG
R/B
"0"
I/Ox
80h
Address & Data Input
Col. Add.1,2 & Row Add1,2,3
Data
85h
Address & Data Input
10h
Col. Add.1,2
Data
70h
I/O0
"1"
Fail
[Figure 10] Random Data Input In a Page
- 36 -
Pass
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
4.3 COPY-BACK PROGRAM
Copy-Back program with Read for Copy-Back is configured to quickly and efficiently rewrite data stored in one page without data re-loading when the bit
error is not in data stored. Since the time-consuming re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also needs to be copied to the newly assigned free block. Copy-Back operation is a
sequential execution of Read for Copy-Back and of copy-back program with the destination page address. A read operation with "35h" command and the
address of the source page moves the whole 4,224 Bytes(2,112 Words) data into the internal data buffer. A bit error is checked by sequential reading the
data output. In the case where there is no bit error, the data do not need to be reloaded. Therefore Copy-Back program operation is initiated by issuing
Page-Copy Data-Input command (85h) with destination page address. Actual programming operation begins after Program Confirm command (10h) is
issued. Once the program process starts, the Read Status Register command (70h) may be entered to read the status register. The system controller can
detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. When the Copy-Back Program is
complete, the Write Status Bit(I/O 0) may be checked(Figure 11 & Figure 12). The command register remains in Read Status command mode until
another valid command is written to the command register.
During copy-back program, data modification is possible using random data input command (85h) as shown in Figure 12.
tR
tPROG
≈
R/B
00h
Add.(5Cycles)
Data Output
35h
≈
I/Ox
Col. Add.1,2 & Row Add.1,2,3
Source Address
85h
Add.(5Cycles)
10h
70h
I/O0
Col. Add.1,2 & Row Add.1,2,3
Destination Address
"0"
Pass
"1"
Fail
[Figure 11] Page Copy-Back Program Operation
NOTE :
1) Copy-Back Program operation is allowed only within the same memory plane.
≈
00h
Add.(5Cycles)
35h
Col. Add.1,2 & Row Add.1,2,3
Source Address
Data Output
≈
I/Ox
tPROG
tR
R/B
85h
Add.(5Cycles)
Data
Col. Add.1,2 & Row Add.1,2,3
Destination Address
85h
Add.(2Cycles)
10h
Col. Add.1,2
There is no limitation for the number of repetition.
[Figure 12] Page Copy-Back Program Operation with Random Data Input
- 37 -
Data
70h
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
4.4 BLOCK ERASE
The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command(60h). Only
Block address is valid while page address is ignored. The Erase Confirm command(D0h) following the block address loading initiates the internal erasing
process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external
noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the erase operation is
completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence.
tBERS
R/B
"0"
I/Ox
60h
Address Input(3Cycle)
70h
D0h
Pass
I/O0
"1"
Row Add 1,2,3
Fail
[Figure 13] Block Erase Operation
4.5 READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase
operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/
O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to Table 4 for specific Status
Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read
during a random read cycle, the read command(00h) should be given before starting read cycles.
[Table 4] Status Register Definition for 70h Command
I/O
Page Program
Block Erase
Read
Definition
I/O 0
Pass/Fail
Pass/Fail
Not Use
I/O 1
Not use
Not use
Not use
Don’t -cared
I/O 2
Not use
Not use
Not use
Don’t -cared
I/O 3
Not Use
Not Use
Not use
Don’t -cared
I/O 4
Not Use
Not Use
Not Use
Don’t -cared
I/O 5
Not Use
Not Use
Not Use
Don’t -cared
I/O 6
Ready/Busy
Ready/Busy
Ready/Busy
I/O 7
Write Protect
Write Protect
Write Protect
Pass : "0"
NOTE :
1) I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.
- 38 -
Busy : "0"
Protected : "0"
Fail : "1"
Ready : "1"
Not Protected : "1"
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
4.6 Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Five read cycles
sequentially output the manufacturer code(ECh), and the device code and 3rd, 4th, 5th cycle ID respectively. The command register remains in Read ID
mode until further commands are issued to it. Figure 14 shows the operation sequence.
tCLR
CLE
tCEA
CE
WE
tAR
ALE
tWHR
RE
I/OX
90h
tREA
00h
ECh
Maker code
Address. 1cycle
Device
Code
4th Cyc.
3rd Cyc.
5th Cyc.
Device code
[Figure 14] Read ID Operation
Device
Device Code (2nd Cycle)
3rd Cycle
4th Cycle
5th Cycle
4Gb(x8)
ACh
00h
26h
56h
8Gb DDP(x8)
A3h
01h
26h
5Ah
4Gb(x16)
BCh
00h
66h
56h
8Gb DDP(x16)
B3h
01h
66h
5Ah
4.7 RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or
erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially
programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high.
If the device is already in reset state a new reset command will be accepted by the command register. The R/B pin changes to low for tRST after the
Reset command is written. Refer to Figure 15 below.
tRST
R/B
I/OX
FFh
[Figure 15] RESET Operation
[Table 5] Device Status
Operation mode Mode
After Power-up
After Reset
00h Command is latched
Waiting for next command
- 39 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
4.8 READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/
B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address
loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs
to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig.17). Its value can be determined by the following guidance.
Vcc
Rp
VCC
ibusy
1.8V device - VOL : 0.1V, VOH : VCC-0.1V
Ready Vcc
VOH
R/B
open drain output
VOL
CL
Busy
tf
tr
GND
Device
[Figure 16] Rp vs tr ,tf & Rp vs ibusy
2m
1.70
Ibusy
400
346
259
0.89
200
86
tr
0.60
173
1m
0.45
tf
2.7
1K
2.6
2.6
2K
3K
Rp(ohm)
Rp value guidance
Rp(min, 1.8V part) =
1.85V
VCC(Max.) - VOL(Max.)
IOL + ΣIL
Ibusy [A]
tr,tf [ns]
@ Vcc = 1.8V, Ta = 25°C , CL = 30pF
=
3mA + ΣIL
where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp(max) is determined by maximum permissible limit of tr
- 40 -
2.5
4K
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
5.0 DATA PROTECTION & POWER UP SEQUENCE
≈
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions
whenever Vcc is below about 1.1V. WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down. A
recovery time of minimum 1ms is required before internal circuit gets ready for any command sequences as shown in Figure 17. The two step command
sequence for program/erase provides additional software protection.
~ 1.5V
~ 1.5V
High
≈
VCC
≈
WP
Don’t care
≈
WE
Operation
Ready/Busy
1ms
≈
5 ms max
Invalid
Don’t care
[Figure 17] AC Waveforms for Power Transition
- 41 -
datasheet
KA100O015E-BJTT
5.1 WP AC TIMING GUIDE
Enabling WP during erase and program busy is prohibited.
The erase and program operations are enabled and disabled as follows:
≈
1. Enable Mode
WE
I/O
80h
10h
WP
R/B
tww(min.100ns)
≈
2. Disable Mode
WE
I/O
80h
10h
WP
R/B
tww(min.100ns)
[Figure 18] Program Operation
≈
1. Enable Mode
WE
I/O
60h
D0h
WP
R/B
tww(min.100ns)
≈
2. Disable Mode
WE
I/O
60h
WP
R/B
tww(min.100ns)
[Figure 19] Erase Operation
- 42 -
D0h
Rev. 1.0
MCP Memory
KA100O015E-BJTT
datasheet
Rev. 1.0
MCP Memory
2Gb (64M x32) Mobile DDR SDRAM C-die
- 43 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
1.0 FUNCTIONAL DESCRIPTION
POWER
APPLIED
POWER
ON
PARTIAL
SELF
REFRESH SELF
REFRESH
PRECHARGE
REFS
ALL BANKS
REFSX
MRS
EMRS
MRS
IDLE
ALL BANKS
PRECHARGED
REFA
AUTO
REFRESH
CKEL
CKEH
ACT
POWER
DOWN
POWER
DOWN
CKEH
ROW
ACTIVE
CKEL
BURST STOP
WRITE
READ
WRITEA
WRITEA
WRITE
READA
READ
WRITEA
READ
READA
READA
PRE
WRITEA
PRE
PRE
READA
PRE
PRECHARGE
PREALL
Automatic Sequence
Command Sequence
Figure 1. State diagram
- 44 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
2.0 MODE REGISTER DEFINITION
2.1 Mode Register Set (MRS)
The mode register is designed to support the various operating modes of Mobile DDR SDRAM. It includes Cas latency, addressing mode, burst length,
test mode and vendor specific options to make Mobile DDR SDRAM useful for variety of applications. The mode register is written by asserting low on
CS, RAS, CAS and WE (The Mobile DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The states of
address pins A0 ~ A13 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the mode register. Two clock cycles are
required to complete the write operation in the mode register. Even if the power-up sequence is finished and some read or write operation is executed
afterward, the mode register contents can be changed with the same command and two clock cycles. This command must be issued only when all banks
are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A3,
Cas latency (read latency from column address) uses A4 ~ A6, A7 ~ A13 is used for test mode. BA0 and BA1 must be set to low for proper MRS operation.
BA1
0
BA0
0
A13 ~ A10/AP
RFU1)
A9
A8
A7
0
0
0
A6
A5
A4
CAS Latency
A3
BT
A2
A1
A0
Mode Register
Burst Length
A3
Burst Type
0
Sequential
1
Interleave
Address Bus
A6
A5
A4
CAS Latency
A2
A1
A0
Burst Type
0
0
0
Reserved
0
0
0
Reserved
0
0
1
Reserved
0
0
1
2
0
1
0
Reserved
0
1
0
4
0
1
1
3
0
1
1
8
1
0
0
Reserved
1
0
0
16
1
0
1
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
0
Reserved
1
1
1
Reserved
1
1
1
Reserved
Figure 2. Mode Register Set
NOTE :
1) RFU (Reserved for future use) should stay "0" during MRS cycle
- 45 -
datasheet
KA100O015E-BJTT
Rev. 1.0
MCP Memory
[Table 1] Burst address ordering for burst length
Burst
Length
2
4
8
16
Starting Address
(A3, A2, A1, A0)
Sequential Mode
Interleave Mode
xxx0
0, 1
0, 1
xxx1
1, 0
1, 0
xx00
0, 1, 2, 3
0, 1, 2, 3
xx01
1, 2, 3, 0
1, 0, 3, 2
xx10
2, 3, 0, 1
2, 3, 0, 1
xx11
3, 0, 1, 2
3, 2, 1, 0
x000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
x001
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
x010
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
x011
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
x100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
x101
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
x110
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
x111
7, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0
0000
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15
0001
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0
1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11,10,13,12,15,14
0010
2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1
2, 3, 0, 1, 6, 7, 4, 5,10,11, 8, 9, 14,15,12,13
0011
3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4,11,10, 9, 8, 15,14,13,12
0100
4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3,12,13,14,15, 8, 9, 10,11
0101
5, 6, 7,8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2,13,12,15,14, 9, 8,11,10
0110
6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1,14,15,12,13,10,11, 8, 9
0111
7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0, 15,14,13,12,11,10, 9, 8
1000
8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6, 7
8, 9,10,11,12,13,14,15, 0, 1, 2, 3, 4, 5, 6, 7
1001
9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6, 7, 8
9, 8, 11,10,13,12,15,14,1, 0, 3, 2, 5, 4, 7, 6
1010
10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9
10,11, 8, 9, 14,15,12,13, 2, 3, 0, 1, 6, 7, 4, 5
1011
11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10
11,10, 9, 8, 15,14,13,12, 3, 2, 1, 0, 7, 6, 5, 4
1100
12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11
12,13,14,15, 8, 9, 10,11, 4, 5, 6, 7, 0, 1, 2, 3
1101
13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,12
13,12,15,14, 9, 8,11,10, 5, 4, 7, 6, 1, 0, 3, 2
1110
14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
14,15,12,13,10,11, 8, 9, 6, 7, 4, 5, 2, 3, 0, 1
1111
15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
15,14,13,12,11,10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
- 46 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
2.2 Extended Mode Register Set (EMRS)
The extended mode register is designed to support for the desired operating modes of DDR SDRAM. The extended mode register is written by asserting
low on CS, RAS, CAS, WE and high on BA1, low on BA0(The Mobile DDR SDRAM should be in all bank precharge with CKE already high prior to writing
into the extended mode register). The state of address pins A0 ~ A13 in the same cycle as CS, RAS, CAS and WE going low is written in the extended
mode register. Two clock cycles are required to complete the write operation in the extended mode register. Even if the power-up sequence is finished
and some read or write operations is executed afterward, the mode register contents can be changed with the same command and two clock cycles. But
this command must be issued only when all banks are in the idle state. A0 - A2 are used for partial array self refresh and A5 - A7 are used for driver
strength control. "High" on BA1 and "Low" on BA0 are used for EMRS. All the other address pins except A0,A1,A2,A5,A6,A7, BA1, BA0 must be set to
low for proper EMRS operation. Refer to the table for specific codes.
BA1
BA0
1
0
A13 ~ A10/AP
RFU1)
A9
A8
0
0
A7
A6
A5
A4
A3
A2
RFU1)
DS
A1
A0
Mode Register
PASR
DS
Address Bus
PASR
A7
A6
A5
Driver Strength
A2
A1
A0
Refreshed Area
0
0
0
Full
0
0
0
Full Array
0
0
1
1/2
0
0
1
1/2 Array
0
1
0
1/4
0
1
0
1/4 Array
0
1
1
1/8
0
1
1
Reserved
1
0
0
3/4
1
0
0
Reserved
1
0
1
3/8
1
0
1
Reserved
1
1
0
5/8
1
1
0
Reserved
1
1
1
7/8
1
1
1
Reserved
Figure 3. Extended Mode Register Set
NOTE :
1) RFU (Reserved for future use) should stay "0" during EMRS cycle
- 47 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
2.3 Internal Temperature Compensated Self Refresh (TCSR)
1. In order to save power consumption, this Mobile DRAM includes the internal temperature sensor and control units to control the self refresh cycle automatically according to the real device temperature.
2. TCSR ranges for IDD6 shown in the table are only examples.
3. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.
Self Refresh Current (IDD6)
Temperature Range
Full Array
1/2 Array
1/4 Array
85 °C
1700
1400
1200
45 °C
400
270
200
Unit
uA
NOTE :
1) IDD6 85°C are guaranteed, IDD6 45°C are typical value.
2.4 Partial Array Self Refresh (PASR)
1. In order to save power consumption, Mobile DDR SDRAM includes PASR option.
2. Mobile DDR SDRAM supports three kinds of PASR in self refresh mode; Full array, 1/2 Array, 1/4 Array.
BA1=0
BA0=0
BA1=0
BA0=1
BA1=0
BA0=0
BA1=0
BA0=1
BA1=0
BA0=0
BA1=0
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
- Full Array
- 1/2 Array
- 1/4 Array
Partial Self Refresh Area
Figure 4. EMRS code and TCSR, PASR
- 48 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
3.0 ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VIN, VOUT
- 0.5 ~ 2.7
V
Voltage on VDD supply relative to VSS
VDD
- 0.5 ~ 2.7
V
Voltage on VDDQ supply relative to VSS
VDDQ
- 0.5 ~ 2.7
V
Storage temperature
TSTG
- 55 ~ + 150
°C
Power dissipation
PD
1.0
W
Short circuit current
IOS
50
mA
NOTE :
1) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
2) Functional operation should be restricted to recommend operation condition.
3) Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
4.0 DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS=0V, TC = -25°C to 85°C)
Parameter
Supply voltage (for device with a nominal VDD of 1.8V)
I/O Supply voltage
Input logic high voltage
Input logic low voltage
Address
Data
Address
Data
Symbol
Min
Max
Unit
Note
VDD
1.7
1.95
V
1
VDDQ
1.7
1.95
V
1
0.8 x VDDQ
VDDQ + 0.3
V
0.7 x VDDQ
VDDQ + 0.3
V
-0.3
0.2 x VDDQ
V
-0.3
0.3 x VDDQ
V
VIH(DC)
VIL(DC)
2
2
Output logic high voltage
VOH(DC)
0.9 x VDDQ
-
V
IOH = - 0.1mA
Output logic low voltage
VOL(DC)
-
0.1 x VDDQ
V
IOL = 0.1mA
II
-2
2
uA
3
IOZ
-5
5
uA
Input leakage current
Output leakage current
NOTE :
1) Under all conditions, VDDQ must be less than or equal to VDD.
2) These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation.
3) Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
- 49 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
5.0 DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, Tc = -25 to 85°C)
Parameter
Symbol
Operating Current
(One Bank Active)
DDR400
Unit
tRC=tRCmin; tCK=tCKmin; CKE is HIGH; CS is HIGH between valid commands;
address inputs are SWITCHING; data bus inputs are STABLE
70
mA
IDD2P
all banks idle, CKE is LOW; CS is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
1.0
IDD2PS
all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
1.0
IDD2N
all banks idle, CKE is HIGH; CS is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
8
IDD2NS
all banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
4
IDD3P
one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
6
IDD3PS
one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
5
IDD3N
one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
15
IDD3NS
one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
10
one bank active; BL=4; CL=3; tCK = tCKmin; continuous read bursts; I OUT =0 mA
address inputs are SWITCHING; 50% data change each burst transfer
100
IDD0
Precharge Standby Current
in power-down mode
Precharge Standby Current
in non power-down mode
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
IDD4R
Operating Current
(Burst Mode)
Test Condition
mA
mA
mA
mA
one bank active; BL = 4; tCK = tCKmin; continuous write bursts;
IDD4W
address inputs are SWITCHING; 50% data change each burst transfer
Refresh Current
IDD5
160
TCSR Range
Self Refresh Current
IDD6
Full Array
1/2 Array
1/4 Array
mA
80
tRC ≥ tRFC; tCK = tCKmin; burst refresh; CKE is HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
CKE is LOW; t CK = t CKmin;
Extended Mode Register set to all 0’s;
address and control inputs are STABLE;
data bus inputs are STABLE
1700
45°C
400
85°C
1400
45°C
270
85°C
1200
45°C
200
1) IDD5 is measured in the below test condition.
128Mb
256Mb
512Mb
1Gb
2Gb
Unit
tRFC
80
80
110
140
140
ns
2) IDD specifications are tested after the device is properly initialized.
3) Input slew rate is 1V/ns.
4) Definitions for IDD: LOW is defined as V IN ≤ 0.1 * VDDQ;
HIGH is defined as V IN ≥ 0.9 * VDDQ;
STABLE is defined as inputs stable at a HIGH or LOW level;
SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once per two clock cycles;
- data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE.
5) IDD6 85°C are guaranteed, IDD6 45°C are typical value.
- 50 -
mA
1
Values
85°C
NOTE :
Density
Note
uA
uA
uA
5
KA100O015E-BJTT
Rev. 1.0
datasheet
MCP Memory
6.0 AC OPERATING CONDITIONS & TIMMING SPECIFICATION
Parameter/Condition
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, all inputs
VIH (AC)
0.8 x VDDQ
VDDQ + 0.3
V
1
Input Low (Logic 0) Voltage, all inputs
VIL (AC)
-0.3
0.2 x VDDQ
V
1
Input Crossing Point Voltage, CK and CK inputs
VIX (AC)
0.4 x VDDQ
0.6 x VDDQ
V
2
NOTE :
1) These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation.
2) The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
- 51 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
7.0 AC TIMMING PARAMETERS & SPECIFICATIONS
Parameter
Symbol
DDR400
Min
Max
Unit
Note
1,2
tCK
5
ns
Row cycle time
tRC
55
ns
Row active time
tRAS
40
RAS to CAS delay
tRCD
15
ns
tRP
15
ns
Row active to Row active delay
tRRD
10
ns
Write recovery time
tWR
12
ns
Last data in to Active delay
tDAL
-
-
Last data in to Read command
tCDLR
2
tCK
Col. address to Col. address delay
tCCD
1
tCK
Clock high level width
tCH
0.45
0.55
tCK
Clock low level width
tCL
0.45
0.55
tCK
Clock cycle time
CL=3
Row precharge time
70,000
ns
DQ Output data access time from CK / CK
CL=3
tAC
2
5
ns
DQS Output data access time from CK / CK
CL=3
tDQSCK
2
5
ns
0.4
ns
tDQSQ
Data strobe edge to output data edge
tRPRE
0.9
1.1
tCK
Read Postamble
tRPST
0.4
0.6
tCK
CK to valid DQS-in
tDQSS
0.75
1.25
tCK
DQS-in setup time
tWPRES
0
ns
DQS-in hold time
tWPREH
0.25
tCK
DQS-in high level width
tDQSH
0.4
0.6
tCK
DQS-in low level width
tDQSL
0.4
0.6
tCK
DQS falling edge to CK setup time
tDSS
0.2
tCK
DQS falling edge hold time from CK
tDSH
0.2
tCK
DQS-in cycle time
tDSC
0.9
Read Preamble
Address and Control
Input setup time
Address and Control
Input hold time
CL=3
fast slew rate
slow slew rate
fast slew rate
slow slew rate
DQ & DM hold time to DQS
tIH
tIPW
Address & Control input pulse width
DQ & DM setup time to DQS
tIS
fast slew rate
slow slew rate
fast slew rate
slow slew rate
tDS
tDH
1.1
0.9
0.9
ns
1.1
ns
0.58
0.48
ns
0.58
DQ & DQS low-impedence time from CK / CK
tLZ
1.0
ns
DQ & DQS high-impedence time from CK / CK
tHZ
- 52 -
8
7
0.4
6,7
6,8
6,7
6,8
ns
tWPST
7
2.2
0.48
1.2
DQS write postamble time
5
8
tDIPW
DQ & DM input pulse width
4
tCK
ns
1.1
3
5
ns
0.6
tCK
Rev. 1.0
datasheet
KA100O015E-BJTT
Parameter
Symbol
tWPRE
DQS write preamble time
MCP Memory
DDR400
Min
Max
0.25
Unit
Note
tCK
Refresh interval time
tREF
Mode register set cycle time
tMRD
2
tCK
Power down exit time
tPDEX
2
tCK
CKE min. pulse width (high and low pulse width)
tCKE
2
tCK
Auto refresh cycle time
tRFC
120
ns
Exit self refresh to active command
tXSR
120
ns
Data hold from DQS to earliest DQ edge
tQH
tHPmin - tQHS
ns
Data hold skew factor
tQHS
64
0.5
ms
9
ns
Clock half period
tHP
tCLmin or tCHmin
ns
Clock half period
tHP
tCLmin or
tCHmin
ns
NOTE :
1) tCK (max) value is measured at 100ns.
2) The only time that the clock Frequency is allowed to be changed is during clock stop, power-down, self-refresh modes.
3) In case of below 33MHz (tCK=30ns) condition, SEC could support tDAL (=2*tCK).
tDAL =(tWR/tCK) + (tRP/tCK)
4) tAC (min) value is measured at the high Vdd(1.95V) and cold temperature (-25°C).
tAC (max) value is measured at the low Vdd(1.7V) and hot temperature (85°C).
tAC is measured in the device with half driver strength and under the AC output load condition (Fig.6 in next Page).
5) The specific requirement is that DQS be valid (High or Low) on or before this CK edge. The case shown (DQS going from High_Z to logic Low) applies when no
writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS.
6) I/O Delta Rise/Fall Rate(1/slew-rate) Derating
Data Rise/Fall Rate
ΔtDS
ΔtDH
(ns/V)
(ps)
(ps)
0
0
0
±0.25
+50
+50
±0.5
+100
+100
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calculated as 1/SlewRate1-1/SlewRate2. For
example, if slew rate 1 = 1.0V/ns and slew rate 2 =0.8V/ns, then the Delta Rise/Fall Rate =-0.25ns/V.
7) Input slew rate 1.0 V/ ns.
8) Input slew rate 0.5V/ns and < 1.0V/ns.
9) Maximum burst refresh cycle : 8
- 53 -
datasheet
KA100O015E-BJTT
Rev. 1.0
MCP Memory
8.0 AC OPERATING TEST CONDITIONS (VDD = 1.7V to 1.95V, TC = -25°C to 85°C)
Parameter
Value
Unit
AC input levels (Vih/Vil)
0.8 x VDDQ / 0.2 x VDDQ
V
Input timing measurement reference level
0.5 x VDDQ
V
Input signal minimum slew rate
1.0
V/ns
Output timing measurement reference level
0.5 x VDDQ
V
Output load condition
See Figure 6
1.8V
13.9KΩ
- VOH (DC) = 0.9 x VDDQ, IOH = -0.1mA
Output
- VOL (DC) = 0.1 x VDDQ, IOL = 0.1mA
20pF
10.6KΩ
Figure 5. DC Output Load Circuit
Vtt=0.5 x VDDQ
50Ω
Output
Z0=50Ω
Test load values need to be proportional to the driver strength
which is set by the controller.
- Test load for Full Driver Strength Buffer (20pF)
- Test load for Half Driver Strength Buffer (10pF)
Figure 6. AC Output Load Circuit 1), 2)
NOTE :
1) The circuit shown above represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate
the timing reference load to system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester
electronics). For the half driver strength with a nominal 10pF load parameters tAC and tQH are expected to be in the same range. However, these parameters are not subject to
production test but are estimated by design / characterization. Use of IBIS or other simulation tools for system design validation is suggested.
2) Based on nominal impedance at 0.5 x VDDQ.
The impedence for Half(1/2) Driver Strength is designed 55ohm. And for other Driver Strength, it is designed proportionally.
- 54 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
9.0 INPUT/OUTPUT CAPACITANCE (VDD=1.8, VDDQ=1.8V, TC = 25°C, f=100MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance
(A0 ~ A13, BA0 ~ BA1, CKE, CS, RAS,CAS, WE)
CIN1
1.5
3.0
pF
Input capacitance (CK, CK)
CIN2
1.5
3.5
pF
Data & DQS input / output capacitance
COUT
2.0
4.5
pF
Input capacitance (DM)
CIN3
2.0
4.5
pF
- 55 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
10.0 AC OVERSHOOT/UNDERSHOOT SPECIFICATION FOR ADDRESS & CONTROL PINS
Parameter
Specification
Maximum peak Amplitude allowed for overshoot area
0.9V
Maximum peak Amplitude allowed for undershoot area
0.9V
Maximum overshoot area above VDD
3V-ns
Maximum undershoot area below VSS
3V-ns
Maximum Amplitude
Overshoot Area
Volts
(V)
VDD
VSS
Maximum Amplitude
Undershoot Area
Time (ns)
Figure 7. AC Overshoot and Undershoot Definition for Address and Control Pins
11.0 AC OVERSHOOT/UNDERSHOOT SPECIFICATION FOR CK, DQ, DQS AND DM PINS
Parameter
Specification
Maximum peak Amplitude allowed for overshoot area
0.9V
Maximum peak Amplitude allowed for undershoot area
0.9V
Maximum overshoot area above VDDQ
3V-ns
Maximum undershoot area below VSSQ
3V-ns
Maximum Amplitude
Overshoot Area
Volts
(V)
VDDQ
VSSQ
Maximum Amplitude
Undershoot Area
Time (ns)
Figure 8. AC Overshoot and Undershoot Definition for CK, DQ, DQS and DM Pins
- 56 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
12.0 COMMAND TRUTH TABLE
Command
Register
Mode Register Set
Auto Refresh
Refresh
Entry
Self
Refresh
Exit
Write &
Column Address
CKEn
CS
RAS
CAS
WE
H
X
L
L
L
L
OP CODE
L
L
L
H
X
L
H
H
H
H
X
X
X
H
H
L
BA0,1
L
H
H
X
L
L
H
H
V
H
X
L
H
L
H
V
H
X
L
H
L
L
V
H
X
L
H
H
L
H
X
L
L
H
L
Entry
H
L
H
X
X
X
L
H
H
H
Exit
L
H
X
X
X
X
Entry
H
L
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
Bank Active & Row Addr.
Read &
Column Address
CKEn-1
Burst Stop
Bank Selection
Precharge
All Banks
Active Power Down
Exit
L
DM
H
No operation (NOP) : Not defined
H
H
X
X
H
X
X
X
L
H
H
H
3
3
3
3
Column
Address
(A0~A9)
H
X
V
L
X
H
4
4
4
4, 6
7
X
5
X
X
X
H
1, 2
Column
Address
(A0~A9)
L
Precharge Power Down
Note
Row Address
L
Auto Precharge Disable
Auto Precharge Enable
A13~11,
A9~A0
X
Auto Precharge Disable
Auto Precharge Enable
A10/AP
X
8
9
9
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
NOTE :
1) OP Code : Operand Code. A0 ~ A13 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2) EMRS / MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3) Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4) BA0 ~ BA1 : Bank select addresses.
5) If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6) During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7) Burst stop command is valid at every burst length.
8) DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9) This combination is not defined for any function, which means "No Operation(NOP)" in Mobile DDR SDRAM.
- 57 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
13.0 FUNCTIONAL TRUTH TABLE
Current State
PRECHARGE
STANDBY
ACTIVE
STANDBY
CS
RAS
CAS
WE
Address
Command
Action
L
H
H
L
X
Burst Stop
ILLEGAL 2)
L
H
L
X
BA, CA, A10
READ/WRITE
ILLEGAL 2)
L
L
H
H
BA, RA
Active
Bank Active, Latch RA
L
L
H
L
BA, A10
PRE/PREA
ILLEGAL 4)
L
L
L
H
X
Refresh
AUTO-Refresh 5)
L
L
L
L
Op-Code, Mode-Add
MRS
Mode Register Set 5)
L
H
H
L
X
Burst Stop
NOP
L
H
L
H
BA, CA, A10
READ/READA
Begin Read, Latch CA,
Determine Auto-Precharge
L
H
L
L
BA, CA, A10
WRITE/WRITEA
Begin Write, Latch CA,
Determine Auto-Precharge
L
L
H
H
BA, RA
Active
Bank Active/ILLEGAL 2)
L
L
H
L
BA, A10
PRE/PREA
Precharge/Precharge All
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
L
H
H
L
X
Burst Stop
Terminate Burst
READ/READA
Terminate Burst, Latch CA,
Begin New Read, Determine
L
H
L
H
BA, CA, A10
Auto-Precharge 3)
READ
L
H
L
L
BA, CA, A10
WRITE/WRITEA
ILLEGAL
L
L
H
H
BA, RA
Active
Bank Active/ILLEGAL 2)
L
L
H
L
BA, A10
PRE/PREA
Terminate Burst, Precharge 10)
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
L
H
H
L
X
Burst Stop
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
Terminate Burst With DM=High, Latch
CA, Begin Read, Determine Auto-Precharge 3)
L
H
L
L
BA, CA, A10
WRITE/WRITEA
Terminate Burst, Latch CA,
Begin new Write, Determine Auto-Precharge 3)
WRITE
Bank Active/ILLEGAL 2)
L
L
H
H
BA, RA
Active
L
L
H
L
BA, A10
PRE/PREA
L
L
L
H
X
Refresh
ILLEGAL
Terminate Burst With DM=High,
Precharge 10)
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
L
H
H
L
X
Burst Stop
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
NOTE6
READ with
AUTO
L
H
L
L
BA, CA, A10
WRITE/WRITEA
ILLEGAL
PRECHARGE6)
L
L
H
H
BA, RA
Active
NOTE6
(READA)
L
L
H
L
BA, A10
PRE/PREA
NOTE6
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
- 58 -
datasheet
KA100O015E-BJTT
Current State
Rev. 1.0
MCP Memory
CS
RAS
CAS
WE
Address
Command
Action
L
H
H
L
X
Burst Stop
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
NOTE7
WRITE with AUTO
L
H
L
L
BA, CA, A10
WRITE/WRITEA
NOTE7
RECHARGE7)
(WRITEA)
L
L
H
H
BA, RA
Active
NOTE7
L
L
H
L
BA, A10
PRE/PREA
NOTE7
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
L
H
H
L
X
Burst Stop
ILLEGAL 2)
L
H
L
X
BA, CA, A10
READ/WRITE
ILLEGAL 2)
L
L
H
H
BA, RA
Active
ILLEGAL 2)
L
L
H
L
BA, A10
PRE/PREA
NOP 4 )(Idle after tRP)
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
L
H
H
L
X
Burst Stop
ILLEGAL 2)
L
H
L
X
BA, CA, A10
READ/WRITE
ILLEGAL 2)
L
L
H
H
BA, RA
Active
ILLEGAL 2)
L
L
H
L
BA, A10
PRE/PREA
ILLEGAL 2)
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
L
H
H
L
X
Burst Stop
ILLEGAL 2)
L
H
L
H
BA, CA, A10
READ
ILLEGAL 2)
L
H
L
L
BA, CA, A10
WRITE
WRITE
L
L
H
H
BA, RA
Active
ILLEGAL 2)
L
L
H
L
BA, A10
PRE/PREA
ILLEGAL 2)
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
L
H
H
L
X
Burst Stop
ILLEGAL
L
H
L
X
BA, CA, A10
READ/WRITE
ILLEGAL
L
L
H
H
BA, RA
Active
ILLEGAL
L
L
H
L
BA, A10
PRE/PREA
ILLEGAL
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
L
H
H
L
X
Burst Stop
ILLEGAL
L
H
L
X
BA, CA, A10
READ/WRITE
ILLEGAL
L
L
H
H
BA, RA
Active
ILLEGAL
L
L
H
L
BA, A10
PRE/PREA
ILLEGAL
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
PRECHARGING
(DURING tRP)
ROW
ACTIVATING
(FROM ROW
ACTIVE TO
tRCD)
WRITE
RECOVERING
(DURING tWR
OR tCDLR)
REFRESHING
MODE
REGISTER
SETTING
- 59 -
datasheet
KA100O015E-BJTT
Current State
Rev. 1.0
MCP Memory
CKE
n-1
CKE
n
CS
RAS
CAS
WE
Add
Action
L
H
H
X
X
X
X
Exit Self-Refresh
L
H
L
H
H
H
X
Exit Self-Refresh
SELF-
L
H
L
H
H
L
X
ILLEGAL
REFRESHING 8)
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP (Maintain Self-Refresh)
L
H
X
X
X
X
X
Exit Power Down (Idle after tPDEX)
L
L
X
X
X
X
X
NOP (Maintain Power Down)
H
H
X
X
X
X
X
Refer to Function Truth Table
H
L
L
L
L
H
X
Enter Self-Refresh
POWER
DOWN
H
L
H
X
X
X
X
Enter Power Down
ALL BANKS
H
L
L
H
H
H
X
Enter Power Down
IDLE 9)
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
X
X
X
ILLEGAL
L
X
X
X
X
X
X
Refer to Current State = Power Down
(H=High Level, L=Low level, X=Don′t Care)
NOTE :
1) All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2) ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank.
(ILLEGAL = Device operation and/or data integrity are not guaranteed.)
3) Must satisfy bus contention, bus turn around and write recovery requirements.
4) NOP to bank precharging or in idle sate. May precharge bank indicated by BA.
5) ILLEGAL if any bank is not idle.
6) Refer to "Read with Auto Precharge Timing Diagram" for detailed information.
7) Refer to "Write with Auto Precharge Timing Diagram" for detailed information.
8) CKE Low to High transition will re-enable CK, CK and other inputs asynchronously.
A minimum setup time must be satisfied before issuing any command other than EXIT.
9) Power-Down, Self-Refresh can be entered only from All Bank Idle state.
- 60 -
KA100O015E-BJTT
datasheet
Rev. 1.0
MCP Memory
Mobile DDR SDRAM Device Operation & Timing Diagram
- 61 -
KA100O015E-BJTT
datasheet
Device Operations
- 62 -
Rev. 1.0
MCP Memory
datasheet
KA100O015E-BJTT
Rev. 1.0
MCP Memory
1. PRECHARGE
The precharge command is used to precharge or close a bank that has been activated. The precharge command is issued when CS, RAS and WE are
low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge each bank respectively or all banks simultaneously. The bank select addresses(BA0, BA1) are used to define which bank is precharged when the command is initiated. For write cycle, tWR(min.) must
be satisfied until the precharge command can be issued. After tRP from the precharge, an active command to the same bank can be initiated.
[Table 1] Bank selection for precharge by Bank address bits
A10/AP
BA1
BA0
Precharge
0
0
0
Bank A Only
0
0
1
Bank B Only
0
1
0
Bank C Only
0
1
1
Bank D Only
1
X
X
All Banks
2. NO OPERATION(NOP) & DEVICE DESELECT
The device should be deselected by deactivating the CS signal. In this mode, Mobile DDR SDRAM should ignore all the control inputs. The Mobile DDR
SDRAM is put in NOP mode when CS is activated and RAS, CAS and WE are deactivated. Both Device Deselect and NOP command can not affect operation already in progress. So even if the device is deselected or NOP command is issued under operation, the operation will be completed.
- 63 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
3. ROW ACTIVE
The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock (CK). The Mobile DDR SDRAM
has four independent banks, so two Bank Select addresses(BA0, BA1) are required. The Bank Activation command must be applied before any Read or
Write operation is executed. The delay from the Bank Activation command to the first read or write command must meet or exceed the minimum of RAS
to CAS delay time, tRCD(min). Once a bank has been activated, it must be precharged before another Bank Activation command can be applied to the
same bank. The minimum time interval between interleaved Bank Activation commands (Bank A to Bank B and vice versa) is the Bank to Bank delay
time, tRRD(min).
Any system or application incorporating random access memory products should be properly designed, tested and qualifided to ensure proper use or
access of such memory products. Disproportionate, excessive and/or repeated access to a particular address or addresses may result in reduction of
product life.
0
1
2
3
4
5
Tn
Tn+1
Tn+2
CK
CK
Address
Bank A
Row Addr.
Bank A
Col. Addr.
Bank B
Row Addr.
RAS-CAS delay(tRCD)
Command
Bank A
Activate
NOP
NOP
Write A
with Auto
Precharge
Bank A
Row. Addr.
RAS-RAS delay time(tRRD)
NOP
NOP
Bank B
Activate
ROW Cycle Time(tRC)
NOP
Bank A
Activate
: Don′t care
Figure 1. Bank Activation Command Cycle timing <tRCD=3CLK, tRRD=2CLK>
4. READ BANK
This command is used after the row activate command to initiate the burst read of data. The read command is initiated by activating RAS, CS, CAS, and
WE at the same clock sampling (rising) edge as described in the command truth table. The length of the burst and the CAS latency time will be determined by the values programmed during the MRS cycle.
5. WRITE BANK
This command is used after the row activate command to initiate the burst write of data. The write command is initiated by activating RAS, CS, CAS, and
WE at the same clock sampling(rising) edge as described in the command truth table. The length of the burst will be determined by the values programmed during the MRS cycle.
- 64 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
6. BURST READ OPERATION
Burst Read operation in Mobile DDR SDRAM is in the same manner as the Mobile SDR SDRAM such that the Burst read command is issued by asserting
CS and CAS low while holding RAS and WE high at the rising edge of the clock(CK) after tRCD from the bank activation. The address inputs determine
the starting address for the Burst. The Mode Register sets type of burst (Sequential or interleave) and burst length(2, 4, 8, 16). The first output data is
available with a CAS Latency from the READ command, and the consecutive data are presented on the falling and rising edge of Data Strobe (DQS)
adopted by Mobile DDR SDRAM until the burst length is completed.
0
1
2
3
4
5
6
7
8
CK
CK
Command
READ A
NOP
NOP
NOP
NOP
NOP
tDQSCK
DQS
Hi-Z
tRPST
tRPRE
Postamble
Preamble
tAC
DQs
Hi-Z
Dout 0 Dout 1 Dout 2 Dout 3
Figure 2. Burst read operation timing
NOTE :
1) Burst Length=4, CAS Latency= 3.
- 65 -
NOP
NOP
NOP
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
7. BURST WRITE OPERATION
The Burst Write command is issued by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock (CK). The address inputs
determine the starting column address. There is no write latency relative to DQS required for burst write cycle. The first data of a burst write cycle must be
applied on the DQ pins tDS (Data-in setup time) prior to data strobe edge enabled after tDQSS from the rising edge of the clock (CK) that the write command is issued. The remaining data inputs must be supplied on each subsequent falling and rising edge of Data Strobe until the burst length is completed.
When the burst has been finished, any additional data supplied to the DQ pins will be ignored.
0
1
2
3
4
5
6
7
8
CK
CK
Command
NOP
WRITEA
WRITEB
NOP
NOP
NOP
NOP
tWR
tDQSS(max)
tDQSS(max)
DQS
NOP
Hi-Z
tWPREH
tWPRES
DQs
Hi-Z
Din 0 Din 1 Din 2 Din 3 Din 0 Din 1 Din 2 Din 3
tWR
tDQSS(min)
tDQSS(min)
DQS
Hi-Z
DQs
Hi-Z
tWPRES tWPREH
Din 0 Din 1 Din 2 Din 3 Din 0 Din 1 Din 2 Din 3
tDS tDH
Figure 3. Burst write operation timing
NOTE :
1) Burst Length=4.
2) The specific requirement is that DQS be valid (High or Low) on or before this CK edge.
The case shown (DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus.
- 66 -
NOP
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
8. READ INTERRUPTED BY A READ
A Burst Read can be interrupted by new Read command of any bank before completion of the burst. When the previous burst is interrupted, the new
address with the full burst length override the remaining address. The data from the first Read command continues to appear on the outputs until the CAS
latency from the interrupting Read command is satisfied. At this point, the data from the interrupting Read command appears. Read to Read interval is
minimum 1 Clock.
0
1
2
3
4
5
6
7
8
CK
CK
Command
tCCD(min)
READ
READ
NOP
Preamble
Hi-Z
DQs
NOP
NOP
tDQSCK
tRPRE
Hi-Z
DQS
NOP
NOP
NOP
NOP
tRPST
Dout A0 Dout A1 Dout B0 Dout B1 Dout B2 Dout B3
Figure 4. Read interrupted by a read timing
NOTE :
1) Burst Length=4, CAS Latency=3
9. READ INTERRUPTED BY A WRITE & BURST STOP
To interrupt a burst read with a write command, Burst Stop command must be asserted to avoid data contention on the I/O bus by placing the DQs (Output
drivers) in a high impedance state.
0
1
2
3
4
5
6
7
8
CK
CK
Command
READ
Burst Stop
NOP
NOP
NOP
tDQSCK
DQS
Hi-Z
DQs
Hi-Z
NOP
NOP
NOP
tDQSS
tWPREH
tRPRE
tAC
WRITE
tRPST
tWPST
tWPRES
Dout 0 Dout 1
Din 0
Din 1
Din 2
Din 3
tWPRE
Figure 5. Read interrupted by a write and burst stop timing
NOTE :
1) Burst Length=4, CAS Latency=3 .
The following functionality establishes how a Write command may interrupt a burst Read.
1. For Write commands interrupting a burst Read, a Burst Terminate command is required to stop the burst read and tri-state the DQ bus prior to valid
input write data. Burst stop command must be applied at least 2 clock cycles for CL=2 and at least 3 clock cycles for CL=3 before the Write command.
2. It is illegal for a Write command to interrupt a Read with autoprecharge command.
- 67 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
10. READ INTERRUPTED BY A PRECHARGE
A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to precharge intervals. The
latency from a precharge command to invalid output is equivalent to the CAS latency.
CK
0
1
2
3
4
5
6
7
NOP
NOP
NOP
NOP
NOP
NOP
8
CK
1tCK
Command
Precharge
READ
DQS
Hi-Z
DQs
Hi-Z
NOP
tDQSCK
tRPRE
tAC
Dout 0 Dout 1 Dout 2 Dout 3 Dout 4 Dout 5 Dout 6 Dout 7
Interrupted by precharge
Figure 6. Read interrupted by a precharge timing
NOTE :
1) Burst Length=8, CAS Latency=3 .
When a burst Read command is issued to a Mobile DDR SDRAM, a Precharge command may be issued to the same bank before the Read burst is
completed. The following functionality determines when a Precharge command may be given during a Read burst and when a new Bank Activate
command may be issued to the same bank.
1. For the earliest possible Precharge command without interrupting a burst Read, the Precharge command may be given on the rising clock edge which
is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank Activate command may be issued to the same bank after
tRP (Row Precharge time).
2. When a Precharge command interrupts a burst Read operation, the Precharge command given on a rising clock edge terminates the burst with the last
valid data word presented on DQ pins at CL-1(CL=CAS Latency) clock cycles after the command has been issued. Once the last data word has been
output, the output buffers are tri-stated. A new Bank Activate command may be issued to the same bank after tRP.
3. For a Read with Autoprecharge command, a new Bank Activate command may be issued to the same bank after tRP from rising clock that comes
CL(CL=CAS Latency) clock cycles before the end of the Read burst. During Read with autoprecharge, the initiation of the internal precharge occurs at the
same time as the earliest possible external Precharge command would initiate a precharge operation without interrupting the Read burst as described in
1 above.
4. For all cases above, tRP is an analog delay that needs to be converted into clock cycles. The number of clock cycles between a Precharge command
and a new Bank Activate command to the same bank equals tRP/tCK (where tCK is the clock cycle time) with the result rounded up to the nearest integer
number of clock cycles. (Note that rounding to X.5 is not possible since the Precharge and Bank Activate commands can only be given on a rising clock
edge).In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This
includes Read with autoprecharge commands where tRAS(min) must still be satisfied such that a Read with autoprecharge command has the same
timing as a Read command followed by the earliest possible Precharge command which does not interrupt the burst.
- 68 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
11. WRITE INTERRUPTED BY A WRITE
A Burst Write can be interrupted by a new Write command before completion of the burst, where the interval between the successive Write commands
must be at least one clock cycle(tCCD(min)). When the previous burst is interrupted, the remaining addresses are overridden by the new address and
data will be written into the device until the programmed burst length is satisfied.
CK
0
1
2
3
4
5
6
7
NOP
NOP
NOP
NOP
NOP
8
CK
tCCD(min)
Command
NOP
WRITE A
DQS
Hi-Z
DQs
Hi-Z
WRITE b
Din A0
Din A1
Din B0
Din B1
Din B2
Din B3
Figure 7. Write interrupted by a write timing
NOTE :
1) Burst Length=4.
- 69 -
NOP
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
12. WRITE INTERRUPTED BY A PRECHARGE & DM
A burst write operation can be interrupted by a precharge of the same bank before completion of the burst. Random column access is allowed. A write
recovery time(tWR) is required from the last data to precharge command. When precharge command is asserted, any residual data from the burst write
cycle must be masked by DM.
0
1
2
3
4
5
6
7
8
CK
CK
Command
NOP
WRITE A
DQs
NOP
NOP
NOP
Hi-Z
Hi-Z
PrechargeA
tWR
tDQSS(max)
tDQSS(max)
DQS
NOP
NOP
tDQSS(max)
tWPREH
tWPRES
WRITE B
tWPREH
Dina0
Dina1
Dina2
Dina3
Dina4
Dina5
Dina6
Dina7
tWPRES
Dinb0
Dinb1
Dinb1
Dinb2
DM
tDQSS(min)
Hi-Z
DQs
Hi-Z
tDQSS(min)
tWR
tDQSS(min)
DQS
tWPRES tWPREH
tWPRES tWPREH
Dina0
Dina1
Dina2
Dina3
Dina4
Dina5
Dina6
Dina7
Dinb0
DM
Figure 8. Write interrupted by a precharge and DM timing
NOTE :
1) Burst Length=8.
Precharge timing for Write operations in Mobile DDR SDRAM requires enough time to allow ’write recovery’ which is the time required by a Mobile DDR
SDRAM core to properly store a full ’0’ or ’1’ level before a Precharge operation. For Mobile DDR SDRAM, a timing parameter, tWR, is used to indicate
the required amount of time between the last valid write operation and a Precharge command to the same bank.
The precharge timing for writes is a complex definition since the write data is sampled by the data strobe and the address is sampled by the input clock.
Inside the Mobile DDR SDRAM, the data path is eventually synchronized with the address path by switching clock domains from the data strobe clock
domain to the input clock domain. This makes the definition of when a precharge operation can be initiated after a write very complex since the write
recovery parameter must make reference to only the clock domain that affects internal write operation, i.e., the input clock domain.
tWR starts on the rising clock edge after the last possible DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes in the
precharge command.
1. For the earliest possible Precharge command following a burst Write without interrupting the burst, the minimum time for write recovery is defined by
tWR.
2. When a precharge command interrupts a Write burst operation, the data mask pin, DM, is used to mask input data during the time between the last
valid write data and the rising clock edge on which the Precharge command is given. During this time, the DQS input is still required to strobe in the
state of DM. The minimum time for write recovery is defined by tWR.
3. For a Write with autoprecharge command, a new Bank Activate command may be issued to the same bank after tWR+tRP where tWR+tRP starts on
the falling DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes in the Bank Activate command. During write
with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external Precharge command without
interrupting the Write burst as described in 1 above.
4. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This includes
Write with autoprecharge commands where tRAS(min) must still be satisfied such that a Write with autoprecharge command has the same timing as
a Write command followed by the earliest possible Precharge command which does not interrupt the burst.
- 70 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
13. WRITE INTERRUPTED BY A READ & DM
A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any residual data from the burst write cycle must
be masked by DM. The delay from the last data to read command (tCDLR) is required to avoid the data contention Mobile DDR SDRAM inside. Data that
are presented on the DQ pins before the read command is initiated will actually be written to the memory. Read command interrupting write can not be
issued at the next clock edge of that of write command.
0
1
2
3
4
NOP
NOP
NOP
5
6
7
8
NOP
NOP
NOP
9
CK
CK
Command
NOP
WRITE
tDQSS(max)
tDQSS(max)
DQS
READ
NOP
NOP
tCDLR
Hi-Z
tWPRES
DQs
Hi-Z
Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7
Dout0 Dout1 Dout2 Dout3 Dout4
DM
tDQSS(min)
tDQSS(min)
DQS
tCDLR
Hi-Z
tWPRES
DQs
Hi-Z
Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7
Dout0 Dout1 Dout2 Dout3 Dout4
DM
Figure 9. Write interrupted by a Read and DM timing
NOTE :
1) Burst Length=8, CAS Latency=3 .
The following function established how a Read command may interrupt a Write burst and which input data is not written into the memory.
1. For Read commands interrupting a burst Write, the minimum Write to Read command delay is 2 clock cycles. The case where the Write to Read delay
is 1 clock cycle is disallowed.
2. For Read commands interrupting a burst Write, the DM pin must be used to mask the input data words which immediately precede the interrupting
Read operation and the input data word which immediately follows the interrupting Read operation
3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory controller) in time to allow
the buses to turn around before the Mobile DDR SDRAM drives them during a read operation.
4. If input Write data is masked by the Read command, the DQS input is ignored by the Mobile DDR SDRAM.
5. Refer to Burst write operation.
- 71 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
14. BURST STOP
The burst stop command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock(CK). The burst stop command has
the fewest restrictions making it the easiest method to use when terminating a burst read operation before it has been completed. When the burst stop
command is issued during a burst read cycle, the pair of data and DQS(Data Strobe) go to a high impedance state after a delay which is equal to the CAS
latency set in the mode register. However, the burst stop command is not supported during a burst write operation.
0
1
READ A
Burst Stop
2
3
4
5
6
7
8
CK
CK
Command
NOP
NOP
NOP
NOP
NOP
NOP
NOP
The burst read ends after a delay equal to the CAS latency.
DQS
Hi-Z
DQs
Hi-Z
Dout 0 Dout 1
Figure 10. Burst stop timing
NOTE :
1) Burst Length=4, CAS Latency= 3.
The Burst Stop command is a mandatory feature for Mobile DDR SDRAM. The following functionality is required:
1. The Burst Stop command may only be issued on the rising edge of the input clock, CK.
2. Burst Stop is only a valid command during Read bursts.
3. Burst Stop during a Write burst is undefined and shall not be used.
4. Burst Stop applies to all burst lengths.
5. Burst Stop is an undefined command during Read with autoprecharge and shall not be used.
6. When terminating a burst Read command, the BST command must be issued LBST (“BST Latency”) clock cycles before the clock
edge at which the output buffers are tristated, where LBST equals the CAS latency for read operations.
7. When the burst terminates, the DQ and DQS pins are tristated.
The Burst Stop command is not byte controllable and applies to all bits in the DQ data word and the(all) DQS pin(s).
- 72 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
15. DM MASKING
The Mobile DDR SDRAM has a data mask function that can be used in conjunction with data write cycle, not read cycle. When the data mask is activated(DM high) during write operation, Mobile DDR SDRAM does not accept the corresponding data.(DM to data-mask latency is zero). DM must be
issued at the rising or falling edge of data strobe.
0
1
2
3
4
5
6
7
8
CK
CK
Command
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSS
Hi-Z
DQS
tWPRES tWPREH
DQs
Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din7
DM
masked by DM=H
Figure 11. DM masking timing
NOTE :
1) Burst Length=8.
- 73 -
Hi-Z
NOP
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
16. READ WITH AUTO PRECHARGE
If A10/AP is high when read command is issued, the read with auto-precharge function is performed. If a read with auto-precharge command is issued,
the Mobile DDR SDRAM automatically enters the precharge operation BL/2 clock later from a read with auto-precharge command when tRAS(min) is satisfied. If not, the start point of precharge operation will be delayed until tRAS(min) is satisfied. Once the precharge operation has started, the bank cannot
be reactivated and the new command can not be asserted until the precharge time(tRP) has been satisfied.
0
1
2
3
4
5
6
7
8
9
NOP
NOP
NOP
10
11
CK
CK
Command
BANK A
ACTIVE
NOP
NOP
NOP
READ A
Auto Precharge
NOP
NOP
tRP
DQS
Hi-Z
DQs
Hi-Z
NOP
NOP
Bank can be reactivated at
completion of tRP2)
Dout0 Dout1 Dout2 Dout3
tRAS(min)
Auto-Precharge starts
Figure 12. Read with auto precharge timing
NOTE :
1) Burst Length=4, CAS Latency= 3.
2) The row active command of the precharge bank can be issued after tRP from this point.
Asserted
command
READ
For same Bank
5
READ +No
AP1)
For Different Bank
6
7
5
6
7
READ+No AP
Illegal
Legal
Legal
Legal
READ+AP
READ + AP
READ + AP
Illegal
Legal
Legal
Legal
Active
Illegal
Illegal
Illegal
Legal
Legal
Legal
Precharge
Legal
Legal
Illegal
Legal
Legal
Legal
NOTE :
1) AP = Auto Precharge.
- 74 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
17. WRITE WITH AUTO PRECHARGE
If A10/AP is high when write command is issued, the write with auto-precharge function is performed. Any new command to the same bank should not be
issued until the internal precharge is completed. The internal precharge begins after keeping tWR(min).
0
1
2
3
NOP
NOP
NOP
4
5
6
7
8
9
NOP
NOP
NOP
NOP
NOP
10
11
12
13
CK
CK
Command
DQS
DQs
BANK A
ACTIVE
WRITE A
Auto Precharge
NOP
NOP
NOP
NOP
Hi-Z
Hi-Z
Bank can be reactivated at
completion of tRP2)
Din 0 Din 1 Din 2 Din 3
tWR
tRP
Internal precharge start
Figure 13. Write with auto precharge timing
NOTE :
1) Burst Length=4.
2) The row active command of the precharge bank can be issued after tRP from this point.
Asserted
command
For same Bank
For Different Bank
5
6
7
8
9
10
5
6
7
8
9
WRITE+
No AP1)
WRITE+
No AP
Illegal
Illegal
Illegal
Illegal
Legal
Legal
Legal
Legal
Legal
WRITE+
AP
WRITE+
AP
WRITE+
AP
Illegal
Illegal
Illegal
Illegal
Legal
Legal
Legal
Legal
Legal
READ
Illegal
NO AP+DM2)
READ+
NO AP+DM
READ+
NO AP
Illegal
Illegal
Illegal
Illegal
Illegal
Legal
Legal
READ+AP
Illegal
READ +
AP+DM
READ +
AP+DM
READ +
AP
Illegal
Illegal
Illegal
Illegal
Illegal
Legal
Legal
Active
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
Legal
Legal
Legal
Legal
Legal
Precharge
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
Legal
Legal
Legal
Legal
Legal
WRITE
READ+
NOTE :
1) AP = Auto Precharge.
2) DM : Refer to "27. Write Interrupted by Precharge & DM ".
- 75 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
18. AUTO REFRESH & SELF REFRESH
18.1. Auto Refresh
CK
CK
CKE
PRE
= High
NOP
NOP
Auto
Refresh
NOP
NOP
∼
Command
∼
∼ ∼
An auto refresh command is issued by having CS, RAS and CAS held low with CKE and WE high at the rising edge of the clock(CK). All banks must be
precharged and idle for tRP(min) before the auto refresh command is applied. Once this cycle has been started, no control of the external address pins
are required because of the internal address counter. When the refresh cycle has completed, all banks will be in the idle state. A delay between the auto
refresh command and the next activate command or subsequent auto refresh command must be greater than or equal to the tRFC(min).
tRP
NOP
ACT
NOP
NOP
tRFC(min)
DQ
High-Z
DQS
High-Z
Figure 14. Auto refresh timing
NOTE :
1) tRP=3CLK
2) Device must be in the all banks idle state prior to entering Auto refresh mode.
18.2. Self Refresh
Command NOP
Self
Refresh
∼ ∼
CK
Stable Clock
NOP
NOP
∼
CK
∼ ∼ ∼ ∼
A Self Refresh command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. Once the self Refresh command is initiated, CKE must be held low to keep the device in Self Refresh mode. After 1 clock cycle from the self refresh command, all of the external
control signals including system clock(CK, CK) can be disabled except CKE. The clock is internally disabled during Self Refresh operation to reduce
power. Before returning CKE high to exit the Self Refresh mode, apply stable clock input signal with Deselect or NOP command asserted.
NOP
tXSR(min)
∼
tRFC
∼
CKE
NOP
tIS
tIS
DQ
High-Z
DQS
High-Z
Figure 15. Self refresh timing
NOTE :
1) Device must be in the all banks idle state prior to entering Self Refresh mode.
2) The minimum time that the device must remain in Self Refresh mode is tRFC.
- 76 -
Active
NOP
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
19. POWER DOWN
Command Precharge NOP
NOP
Precharge
power
down
Entry
∼ ∼
CK
Precharge
power
Active
down
Exit
∼ ∼∼
CK
Active
power
down
Entry
∼ ∼∼
∼ ∼
The device enters power down mode when CKE Low, and it exits when CKE High. Once the power down mode is initiated, all of the receiver circuits
except CK and CKE are gated off to reduce power consumption. All banks should be in idle state prior to entering the precharge power down mode and
CKE should be set in high for at least tPDEX prior to Row active command. Refresh operations cannot be performed during power down mode, therefore
the device cannot remain in power down mode longer than the refresh period(tREF) of the device.
Active
power
down
Exit
(NOP)
tCKE
∼
∼
CKE
tCKE
tPDEX
tIS
tIS
DQ
tIS
High-Z
DQS
High-Z
Figure 16. Power down entry and exit timing
NOTE :
1) Device must be in the all banks idle state prior to entering Power Down mode.
2) The minimum power down duration is specified by tCKE.
- 77 -
tIS
Read
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
20. CLOCK STOP
Stopping a clock during idle periods is an effective method of reducing power consumption.
The LPDDR SDRAM supports clock stop under the following conditions :
- the last command (ACTIVE, READ, WRITE, PRECHARGE, AUTO REFRESH or MODE REGISTER SET) has executed to completion, including any
data-out during read bursts; the number of clock pulses per access command depends on the device’s AC timing parameters and the clock frequency;
- the related timing conditions (tRCD, tWR, tRP, tRFC, tMRD) has been met;
- CKE is held High
When all conditions have been met, the device is either in "idle state"or "row active state" and clock stop mode may be entered with CK held Low and CK
held Hight.
Clock stop mode is exited by restarting the clock. At least one NOP command has to be issued before the next access command any be applied. Additional clock pulses might be required depending on the system characteristics.
Figure shows clock stop mode entry and exit.
- Initially the device is in clock stop mode
- The clock is restarted with the rising edge of T0 and a NOP on the command inputs
- With T1 a valid access command is latched; this command is followed by NOP commands in order to allow for clock stop as soon as this access command is completed.
- Tn is the last clock pulse required by the access command latched with T1
- The clock can be stopped after Tn.
T1
T2
~
~
CKE
~
CK
CK
Tn
~ ~
T0
CMD
NOP
Valid
NOP
NOP
∼
Address
NOP
~ ~ ~ ~
Command
~ ~ ~ ~
~ ~ ~ ~
Timing Condition
High-Z
DQ, DQS
Clock
Stopped
Exit
Valid
Clock Command
Stop
Mode
= Don’t Care
Enter
clock
Stop
Mode
Figure 17. Clock Stop Mode Entry and Exit
- 78 -
KA100O015E-BJTT
datasheet
Timing Diagram
- 79 -
Rev. 1.0
MCP Memory
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
1. POWER UP SEQUENCE FOR MOBILE DDR SDRAM
≈ ≈
≈ ≈
CK
CK
HiGH
≈
≈
CKE
≈
≈
RAS
≈ ≈
≈ ≈
CAS
≈ ≈
≈ ≈
WE
≈ ≈
≈ ≈
ADDR
≈ ≈
≈ ≈
BA0
≈ ≈
≈ ≈
BA1
≈ ≈
≈ ≈
A10/AP
≈ ≈
≈ ≈
CS
Hi-Z
tRP
Precharge
(All Bank)
tRFC
Auto
Refresh
RAa
Key
Key
RAa
≈
≈
DM
Key
Hi-Z
≈
≈
Hi-Z
DQs
Key
tRFC
Auto
Refresh
Normal
MRS
Row Active
(A-Bank)
Extended
MRS
: Don’t care
Figure 18. Power Up Sequence for Mobile DDR SDRAM
NOTE :
1) Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined.
- Apply VDD before or at the same time as VDDQ.
2) Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3) Issue precharge commands for all banks of the devices.
4) Issue 2 or more auto-refresh commands.
5) Issue a mode register set command to initialize the mode register.
6) Issue a extended mode register set command for the desired operating modes after normal MRS.
The Mode Register and Extended Mode Register do not have default values.
If they are not programmed during the initialization sequence, it may lead to unspecified operation.
All banks have to be in idle state prior to adjusting MRS and EMRS set.
- 80 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
2. BASIC TIMING
0
1
2
3
4
5
tCH tCL
tCH tCL
tCK
tCK
6
7
8
9
10
11
12
13
14
15
CK
CK
HIGH
CKE
CS
tIS
tIH
RAS
CAS
WE
BA0, BA1
BAa
A10/AP
Ra
ADDR
(A0~An)
Ra
BAa
BAb
Ca
Cb
tDQSS
Hi-Z
DQS
tDQSL
Hi-Z
tWPRES
tDQSCK
Hi-Z
DQs
tDSC
tRPST
tRPRE
Qa0
tAC
Qa1
Qa2
Qa3
Hi-Z
tWPST
Db0 Db1 Db2 Db3
tQHS
Hi-Z
tDQSH
tWPREH
Hi-Z
tDS tDH
DM
COMMAND
ACTIVE
READ
WRITE
: Don’t care
Figure 19. Basic Timing (Setup, Hold and Access Time @BL=4, CL=3)
- 81 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
3. MULTI BANK INTERLEAVING READ
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CK
CK
HIGH
CKE
CS
RAS
CAS
WE
BA0,BA1
BAa
BAb
A10/AP
Ra
Rb
ADDR
(A0~An)
Ra
Rb
BAa
BAb
Ca
Cb
tRRD
tCCD
DQS
Hi-Z
DQs
Hi-Z
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
DM
tRCD
COMMAND
ACTIVE
ACTIVE
READ
READ
: Don’t care
Figure 20. Multi Bank Interleaving READ (@BL=4, CL=3)
- 82 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
4. MULTI BANK INTERLEAVING WRITE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CK
CK
HIGH
CKE
CS
RAS
CAS
WE
BA0,BA1
BAa
BAb
A10/AP
Ra
Rb
ADDR
(A0~An)
Ra
Rb
BAa
BAb
Ca
Cb
tRRD
tCCD
DQS
Hi-Z
DQs
Hi-Z
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
DM
tRCD
COMMAND
ACTIVE
ACTIVE
WRITE
WRITE
: Don’t care
Figure 21. Multi Bank Interleaving WRITE (@BL=4)
- 83 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
5. READ WITH AUTO PRECHARGE
0
1
2
3
4
5
6
7
8
9
10
CK
CK
HIGH
CKE
CS
RAS
CAS
WE
BA0,BA1
BAa
BAa
Ra
A10/AP
ADDR
(A0~An)
Ca
Ra
Auto precharge start
tRP
NOTE1)
DQS
(CL=3)
Hi-Z
DQs
(CL=3)
Hi-Z
Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7
DM
COMMAND
READ
ACTIVE
: Don’t care
Figure 22. Read with Auto Precharge (@BL=8)
NOTE :
1) The row active command of the precharge bank can be issued after tRP from this point.
- 84 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
6. WRITE WITH AUTO PRECHARGE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CK
CK
HIGH
CKE
CS
RAS
CAS
WE
BA0,BA1
BAa
BAa
A10/AP
ADDR
(A0~An)
Ra
Ca
Ra
tWR
Auto precharge start
tRP
NOTE1)
Hi-Z
DQS
DQs
Hi-Z
Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7
DM
COMMAND
WRITE
ACTIVE
: Don’t care
Figure 23. Write with Auto Precharge (@BL=8)
NOTE :
1) The row active command of the precharge bank can be issued after tRP from this point
- 85 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
7. WRITE FOLLOWED BY PRECHARGE
0
1
2
3
4
5
6
7
8
9
10
CK
CK
HIGH
CKE
CS
RAS
CAS
WE
BA0,BA1
BAa
BAa
A10/AP
ADDR
(A0~An)
Ca
tWR
DQS
Hi-Z
DQs
Hi-Z
Da0 Da1 Da2 Da3
DM
COMMAND
PRE
CHARGE
WRITE
: Don’t care
Figure 24. Write followed by Precharge (@BL=4)
- 86 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
8. WRITE INTERRUPTED BY PRECHARGE & DM
0
1
2
3
4
5
6
7
8
9
10
11
12
13
CK
CK
HIGH
CKE
CS
RAS
CAS
WE
BA0,BA1
BAa
BAa
BAb
BAc
Cb
Cc
A10/AP
ADDR
(A0~An)
Ca
DQS
Hi-Z
DQs
Hi-Z
Db0 Db1 Dc0 Dc1 Dc2 Dc3 Dc4 Dc5 Dc6 Dc7
Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7
DM
tWR
COMMAND
WRITE
tCCD
PRE
CHARGE
WRITE
WRITE
: Don’t care
Figure 25. Write Interrupted by Precharge & DM (@BL=8)
- 87 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
9. WRITE INTERRUPTED BY A READ
0
1
2
3
4
5
6
7
8
9
10
11
CK
CK
HIGH
CKE
CS
RAS
CAS
WE
BA0,BA1
BAa
BAb
Ca
Cb
A10/AP
ADDR
(A0~An)
DQS
Hi-Z
DQs
Hi-Z
Da0 Da1 Da2 Da3 Da4 Da5
Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb6 Qb7
Masked by DM
DM
tCDLR
COMMAND
WRITE
READ
: Don’t care
Figure 26. Write Interrupted by a Read (@BL=8, CL=3)
- 88 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
10. READ INTERRUPTED BY PRECHARGE
0
1
2
3
4
5
6
7
8
9
10
CK
CK
HIGH
CKE
CS
RAS
CAS
WE
BA0,BA1
BAa
BAa
A10/AP
ADDR
(A0~An)
DQS
Ca
Hi-Z
2 tCK Valid
DQs
Hi-Z
Qa0 Qa1 Qa2 Qa3 Qa4 Qa5
DM
COMMAND
READ
PRE
CHARGE
: Don’t care
Figure 27. Read Interrupted by Precharge (@BL=8, CL=3)
- 89 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
11. READ INTERRUPTED BY A WRITE & BURST STOP
0
1
2
3
4
5
6
7
8
9
10
11
CK
CK
HIGH
CKE
CS
RAS
CAS
WE
BA0,BA1
BAa
BAb
Ca
Cb
A10/AP
ADDR
(A0~An)
DQS
Hi-Z
DQs
Hi-Z
Qa0 Qa1
Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb6 Qb7
DM
COMMAND
READ
Burst
Stop
WRITE
: Don’t care
Figure 28. Read Interrupted by a Write & Burst Stop (@BL=8, CL=3)
- 90 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
12. READ INTERRUPTED BY A READ
0
1
2
3
4
5
6
7
8
9
10
CK
CK
HIGH
CKE
CS
RAS
CAS
WE
BA0,BA1
BAa
BAb
Ca
Cb
A10/AP
ADDR
(A0~An)
DQS
Hi-Z
DQs
Hi-Z
Qa0 Qa1 Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb6 Qb7
DM
COMMAND
READ
READ
: Don’t care
Figure 29. Read Interrupted by a Read (@BL=8, CL=3)
- 91 -
Rev. 1.0
datasheet
KA100O015E-BJTT
MCP Memory
13. DM FUNCTION
0
1
2
3
4
5
6
7
8
9
10
CK
CK
HIGH
CKE
CS
RAS
CAS
WE
BA0,BA1
BAa
A10/AP
ADDR
(A0~An)
Ca
Hi-Z
DQS
DQs
Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7
Hi-Z
DM
COMMAND
WRITE
: Don’t care
Figure 30. DM Function (@BL=8) only for write
- 92 -