Ordering number : ENA0477
LC87F1G64A
CMOS IC
FROM 64K byte, RAM 3K byte on-chip
8-bit 1-chip Microcontroller
with Full-Speed USB
Overview
The SANYO LC87F1G64A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time
of 83.3ns, integrates on a single chip a number of hardware features such as 64K-byte flash ROM (onboard
programmable), 3072-byte RAM, an on-chip debugger, a sophisticated 16-bit timers/counters (may be divided into 8-bit
timers), 16-bit timers/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a
prescaler, a base timer serving as a time-of-day clock, two synchronous SIO interface (with automatic block transmit/
receive function), an asynchronous/synchronous SIO interface, a UART interface (full duplex), a Full-Speed USB
interface (function controller), an 8-bit 12-channel AD converter, two 12-bit PWM channels, a system clock frequency
divider, ROM correction function, and a 32-source 10-vector address interrupt feature.
Features
Flash ROM
• Capable of on-board-programming with wide range, 3.0 to 5.5V, of voltage source.
• Block-erasable in 128 byte units
• 65536 × 8 bits
RAM
• 3072 × 9 bits
Minimum Bus Cycle
• 83.3ns (CF=12MHz)
Note: The bus cycle time here refers to the ROM read speed.
Minimum Instruction Cycle Time
• 250ns (CF=12MHz)
* This production is produced and sold by SANYO under license of the Silicon Storage Technology Inc.
Specifications and information herein are subject to change without notice.
Any and all SANYO Semiconductor products described or contained herein do not have specifications
that can handle applications that require extremely high levels of reliability, such as life-support systems,
aircraft's control systems, or other applications whose failure can be reasonably expected to result in
serious physical and/or material damage. Consult with your SANYO Semiconductor representative
nearest you before using any SANYO Semiconductor products described or contained herein in such
applications.
SANYO Semiconductor assumes no responsibility for equipment failures that result from using products
at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor
products described or contained herein.
Ver.1.07
D0606HKIM 20061109-S00012 No.A0477-1/29
LC87F1G64A
Ports
• I/O ports
Ports whose I/O direction can be designated in 1 bit units 28 (P10 to P17, P20 to P27, P30 to P34,
P70 to P73, PWM0, PWM1, XT2)
Ports whose I/O direction can be designated in 4 bit units 8 (P00 to P07)
• USB ports
2 (D+, D-)
• Dedicated oscillator ports
2 (CF1, CF2)
• Input-only port (also used for oscillation)
1 (XT1)
• Reset pins
1 (RES)
• Power pins
6 (VSS1 to 3, VDD1 to 3)
Timers
• Timer 0: 16-bit timer/counter with two capture registers.
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers)
× 2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers)
+ 8-bit counter (with two 8-bit capture registers)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers)
Mode 3: 16-bit counter (with two 16-bit capture registers)
• Timer 1: 16-bit timer/counter that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs)
+ 8-bit timer/counter with an 8-bit prescaler (with toggle outputs)
Mode 1: 8-bit PWM with an-8bit prescaler × 2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from the lower-order 8 bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs)
(The lower-order 8 bits can be used as PWM.)
• Timer 4: 8-bit timer with a 6-bit prescaler
• Timer 5: 8-bit timer with a 6-bit prescaler
• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output)
• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output)
• Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts programmable in 5 different time schemes
SIO
• SIO0: Synchronous serial interface
1) LSB first/MSB first mode selectable
2) Transfer clock cycle: 4/3 to 512/3 tCYC
3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of
data transmission possible in 1 byte units)
• SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
• SIO4: Synchronous serial interface
1) LSB first/MSB first mode selectable
2) Transfer clock cycle: 4/3 to 1020/3 tCYC
3) Automatic continuous data transmission (1 to 3072 bytes, specifiable in 1 byte units, suspension and resumption
of data transmission possible in 1 byte or 2 bytes units)
4) Auto-start-on-falling-edge function
5) Clock polarity selectable
6) CRC16 calculator circuit built in
No.A0477-2/29
LC87F1G64A
Full Duplex UART
1) Data length: 7/8/9 bits selectable
2) Stop bits: 1 bit (2 bits in continuous transmission mode)
3) Baud rate: 16/3 to 8192/3 tCYC
AD Converter: 8 bits × 12 channels
PWM: Multifrequency 12-bit PWM × 2 channels
USB Interface (function controller)
• Compliant with USB 2.0 Full-Speed
• Supports a maximum of 8 user-defined endpoints.
EP0
EP1
EP2
EP3
EP4
EP5
EP6
EP7
Control
{
-
-
-
-
-
-
-
-
Bulk
-
{
{
{
{
{
{
{
{
Endpoint
Transfer
Type
EP8
Interrupt
-
{
{
{
{
{
{
{
{
Isochronous
-
{
{
{
{
{
{
{
{
64
64
64
64
64
1023
1023
64
64
Max. payload
Audio Interface
1) Sampling frequency (fs): 32kHz, 44.1kHz, 48kHz
2) PLL clock frequency: 12.288MHz, 16.9344MHz, 18.432MHz
3) Supported master clocks
Bit Clock
Master Clock
384fs
48fs
192fs
96fs
384fs
64fs
256fs
128fs
4) Data lengths of 16, 18, 20, 24 bits selectable
5) LSB first/MSB first mode selectable
6) Left Justified/Right Justified selectable
Watchdog Timer
• External RC watchdog timer
• Interrupt and reset signals selectable
Clock Output Function
1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock.
2) Able to output oscillation clock of sub clock.
No.A0477-3/29
LC87F1G64A
Interrupts
• 32 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
Vector Address
Level
Interrupt Source
1
00003H
X or L
INT0
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4/USB bus active
4
0001BH
H or L
INT3/INT5/base timer
5
00023H
H or L
T0H/INT6
6
0002BH
H or L
T1L/T1H/INT7
7
00033H
H or L
SIO0/USB bus reset/USB suspend/UART1 receive
8
0003BH
H or L
SIO1/USB endpoint/USB-SOF/SIO4/UART1 transmit/AIF
9
00043H
H or L
ADC/T6/T7
10
0004BH
H or L
Port 0/PWM0/PWM1/T4/T5
• Priority Level: X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine Stack Levels: 1536 levels (the stack is allocated in RAM.)
High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
(5 tCYC execution time)
• 24 bits × 16 bits
(12 tCYC execution time)
• 16 bits ÷ 8 bits
(8 tCYC execution time)
• 24 bits ÷ 16 bits
(12 tCYC execution time)
Oscillation Circuits
• RC oscillation circuit (internal):
• CF oscillation circuit:
• Crystal oscillation circuit:
• PLL circuit (internal):
For system clock
For system clock
For system clock, time-of-day clock
For USB interface (see Fig.5), audio interface (see Fig.6)
Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) Canceled by a system reset or occurrence of an interrupt.
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The PLL base clock generator , CF, RC and crystal oscillators automatically stop operation.
2) There are four ways of resetting the HOLD mode.
(1) Setting the reset pin to the lower level.
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an bus active interrupt source established in the USB interface circuit
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
1) The PLL base clock generator, CF and RC oscillator automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are five ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established in the base timer circuit
(5) Having an bus active interrupt source established in the USB interface circuit
No.A0477-4/29
LC87F1G64A
ROM Correction Function
• Executes the correction program on detection of a match with the program counter value.
• Correction program area size: 128 bytes
Package Form
• TQFP48J(7×7):
• QIP48E(14×14):
• TQFP64J(10×10):
Lead-free type
Lead-free type
Lead-free type
Development Tools
• On-chip debugger: TCB87 type-A or TCB87 type-B + LC87F1G64A
Flash ROM Programming Boards
Package
Programming boards
QIP48E(14×14)
W87F55256Q
TQFP48J(7×7)
W87F55256SQ
TQFP64J(10×10)
W87F15256TQ
Recommended EPROM programmer
Maker
Model
Supported version
Flash Support Group, Inc.
AF9708/AF9709/AF9709B
(Single)
(including product of Ando Electric Co.,Ltd)
SANYO
SKK (SANYO FWS)
Device
After 02.61
LC87F1G64A FAST
Application Version: After 1.03
LC87F1G64
Chip Data Version: After 2.01
Package Dimensions
Package Dimensions
unit : mm (typ)
3288
unit : mm (typ)
3156A
9.0
17.2
48
13
1
12
0.5
37
24
48
13
14.0
24
7.0
37
25
36
17.2
0.5
25
9.0
36
0.8
14.0
7.0
0.125
0.2
1
12
1.0
(0.75)
0.35
0.15
0.1
0.1
1.2max
3.0max
(1.0)
(2.7)
(1.5)
SANYO : TQFP48J(7X7)
SANYO : QIP48E(14X14)
No.A0477-5/29
LC87F1G64A
Package Dimensions
unit : mm (typ)
3310
12.0
0.5
10.0
33
32
64
17
10.0
49
1
12.0
48
16
0.5
0.18
0.125
(1.0)
0.1
1.2 MAX
(1.25)
SANYO : TQFP64J(10X10)
LC87F1G64A
24
23
22
21
20
19
18
17
16
15
14
13
P03/AN3/DBGP1
P02/AN2/DBGP0
P01/AN1
P00/AN0
VSS2
VDD2
PWM0
PWM1
P17/T1PWMH/BUZ
P16/T1PWML
P15/SCK1
P14/SI1/SB1
1
2
3
4
5
6
7
8
9
10
11
12
37
38
39
40
41
42
43
44
45
46
47
48
P73/INT3/T0IN
RES
XT1/AN10
XT2/AN11
VSS1
CF1
CF2
VDD1
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
DD+
VDD3
VSS3
P34/UFILT
P33/AFILT
P32/ACF2
P31/ACF1
P30/MCLK
P70/INT0/T0LCP/AN8/DPUP
P71/INT1/T0HCP/AN9
P72/INT2/T0IN
36
35
34
33
32
31
30
29
28
27
26
25
P27/INT5/LRCK
P26/INT5/BCLK
P25/INT5/SDAT
P24/INT5/INT7/SCK4
P23/INT4/SI4/WR
P22/INT4/SO4/RD
P21/INT4/URX1
P20/INT4/INT6/UTX1
P07/AN7/T7O
P06/AN6/T6O
P05/AN5/CKO
P04/AN4/DBGP2
Pin Assignments
Top view
SANYO: TQFP48J(7×7)
SANYO: QIP48E(14×14)
“Lead-free Type”
“Lead-free Type”
No.A0477-6/29
NC
NC
P04/AN4/DBGP2
P05/AN5/CKO
P06/AN6/T6O
P07/AN7/T7O
P20/INT4/INT6/UTX1
P21/INT4/URX1
P22/INT4/SO4/RD
P23/INT4/SI4/WR
P24/INT5/INT7/SCK4
P25/INT5/SDAT
P26/INT5/BCLK
P27/INT5/LRCK
NC
NC
LC87F1G64A
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
NC
49
32
NC
NC
50
31
NC
D-
51
30
P03/AN3/DBGP1
D+
52
29
P02/AN2/DBGP0
VDD3
53
28
P01/AN1
VSS3
54
27
P00/AN0
P34/UFILT
55
26
VSS2
P33/AFILT
56
25
VDD2
P32/ACF2
57
24
PWM0
P31/ACF1
58
23
PWM1
P30/MCLK
59
22
P17/T1PWMH/BUZ
P70/INT0/T0LCP/AN8/DPUP
60
21
P16/T1PWML
P71/INT1/T0HCP/AN9
61
20
P15/SCK1
P72/INT2/T0IN
62
19
P14/SI1/SB1
NC
63
18
NC
NC
64
17
NC
8
9 10 11 12 13 14 15 16
NC
P73/INT3/T0IN
RES
XT1/AN10
XT2/AN11
VSS1
CF1
CF2
NC
7
NC
6
P13/SO1
5
P12/SCK0
4
P11/SI0/SB0
3
VDD1
2
P10/SO0
1
NC
LC87F1G64A
Top view
SANYO: TQFP64J(10×10) “Lead-free Type”
No.A0477-7/29
LC87F1G64A
TQFP48J/
NAME
QIP48E
TQFP48J/
NAME
QIP48E
1
P73/INT3/T0IN
25
P04/AN4/DBGP2
2
RES
26
P05/AN5/CKO
3
XT1/AN10
27
P06/AN6/T6O
4
XT2/AN11
28
P07/AN7/T7O
5
VSS1
29
P20/INT4/INT6/UTX1
6
CF1
30
P21/INT4/URX1
7
CF2
31
P22/INT4/SO4/RD
8
VDD1
32
P23/INT4/SI4/WR
9
P10/SO0
33
P24/INT5/INT7/SCK4
10
P11/SI0/SB0
34
P25/INT5/SDAT
11
P12/SCK0
35
P26/INT5/BCLK
12
P13/SO1
36
P27/INT5/LRCK
13
P14/SI1/SB1
37
D-
14
P15/SCK1
38
D+
15
P16/T1PWML
39
VDD3
16
P17/T1PWMH/BUZ
40
VSS3
17
PWM1
41
P34/UFILT
18
PWM0
42
P33/AFILT
19
VDD2
43
P32/ACF2
20
VSS2
44
P31/ACF1
21
P00/AN0
45
P30/MCLK
22
P01/AN1
46
P70/INT0/T0LCP/AN8/DPUP
23
P02/AN2/DBGP0
47
P71/INT1/T0HCP/AN9
24
P03/AN3/DBGP1
48
P72/INT2/T0IN
No.A0477-8/29
LC87F1G64A
TQFP64J
NAME
1
NC
2
3
TQFP64J
NAME
33
NC
NC
34
NC
P73/INT3/T0IN
35
P04/AN4/DBGP2
4
RES
36
P05/AN5/CKO
5
XT1/AN10
37
P06/AN6/T6O
6
XT2/AN11
38
P07/AN7/T7O
7
VSS1
39
P20/INT4/INT6/UTX1
8
CF1
40
P21/INT4/URX1
9
CF2
41
P22/INT4/SO4/RD
10
VDD1
42
P23/INT4/SI4/WR
11
P10/SO0
43
P24/INT5/INT7/SCK4
12
P11/SI0/SB0
44
P25/INT5/SDAT
13
P12/SCK0
45
P26/INT5/BCLK
14
P13/SO1
46
P27/INT5/LRCK
15
NC
47
NC
16
NC
48
NC
17
NC
49
NC
18
NC
50
NC
19
P14/SI1/SB1
51
D-
20
P15/SCK1
52
D+
21
P16/T1PWML
53
VDD3
22
P17/T1PWMH/BUZ
54
VSS3
23
PWM1
55
P34/UFILT
24
PWM0
56
P33/AFILT
25
VDD2
57
P32/ACF2
26
VSS2
58
P31/ACF1
27
P00/AN0
59
P30/MCLK
28
P01/AN1
60
P70/INT0/T0LCP/AN8/DPUP
29
P02/AN2/DBGP0
61
P71/INT1/T0HCP/AN9
30
P03/AN3/DBGP1
62
P72/INT2/T0IN
31
NC
63
NC
32
NC
64
NC
No.A0477-9/29
LC87F1G64A
System Block Diagram
Interrupt control
Standby control
CF
USB PLL
RC
Clock
generator
X’tal
PLA
IR
FROM
PC
SIO0
Bus interface
ACC
SIO1
Port 0
B register
SIO4
Port 1
C register
Timer 0
Port 2
ALU
Timer 1
Port 3
Timer 4
Port 7
Timer 5
INT0 to 7
Noise filter
Timer 6
UART1
Timer 7
Audio interface
Base timer
ADC
PSW
RAR
RAM
Stack pointer
Watchdog timer
PWM0
On-chip debugger
PWM1
USB interface
No.A0477-10/29
LC87F1G64A
Pin Description
Pin Name
VSS1,
VSS2,
I/O
Description
Option
-
-power supply pin
No
-
+power supply pin
No
VSS3
VDD1,
VDD2
VDD3
-
Port 0
I/O
USB reference voltage pin
Yes
• 8-bit I/O port
Yes
• I/O specifiable in 4-bit units
P00 to P07
• Pull-up resistors can be turned on and off in 4-bit units.
• HOLD reset input
• Port 0 interrupt input
• Pins functions
AD converter input port: AN0 to AN7 (P00 to P07)
On-chip debugger pins: DBGP0 to DBGP2 (P02 to P04)
P01: Audio interface SDAT input
P05: System Clock Output/Audio interface SDAT input
P06: Timer 6 toggle outputs
P07: Timer 7 toggle outputs
Port 1
I/O
Yes
• 8-bit I/O port
• I/O specifiable in 1-bit units
P10 to P17
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P10: SIO0 data output
P11: SIO0 data input/bus I/O
P12: SIO0 clock I/O
P13: SIO1 data output
P14: SIO1 data input/bus I/O
P15: SIO1 clock I/O
P16: Timer 1 PWML output
P17: Timer 1 PWMH output/beeper output
Port 2
P20 to P27
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P20 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
P24 to P27: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
P20: UART1 transmit/INT6 input/timer 0L capture 1 input
P21: UART1 receive/Audio interface SDAT input
P22: SIO4 date I/O/parallel interface RD output
P23: SIO4 date I/O/parallel interface WR output
P24: SIO4 clock I/O/INT7 input/timer 0H capture 1 input
P25: Audio interface SDAT I/O
P26: Audio interface BCLK I/O
P27: Audio interface LRCK I/O
Interrupt acknowledge type
Rising
Falling
INT4
enable
enable
INT5
enable
INT6
enable
INT7
enable
Rising &
H level
L level
enable
disable
disable
enable
enable
disable
disable
enable
enable
disable
disable
enable
enable
disable
disable
Falling
Continued on next page.
No.A0477-11/29
LC87F1G64A
Continued from preceding page.
Pin Name
Port 3
I/O
I/O
Description
Option
• 5-bit I/O port
Yes
• I/O specifiable in 1-bit units
P30 to P34
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P30: Audio interface master clock I/O
P31: Audio interface oscillator input
P32: Audio interface oscillator output
P33: Audio interface PLL filter pin (see Fig.6)
P34: USB interface PLL filter pin (see Fig.5)
Port 7
I/O
No
• 4-bit I/O port
• I/O specifiable in 1-bit units
P70 to P73
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P70: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output/
D+ 1.5kΩ pull-up resistor connect pin
P71: INT1 input/HOLD reset input/timer 0H capture input
P72: INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input/
High speed clock counter input
P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input
AD converter input port: AN8(P70), AN9(P71)
Interrupt acknowledge type
PWM0
I/O
PWM1
D-
Rising
Falling
INT0
enable
enable
INT1
enable
enable
INT2
enable
INT3
enable
Rising &
H level
L level
disable
enable
enable
disable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
Falling
• PWM0 and PWM1 output port
No
• General-purpose input port
I/O
• USB data I/O pin D-
No
• General-purpose I/O port
D+
I/O
• USB data I/O pin D+
No
• General-purpose I/O port
RES
Input
Reset pin
No
XT1
Input
• 32.768kHz crystal oscillator input pin
No
• Pin functions
General-purpose input port
AD converter input port: AN10
Must be connected to VDD1 if not to be used.
XT2
I/O
32.768kHz crystal oscillator output pin
No
• Pin functions
General-purpose I/O port
AD converter input port: AN11
Must be set for oscillation and kept open if not to be used.
CF1
Input
CF2
Output
Ceramic resonator input pin
No
Ceramic resonator output pin
No
No.A0477-12/29
LC87F1G64A
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Port Name
Option Selected
in Units of
Option Type
P00 to P07
1 bit
1
P10 to P17
1 bit
P20 to P27
Output Type
Pull-up Resistor
CMOS
Programmable (Note 1)
2
Nch-open drain
No
1
CMOS
Programmable
2
Nch-open drain
Programmable
Programmable
P30 to P34
P70
-
No
Nch-open drain
P71 to P73
-
No
CMOS
Programmable
PWM0, PWM1
-
No
CMOS
No
D+, D-
-
No
CMOS
No
XT1
-
No
Input only
No
XT2
-
No
32.768kHz crystal oscillator output
No
Note 1: Programmable pull-up resistors for port 0 are controlled in 4 bit units (P00 to 03, P04 to 07).
Power Pin Treatment
Connect the IC as shown below to minimize the noise input to the VDD1 pin.
Be sure to electrically short the VSS1, VSS2, and VSS3 pins.
Example 1: When the microcontroller is in the backup state in the HOLD mode, the power to sustain the high level of
output ports is supplied by their backup capacitors.
LSI
Power
supply
For backup
VDD1
VDD2
VDD3
VSS1 VSS2 VSS3
Example 2: The high level output at ports is not sustained and unstable in the HOLD backup mode.
LSI
For backup
Power
supply
VDD1
VDD2
VDD3
VSS1 VSS2 VSS3
No.A0477-13/29
LC87F1G64A
USB Reference Power Option
When a voltage 4.5 to 5.5V is supplied to VDD1 and the internal USB reference voltage circuit is activated, the
reference voltage for USB port output is generated. The active/inactive state of reference voltage circuit can be
switched by the option select. The procedure for marking the option selection is described below.
(1)
Option select
(2)
(3)
(4)
USB Regulator
USE
USE
USE
NONUSE
USB Regulator at HOLD mode
USE
NONUSE
NONUSE
NONUSE
USB Regulator at HALT mode
USE
NONUSE
USE
NONUSE
inactive
Reference voltage circuit
Normal state
active
active
active
state
HOLD mode
active
inactive
inactive
inactive
HALT mode
active
inactive
active
inactive
• When the USB reference voltage circuit is made inactive, the level of the reference voltage for USB port output is
equal to VDD1.
• Selection (2) or (3) can be used to set the reference voltage circuit inactive in HOLD or HALT mode.
• When the reference voltage circuit is activated, the current drain increase by approximately 100µA compared with
when the reference voltage circuit is inactive.
Example 1: VDD1=VDD2=3.3V
• Inactivating the reference voltage circuit (selection (4)).
• Connecting VDD3 to VDD1 and VDD2.
LSI
P70
For backup
1.5kΩ
Power supply
3.3V
VDD1
VDD2
VDD3
D+
To USB connector
27 to 33Ω
D-
UFILT
5pF
0Ω
VSS1 VSS2 VSS3
2.2µF
Example 2: VDD1=VDD2=5.0V
• Activating the reference voltage circuit (selection (1)).
• Isolating VDD3 from VDD1 and VDD2, and connecting capacitor between VDD3 and VSS.
LSI
P70
1.5kΩ
For backup
Power supply
5V
VDD1
D+
To USB connector
27 to 33Ω
DVDD2
5pF
VDD3
2.2µF
UFILT
0Ω
0.1µF
VSS1 VSS2 VSS3
2.2µF
No.A0477-14/29
LC87F1G64A
Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
Maximum supply
VDD max
VDD1, VDD2, VDD3
Input voltage
VI(1)
XT1, CF1
Input/output
VIO(1)
Ports 0, 1, 2, 3, 7
VDD1=VDD2=VDD3
voltage
voltage
Peak output
PWM0, PWM1, XT2
IOPH(1)
Ports 0, 1, 2
current
min
typ
max
unit
-0.3
+6.5
-0.3
VDD+0.3
-0.3
VDD+0.3
V
• When CMOS output
type is selected
-10
• Per 1 applicable pin
IOPH(2)
PWM0, PWM1
Per 1 applicable pin
IOPH(3)
Ports 3
• When CMOS output
P71 to P73
type is selected
-20
-5
High level output current
• Per 1 applicable pin
Average
IOMH(1)
Ports 0, 1, 2
output
type is selected
current
(Note 1-1)
• When CMOS output
-7.5
• Per 1 applicable pin
IOMH(2)
PWM0, PWM1
Per 1 applicable pin
IOMH(3)
Ports 3
• When CMOS output
P71 to P73
type is selected
-15
-3
• Per 1 applicable pin
Total output
ΣIOAH(1)
Ports 0, 2
Total of all applicable pins
current
ΣIOAH(2)
Ports 1
Total of all applicable pins
PWM0, PWM1
ΣIOAH(3)
Ports 0, 1, 2
Total of all applicable pins
PWM0, PWM1
ΣIOAH(4)
Ports 3
Total of all applicable pins
P71 to P73
Peak output
ΣIOAH(5)
D+, D-
Total of all applicable pins
IOPL(1)
P02 to P07
Per 1 applicable pin
current
-25
-25
-45
mA
-10
-25
Ports 1, 2
20
Low level output current
PWM0, PWM1
Average
IOPL(2)
P00, P01
Per 1 applicable pin
30
IOPL(3)
Ports 3, 7, XT2
Per 1 applicable pin
10
IOML(1)
P02 to P07
Per 1 applicable pin
output
Ports 1, 2
current
PWM0, PWM1
(Note 1-1)
15
IOML(2)
P00, P01
Per 1 applicable pin
20
IOML(3)
Ports 3, 7, XT2
Per 1 applicable pin
7.5
Total output
ΣIOAL(1)
Ports 0, 2
Total of all applicable pins
45
current
ΣIOAL(2)
Ports 1
Total of all applicable pins
45
PWM0, PWM1
ΣIOAL(3)
Ports 0, 1, 2
Total of all applicable pins
80
PWM0, PWM1
Allowable power
ΣIOAL(4)
Ports 3, 7, XT2
Total of all applicable pins
15
ΣIOAL(5)
D+, D-
Total of all applicable pins
25
Pd max
QIP48E(14×14)
Ta=-20to+70°C
Dissipation
Operating ambient
190
TQFP64J(10×10)
280
Topr
Temperature
Storage ambient
330
TQFP48J(7×7)
Tstg
temperature
-20
+70
-55
+125
mW
°C
Note 1-1: The mean output current is a mean value measured over 100ms.
No.A0477-15/29
LC87F1G64A
Allowable Operating Conditions at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
Operating
VDD(1)
VDD1=VDD2=VDD3
0.245µs≤tCYC≤200µs
supply voltage
0.490µs≤tCYC≤200µs Except
(Note 2-1)
for onboard programming
Memory
VHD
VDD1=VDD2=VDD3
sustaining
min
typ
max
unit
3.0
5.5
2.7
5.5
2.0
5.5
0.3VDD
VDD
RAM and register contents
sustained in HOLD mode.
supply voltage
High level
VIH(1)
input voltage
Ports 0, 1, 2, 3
P71 to P73
P70 port input/
2.7 to 5.5
interrupt side
+0.7
PWM0, PWM1
VIH(2)
Port 70 watchdog
timer side
Low level
VIH(3)
XT1, XT2, CF1, RES
VIL(1)
Ports 1, 2
input voltage
P71 to P73
VIL(2)
P70 port input/
interrupt side
VIL(3)
Ports 0, 3
PWM0, PWM1
VIL(4)
VIL(5)
Port 70 watchdog
timer side
VIL(6)
Instruction
XT1, XT2, CF1, RES
tCYC
cycle time
Except for onboard
(Note 2-2)
programming
External
FEXCF(1)
CF1
system clock
2.7 to 5.5
0.9VDD
VDD
2.7 to 5.5
0.75VDD
4.0 to 5.5
VSS
VDD
0.1VDD
2.7 to 4.0
VSS
4.0 to 5.5
VSS
2.7 to 4.0
VSS
2.7 to 5.5
VSS
2.7 to 5.5
VSS
0.25VDD
3.0 to 5.5
0.245
200
2.7 to 5.5
0.490
200
3.0 to 5.5
0.1
12
V
+0.4
0.2VDD
0.15VDD
+0.4
0.2VDD
0.8VDD
-1.0
µs
• CF2 pin open
• System clock frequency
frequency
division ratio=1/1
• External system clock duty
=50±5%
MHz
• CF2 pin open
• System clock frequency
division ratio=1/1
2.7 to 5.5
0.1
6
• External system clock duty
=50±5%
Oscillation
FmCF(1)
CF1, CF2
frequency
range
12 MHz ceramic oscillation
See Fig. 1.
FmCF(2)
CF1, CF2
(Note 2-3)
6 MHz ceramic oscillation
See Fig. 1.
FmRC
FsX’tal
Internal RC oscillation
XT1, XT2
32.768kHz crystal oscillation
See Fig. 2.
3.0 to 5.5
12
2.7 to 5.5
6
2.7 to 5.5
2.7 to 5.5
0.3
1.0
MHz
2.0
32.768
kHz
Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Note 2-3: See Tables 1 and 2 for the oscillation constants.
No.A0477-16/29
LC87F1G64A
Electrical Characteristics at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
High level input
IIH(1)
current
IIH(2)
Ports 0, 1, 2, 3
Output disabled
Port 7
Pull-up resistor off
RES
PWM0, PWM1
VIN=VDD
(Including output Tr's off
D+, D-
leakage current)
XT1, XT2
IIH(3)
CF1
VIN=VDD
IIL(1)
Ports 0, 1, 2, 3
Output disabled
Port 7
Pull-up resistor off
RES
PWM0, PWM1
VIN=VSS
(Including output Tr's off
D+, D-
leakage current)
current
IIL(2)
typ
unit
2.7 to 5.5
1
2.7 to 5.5
1
2.7 to 5.5
15
2.7 to 5.5
-1
XT1, XT2
For input port specification
2.7 to 5.5
-1
2.7 to 5.5
-15
IIL(3)
CF1
VIN=VSS
VIN=VSS
High level output
VOH(1)
Ports 0, 1, 2, 3
IOH=-1mA
4.5 to 5.5
VDD-1
voltage
VOH(2)
P71 to P73
IOH=-0.4mA
3.0 to 5.5
VDD-0.4
VOH(3)
max
For input port specification
VIN=VDD
Low level input
min
IOH=-0.2mA
2.7 to 5.5
VDD-0.4
VOH(4)
P30 (when using
IOH=-1.6mA
3.0 to 5.5
VDD-0.4
VOH(5)
MCLK output
IOH=-1mA
2.7 to 5.5
VDD-0.4
µA
function)
P73 (when using
clock output
function)
VOH(6)
PWM0, PWM1
IOH=-10mA
4.5 to 5.5
VDD-1.5
VOH(7)
P05 (CK0 when
IOH=-1.6mA
3.0 to 5.5
VDD-0.4
IOH=-1mA
2.7 to 5.5
VDD-0.4
VOH(8)
using system clock
output function)
P00, P01
V
Low level output
VOL(1)
IOL=30mA
4.5 to 5.5
1.5
voltage
VOL(2)
IOL=5mA
3.0 to 5.5
0.4
VOL(3)
IOL=2.5mA
2.7 to 5.5
0.4
VOL(4)
Ports 0, 1, 2
IOL=10mA
4.5 to 5.5
1.5
VOL(5)
PWM0, PWM1
IOL=1.6mA
3.0 to 5.5
0.4
IOL=1mA
2.7 to 5.5
0.4
IOL=1.6mA
3.0 to 5.5
0.4
IOL=1mA
2.7 to 5.5
0.4
VOH=0.9VDD
VOL(6)
VOL(7)
XT2
Ports 3, 7
VOL(8)
Pull-up resistance
Rpu(1)
Ports 0, 1, 2, 3
4.5 to 5.5
15
35
80
Rpu(2)
Port 7
2.7 to 5.5
18
50
150
Hysteresis voltage
VHYS
RES
Ports 1, 2, 7
2.7 to 5.5
0.1VDD
V
Pin capacitance
CP
All pins
2.7 to 5.5
10
pF
kΩ
For pins other than that
under test:
VIN=VSS
f=1MHz
Ta=25°C
No.A0477-17/29
LC87F1G64A
Serial I/O Characteristics at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
Frequency
tSCK(1)
Low level
tSCKL(1)
SCK0(P12)
See Fig.9.
typ
max
unit
2
1
pulse width
High level
min
tSCKH(1)
1
pulse width
tSCKHA(1a)
• Continuous data transmission/
reception mode
• USB, SIO4 nor AIF are not in
4
use simultaneous.
Input clock
• See Fig.9.
• (Note 4-1-2)
tSCKHA(1b)
• Continuous data
2.7 to 5.5
tCYC
transmission/reception mode
• USB is in use simultaneous.
7
• SIO4 nor AIF are not in use
simultaneous.
• See Fig.9.
• (Note 4-1-2)
tSCKHA(1c)
• Continuous data transmission/
reception mode
• USB, SIO4 and AIF are in use
9
simultaneous.
Serial clock
• See Fig.9.
• (Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
• CMOS output selected
4/3
• See Fig.9.
Low level
tSCKL(2)
1/2
pulse width
High level
tSCK
tSCKH(2)
1/2
pulse width
tSCKHA(2a)
• Continuous data transmission/
reception mode
tSCKH(2)
• USB, SIO4 nor AIF are not in
Output clock
use simultaneous.
+2tCYC
• CMOS output selected
tSCKH(2)
+(10/3)
tCYC
• See Fig.9.
tSCKHA(2b)
• Continuous data transmission/
2.7 to 5.5
reception mode
• USB is in use simultaneous.
• SIO4 nor AIF are not in use
simultaneous.
tSCKH(2)
+2tCYC
tSCKH(2)
+(19/3)
tCYC
tCYC
• CMOS output selected
• See Fig.9.
tSCKHA(2c)
• Continuous data transmission/
reception mode
• USB, SIO4 and AIF are in use
simultaneous.
• CMOS output selected
tSCKH(2)
+2tCYC
tSCKH(2)
+(25/3)
tCYC
• See Fig.9.
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is
"H" to the first negative edge of the serial clock must be longer than tSCKHA.
Continued on next page.
No.A0477-18/29
LC87F1G64A
Continued from preceding page.
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
Serial input
Data setup time
SB0(P11),
SI0(P11)
typ
max
unit
• Must be specified with respect
to rising edge of SIOCLK.
2.7 to 5.5
0.03
2.7 to 5.5
0.03
• See Fig.9.
Data hold time
thDI(1)
tdD0(1)
time
SO0(P10),
SB0(P11)
• Continuous data
transmission/reception mode
(1/3)tCYC
2.7 to 5.5
+0.05
• (Note 4-1-3)
tdD0(2)
• Synchronous 8-bit mode
• (Note 4-1-3)
tdD0(3)
Output clock
Input clock
Output delay
Serial output
tsDI(1)
min
µs
1tCYC
2.7 to 5.5
+0.05
(Note 4-1-3)
(1/3)tCYC
2.7 to 5.5
+0.05
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig.9.
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Parameter
Symbol
Pin/Remarks
Specification
Conditions
Frequency
tSCK(3)
Low level
tSCKL(3)
SCK1(P15)
See Fig.9.
2.7 to 5.5
pulse width
High level
Frequency
SCK1(P15)
• CMOS output selected
2
1/2
2.7 to 5.5
tSCK
tSCKH(4)
1/2
pulse width
Serial input
Data setup time
tsDI(2)
SB1(P14),
SI1(P14)
• Must be specified with
respect to rising edge of
2.7 to 5.5
0.03
2.7 to 5.5
0.03
SIOCLK.
Data hold time
Output delay time
• See Fig.9.
thDI(2)
tdD0(4)
SO1(P13),
SB1(P14)
Serial output
unit
1
tSCKL(4)
pulse width
High level
max
1
• See Fig.9.
Low level
typ
tCYC
tSCKH(3)
tSCK(4)
min
2
pulse width
Output clock
Serial clock
Input clock
VDD[V]
• Must be specified with
µs
respect to falling edge of
SIOCLK.
• Must be specified as the time
to the beginning of output state
2.7 to 5.5
(1/3)tCYC
+0.05
change in open drain output
mode.
• See Fig.9.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
No.A0477-19/29
LC87F1G64A
3. SIO4 Serial I/O Characteristics (Note 4-3-1)
Parameter
Symbol
Frequency
tSCK(5)
Low level
tSCKL(5)
Pin/
SCK4(P24)
Specification
Conditions
Remarks
VDD[V]
See Fig.9.
tSCKH(5)
pulse width
tSCKHA(5a)
typ
max
unit
2
1
pulse width
High level
min
1
• USB, AIF nor continuous data
Transmission/reception mode
Of SIO0 are not in use
4
simultaneous.
• See Fig.9.
Input clock
• (Note 4-3-2)
tSCKHA(5b)
• USB is in use simultaneous.
• AIF nor continuous data
2.7 to 5.5
tCYC
transmission/reception mode
7
of SIO0 are not in use
simultaneous.
• See Fig.9.
• (Note 4-3-2)
tSCKHA(5c)
• USB and continuous
data transmission/ reception
mode of SIO0 are in use
10
simultaneous.
• AIF is not in use simultaneous.
Serial clock
• See Fig.9.
• (Note 4-3-2)
Frequency
tSCK(6)
SCK4(P24)
• CMOS output selected
4/3
• See Fig.9.
Low level
tSCKL(6)
1/2
pulse width
High level
tSCK
tSCKH(6)
1/2
pulse width
tSCKHA(6a)
• USB, AIF nor continuous data
transmission/reception mode
tSCKH(6)
tSCKH(6)
+(5/3)
+(10/3)
tCYC
tCYC
data transmission/reception
tSCKH(6)
tSCKH(6)
mode of SIO0 are not in use
+(5/3)
+(19/3)
simultaneous.
tCYC
tCYC
tSCKH(6)
tSCKH(6)
+(5/3)
+(28/3)
tCYC
tCYC
of SIO0 are not in use
simultaneous.
Output clock
• CMOS output selected
• See Fig.9.
tSCKHA(6b)
• USB is in use simultaneous.
2.7 to 5.5
• AIF nor continuous
tCYC
• CMOS output selected
• See Fig.9.
tSCKHA(6c)
• USB and continuous
data transmission/reception
mode of SIO0 are in use
simultaneous.
• AIF is not in use simultaneous.
• CMOS output selected
• See Fig.9.
Serial input
Data setup time
tsDI(3)
SO4(P22),
SI4(P23)
• Must be specified with respect
to rising edge of SIOCLK.
2.7 to 5.5
0.03
• See Fig.9.
Data hold time
µs
thDI(3)
2.7 to 5.5
0.03
Note 4-3-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-3-2: To use serial-clock-input in continuous trans/rec mode, a time from SI4RUN being set when serial clock is
"H" to the first negative edge of the serial clock must be longer than tSCKHA.
Continued on next page.
No.A0477-20/29
LC87F1G64A
Continued from preceding page.
Parameter
Pin/
Symbol
Output delay time
tdD0(5)
SO4(P22),
Serial output
SI4(P23)
Specification
Conditions
Remarks
VDD[V]
min
typ
max
unit
(1/3)tCYC
µs
• Must be specified with
respect to rising edge of
SIOCLK.
• Must be specified as the time
to the beginning of output state
2.7 to 5.5
+0.05
change in open drain output
mode.
• See Fig.9.
Pulse Input Conditions at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
High/low level
tP1H(1)
INT0(P70),
• Interrupt source flag can be set.
pulse width
tP1L(1)
INT1(P71),
• Event inputs for timer 0 or 1 are
INT2(P72),
min
typ
max
unit
enabled.
INT4(P20 to P23),
2.7 to 5.5
1
2.7 to 5.5
2
2.7 to 5.5
64
2.7 to 5.5
256
2.7 to 5.5
200
INT5(P24 to P27),
INT6(P20),
INT7(P24)
tPIH(2)
INT3(P73) when
• Interrupt source flag can be set.
tPIL(2)
noise filter time
• Event inputs for timer 0 are
constant is 1/1
enabled.
tPIH(3)
INT3(P73) when
• Interrupt source flag can be set.
tPIL(3)
noise filter time
• Event inputs for timer 0 are
constant is 1/32
enabled.
tPIH(4)
INT3(P73) when
• Interrupt source flag can be set.
tPIL(4)
noise filter time
• Event inputs for timer 0 are
constant is 1/128
tPIL(5)
RES
tCYC
enabled.
Resetting is enabled.
µs
AD Converter Characteristics at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
Resolution
N
AN0(P00) to
Absolute
ET
AN7(P07),
(Note 6-1)
accuracy
AN8(P70),
Conversion
AN9(P71),
AD conversion time=32×tCYC
AN10(XT1),
(when ADCR2=0) (Note 6-2)
TCAD
time
typ
4.5 to 5.5
3.0 to 5.5
AD conversion time=64×tCYC
(when ADCR2=1) (Note 6-2)
4.5 to 5.5
3.0 to 5.5
VAIN
3.0 to 5.5
voltage range
Analog port
IAINH
VAIN=VDD
3.0 to 5.5
input current
IAINL
VAIN=VSS
3.0 to 5.5
max
unit
8
3.0 to 5.5
AN11(XT2)
Analog input
min
3.0 to 5.5
bit
±1.5
15.68
97.92
(tCYC=
(tCYC=
0.49µs)
3.06µs)
23.52
97.92
(tCYC=
(tCYC=
0.735µs)
3.06µs)
18.82
97.92
(tCYC=
(tCYC=
0. 294µs)
1.53µs)
47.04
97.92
(tCYC=
(tCYC=
0. 735µs)
1.53µs)
VSS
VDD
1
LSB
µs
V
µA
-1
Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy value.
Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till
the time the complete digital value corresponding to the analog input value is loaded in the required register.
No.A0477-21/29
LC87F1G64A
Consumption Current Characteristics at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Normal mode
IDDOP(1)
consumption
IDDOP(2)
current
Pin/
VDD[V]
VDD1
=VDD2
• FmCF=12MHz ceramic oscillation mode
=VDD3
• System clock set to 12MHz side
(Note 7-1)
Specification
Conditions
Remarks
4.5 to 5.5
min
typ
max
9.9
24
5.6
14
4.5 to 5.5
13
32
3.0 to 3.6
7.3
18
unit
• FsX’tal=32.768kHz crystal oscillation mode
• Internal PLL oscillation stopped
3.0 to 3.6
• Internal RC oscillation stopped
• 1/1 frequency division ration
IDDOP(3)
• FmCF=12MHz ceramic oscillation mode
IDDOP(4)
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side
• Internal PLL oscillation mode
• Internal RC oscillation stopped
mA
• 1/1 frequency division ration
IDDOP(5)
• FmCF=12MHz ceramic oscillation mode
4.5 to 5.5
6.4
15
IDDOP(6)
• FsX’tal=32.768kHz crystal oscillation mode
3.0 to 3.6
3.7
8.7
2.7 to 3.0
3.0
6.7
• System clock set to 6MHz side
IDDOP(7)
• Internal RC oscillation stopped
• 1/2 frequency division ration
IDDOP(8)
• FmCF=0MHz (oscillation stopped)
4.5 to 5.5
0.67
3.2
IDDOP(9)
• FsX’tal=32.768kHz crystal oscillation mode
3.0 to 3.6
0.35
1.6
• System clock set to internal RC oscillation
IDDOP(10)
• 1/2 frequency division ration
2.7 to 3.0
0.30
1.3
IDDOP(11)
• FmCF=0MHz (oscillation stopped)
4.5 to 5.5
41
160
IDDOP(12)
• FsX’tal=32.768kHz crystal oscillation mode
3.0 to 3.6
17
60
2.7 to 3.0
14
43
4.5 to 5.5
4.9
12
3.0 to 3.6
2.7
6.5
4.5 to 5.5
7.3
18
• System clock set to 32.768kHz side
IDDOP(13)
• Internal RC oscillation stopped
µA
• 1/2 frequency division ration
HALT mode
IDDHALT(1)
consumption
IDDHALT(2)
current
VDD1
=VDD2
• HALT mode
=VDD3
• FsX’tal=32.768kHz crystal oscillation mode
• FmCF=12MHz ceramic oscillation mode
• System clock set to 12MHz side
(Note 7-1)
• Internal PLL oscillation stopped
• Internal RC oscillation stopped
• 1/1 frequency division ration
IDDHALT(3)
• HALT mode
IDDHALT(4)
• FmCF=12MHz ceramic oscillation mode
• FsX’tal=32.768kHz crystal oscillation mode
mA
• System clock set to 12MHz side
• Internal PLL oscillation mode
3.0 to 3.6
4.0
9.6
• Internal RC oscillation stopped
• 1/1 frequency division ration
IDDHALT(5)
• HALT mode
4.5 to 5.5
3.0
7.2
IDDHALT(6)
• FmCF=12MHz ceramic oscillation mode
3.0 to 3.6
1.6
3.9
2.7 to 3.0
1.3
3.0
IDDHALT(7)
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 6MHz side
• Internal RC oscillation stopped
• 1/2 frequency division ration
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
Continued on next page.
No.A0477-22/29
LC87F1G64A
Continued from preceding page.
Parameter
Symbol
VDD[V]
min
typ
max
• HALT mode
4.5 to 5.5
0.37
1.8
IDDHALT(9)
• FmCF=0MHz (oscillation stopped)
3.0 to 3.6
0.18
0.83
IDDHALT(10)
=VDD3
• FsX'tal=32.768kHz crystal oscillation mode
IDDHALT(8)
consumption
(Note 7-1)
Specification
Conditions
VDD1
=VDD2
HALT mode
current
Pin/
Remarks
• System clock set to internal RC oscillation
unit
mA
2.7 to 3.0
0.15
0.62
• 1/2 frequency division ration
IDDHALT(11)
• HALT mode
4.5 to 5.5
26
110
IDDHALT(12)
• FmCF=0MHz (oscillation stopped)
3.0 to 3.6
8.2
33
2.7 to 3.0
5.8
22
HOLD mode
4.5 to 5.5
0.14
24
• CF1=VDD or open (External clock mode)
3.0 to 3.6
0.04
15
2.7 to 3.0
0.03
12
Timer HOLD mode
4.5 to 5.5
21
90
• CF1=VDD or open (External clock mode)
3.0 to 3.6
5.1
24
2.7 to 3.0
3.3
14
• FsX'tal=32.768kHz crystal oscillation mode
IDDHALT(13)
• System clock set to 32.768kHz side
• Internal RC oscillation stopped
• 1/2 frequency division ration
HOLD mode
IDDHOLD(1)
consumption
IDDHOLD(2)
current
VDD1
IDDHOLD(3)
Timer HOLD
IDDHOLD(4)
mode
VDD1
IDDHOLD(5)
consumption
µA
• FsX’tal=32.768kHz crystal oscillation mode
IDDHOLD(6)
current
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
USB Characteristics and Timing at Ta = 0°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Specification
Conditions
min
typ
max
unit
High level output
VOH(USB)
• 15kΩ±5% to GND
2.8
3.6
V
Low level output
VOL(USB)
• 1.5kΩ±5% to 3.6 V
0.0
0.3
V
Output signal crossover voltage
VCRS
1.3
2.0
V
Differential input sensitivity
VDI
Differential input common mode range
VCM
0.8
2.5
V
High level input
VIH(USB)
2.0
Low level input
VIL(USB)
USB data rise time
tR
• |(D+)-(D-)|
0.2
• RS=27 to 33Ω,CL=50pF
• VDD3=3.0 to 3.6V
USB data fall time
tF
• RS=27 to 33Ω,CL=50pF
• VDD3=3.0 to 3.6V
V
V
0.8
V
4
20
ns
4
20
ns
F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2= VSS3 =0V
Parameter
Symbol
Pin
Specification
Conditions
VDD[V]
Onboard
IDDFW(1)
programming
VDD1
min
typ
max
unit
• 128-byte programming
• Erasing current included
3.0 to 5.5
25
40
mA
3.0 to 5.5
22.5
45
ms
current
Programming
time
tFW(1)
• 128-byte programming
• Erasing current included
• Time for setting up 128-byte
data is excluded.
No.A0477-23/29
LC87F1G64A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a
SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values
with which the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Nominal
Vendor
Frequency
Name
Circuit Constant
Oscillator Name
Operating
Oscillation
Voltage
Stabilization Time
C1
C2
Rd1
Range
[pF]
[pF]
[Ω]
[V]
[ms]
[ms]
1k
2.7 to 5.5
0.05
0.50
6MHz
MURATA
CSTCR6M00G15***-R0
(39)
(39)
typ
Remarks
max
8MHz
MURATA
CSTCE8M00G15***-R0
(33)
(33)
680
3.0 to 5.5
0.05
0.50
10MHz
MURATA
CSTCE10M0G15***-R0
(33)
(33)
470
3.0 to 5.5
0.05
0.50
12MHz
MURATA
CSTCE12M0G15***-R0
(33)
(33)
470
3.0 to 5.5
0.05
0.50
Built-in C1, C2
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD
goes above the operating voltage lower limit (see Figure 4).
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a CF Oscillator
Nominal
Vendor
Frequency
Name
32.768kHz
EPSON
TOYOCOM
Circuit Constant
Oscillator Name
MC-306
Operating
Oscillation
Voltage
Stabilization Time
C3
C4
Rf
Rd2
Range
typ
max
[pF]
[pF]
[Ω]
[Ω]
[V]
[s]
[s]
18
18
OPEN
510k
2.7 to 5.5
1.1
3.0
Remarks
Applicable
CL value=12.5pF
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode is reset (see Figure 4).
Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
CF1
CF2
XT1
Rd1
C1
CF
C2
XT2
Rf
Rd2
C4
C3
X’tal
Figure 1 CF Oscillator Circuit
Figure 2 XT Oscillator Circuit
0.5VDD
Figure 3 AC Timing Measurement Point
No.A0477-24/29
LC87F1G64A
VDD
Operating VDD
lower limit
GND
Power Supply
Reset time
RES
Internal RC
oscillation
tmsCF
CF oscillation
(XT1, XT2)
tmsX’tal
Crystal
oscillation
(XT1, XT2)
Operating mode
Unpredictable
Reset
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD reset
signal
HOLD reset signal valid
Internal RC
oscillation
tmsCF
CF oscillation
(XT1, XT2)
tmsX’tal
Crystal
Oscillation
(XT1, XT2)
Operating mode
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Time
No.A0477-25/29
LC87F1G64A
P34/UFILT
When using the internal PLL circuit to generate
the 48 MHz clock for USB , it is necessary to
connect a filter circuit such as that shown to the
left to the P34/UFILT pin.
Rd
0Ω
+
-
Cd
2.2µF
Figure 5 External Filter Circuit for the Internal USB-dedicated PLL Circuit
P33/AFILT
Rd
2kΩ
Cp
10µF
+
-
Cd
33µF
When using the internal PLL circuit to generate the
master clock for the audio interface, it is necessary
to connect a filter circuit such as that shown to the
left to the P33 pin.
Figure 6 External Filter Circuit for the Internal Audio Interface Dedicated PLL Circuit
No.A0477-26/29
LC87F1G64A
VD3OEN
P70
Note:
It’s necessary to adjust the Circuit Constant of the USB
Port Peripheral Circuit each mounting board. Make the
D+ Pull-up resistors available to control on/off according
to the Vbus.
1.5kΩ
D+
27 to 33Ω
5pF
D27 to 33Ω
5pF
Figure 7 USB Port Peripheral Circuit
VDD
RRES
RES
CRES
Note:
Determine the value of CRES and RRES so
that the reset signal is present for a period of
200µs after the supply voltage goes beyond the
lower limit of the IC's operating voltage.
Figure 8 Reset Circuit
No.A0477-27/29
LC87F1G64A
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
Data RAM transfer period
(SIO0, 4 only)
tSCK
tSCKL
tSCKH
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Data RAM transfer period
(SIO0, 4 only)
tSCKL
tSCKHA
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Figure 9 Serial I/O Waveforms
tPIL
tPIH
Figure 10 Pulse Input Timing Signal Waveform
Voh
tr
D+
tr
90%
90%
Vcrs
10%
Vol
10%
D-
Figure 11 USB Data Signal Timing and Voltage Level
No.A0477-28/29
LC87F1G64A
Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the
performance, characteristics, and functions of the described products in the independent state, and are
not guarantees of the performance, characteristics, and functions of the described products as mounted
in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an
independent device, the customer should always evaluate and test devices mounted in the customer's
products or equipment.
SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any
and all semiconductor products fail with some probability. It is possible that these probabilistic failures
could give rise to accidents or events that could endanger human lives, that could give rise to smoke or
fire, or that could cause damage to other property. When designing equipment, adopt safety measures
so that these kinds of accidents or events cannot occur. Such measures include but are not limited to
protective circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO Semiconductor products (including technical data,services) described
or contained herein are controlled under any of applicable local export control laws and regulations, such
products must not be exported without obtaining the export license from the authorities concerned in
accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
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otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"
for the SANYO Semiconductor product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and
reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual
property rights or other rights of third parties.
This catalog provides information as of December, 2006. Specifications and information herein are subject
to change without notice.
PS No.A0477-29/29