www.fairchildsemi.com UC3842A/UC3843A SMPS Controller Features Description • • • • • • • The UC3842A/UC3843A are fixed PWM controller for OffLine and DC to DC converter applications. The internal circuits include UVLO, low start up current circuit, temperature compensated reference, high gain error amplifier, current sensing comparator, and high current totem-pole output for driving a POWER MOSFET. Also UC3842A/ UC3843A provide low start up current below 0.3mA and short shutdown delay time typ. 100ns. The UC3842A has UVLO threshold of 16V(on) and 10V(off). The UC3843A is 8.4V(on) and 7.6V(off). The UC3842A and UC3843A can operate within 100% duty cycle. Low Start Current 0.2mA (typ) Operating Range Up To 500KHz Cycle by Cycle Current Limiting Under Voltage Lock Out With Hysteresis Short Shutdown Delay Time: typ.100ns High Current Totem-pole Output Output Swing Limiting: 22V 8-DIP 1 8-SOP 1 Internal Block Diagram 7 VCC 29V 5V VREF VREF 8 SET/ RESET 5 GND UVLO Internal Bias Good LOGIC 7 PWR VC 1/2VREF VFB 2 Error Amp + - C.S PWM Comp. LATCH 1/3 R 22V 1V 6 OUTPUT S COMP 1 5 PWR T C.S 3 RT/CT 4 GND OSCILLATOR Rev. 5.0 ©2000 Fairchild Semiconductor International UC3842A/UC3843A Absolute Maximum Ratings Parameter Supply Voltage Output Current Analog Inputs (pin 2, 3) Error Amp. Output Sink Current Power Dissipation Symbol Value Unit VCC 30 V IO ±1 A VI(ANA) - 0.3 to 6.3 V ISINK(EA) 10 mA PD 1 W Electrical Characteristics (VCC = 15V, RT = 10KΩ, CT = 3.3nF, TA = 0°C to + 70°C ,Unless otherwise specified) Parameter Symbol Conditions Min. Typ. Max. Unit REFERENCE SECTION Output Voltage VREF 4.9 5.0 5.1 V Line Regulation ∆VREF VCC = 12V to 25V - 6 20 mV Load Regulation Output Short Circuit ∆VREF ISC IO = 1mA to 20mA Ta = 25°C - Initial Accuracy FOSC TJ = 25°C 47 52 57 KHz Voltage Stability Amplitude STV VOSC VCC = 12V to 25V VPIN4, Peak to Peak - 0.2 1.7 1 - % V IDISCHG TJ = 25°C, Pin4 = 2V 7.8 8.3 8.8 mA GV VI(MAX) (NOTE 2, 3) VPIN1 = 5V(NOTE 2) 2.85 0.9 3 1.0 3.15 1.1 V/V V TJ = 25°C, IO = 1mA 6 25 - 100 - 180 mV mA OSILLATOR SECTION Discharge Current CURRENT SENSE SECTION Gain Maximum Input Signal PSRR PSRR Input Bias Current IBIAS Delay to Output 2 TD VCC = 12V to 25V (NOTE 1, 2) VPIN3 = 0 V to 2V (NOTE1) - 70 - dB - -2 -10 uA - 100 200 ns UC3842A/UC3843A Electrical Characteristics (Continued) (VCC = 15V, RT = 10KΩ, CT = 3.3nF, TA = 0°C to + 70°C, Unless otherwise specified) Parameter Symbol Conditions Min. Typ. Max. Unit 2.42 2.50 2.58 V - -0.3 -2 uA ERROR AMPLIFIER SECTION Input Voltage Input Bias Current VI TPIN1 = 2.5V - IBIAS Open Loop Gain GVO VO = 2V to 4V (NOTE 1) 65 90 - dB Unity Gain Bandwidth GBW TJ= 25°C (NOTE 1) 0.7 1 - MHz PSRR PSRR VCC = 12V to 25V (NOTE 1) 60 70 - dB Output Sink Current ISINK VPIN2 = 2.7V VPIN1 = 1.1V 2 6 - mA ISOURCE VPIN2 = 2.3V VPIN1 = 5.0V -0.5 -0.8 - mA Output Source Current Output High Voltage VOH VPIN2 = 2.3V R1 = 15KΩ to GND 5 6 - V Output Low Voltage VOL VPIN2 = 2.7V R1 = 15KΩ to Pin8 - 0.8 1.1 V VOL ISINK = 20mA - 0.1 0.4 V ISINK = 200mA - 1.5 2.2 V ISOURCE = 20mA 13 13.5 - V ISOURCE = 200mA 12 13.5 - V OUTPUT SECTION Output Low Level Output High Level VOH Rise Time tR TJ = 25°C, C1 = 1nF (NOTE 1) - 40 100 ns Fall Time tF TJ = 25°C, C1 = 1nF (NOTE 1) - 40 100 ns VCC = 27V, C1 = 1nF - 22 - V UC3842A 15 16 17 V Output Voltage Swing Limit VOLIM UNDER VOLTAGE LOCKOUT SECTION Start Threshold Min. Operating Voltage ( After turn on ) VTH VTL UC3843A 7.8 8.4 9.0 V UC3842A 9 10 11 V UC3843A 7.0 7.6 8.2 V UC3842A/UC3843A 94 96 100 % PWM SECTION Maximum Duty Cycle DMAX Minimum Duty Cycle DMIN - - - 0 % Start-Up Current IST - - 0.2 0.4 mA Operating Supply Current ICC VPIN2 = VPIN3 = 0V - 11 17 mA VCC Zener Voltage VZ ICC = 25mA - 29 - V TOTAL STANDBY CURRENT * Adjust VCC above the start threshold before setting at 15V Notes : 1. These parameters, although guaranteed, are not 100% tested in production. 2. Parameter measured at trip point of latch with V2 = 0V. 3. Gain defined as: GV = ∆VPIN1∆VPIN3(VPIN3 = 0 to 0.8V) 3 UC3842A/UC3843A Mechanical Dimensions Package 1.524 ±0.10 #5 2.54 0.100 5.08 MAX 0.200 7.62 0.300 3.40 ±0.20 0.134 ±0.008 +0.10 0.25 –0.05 +0.004 0~15° 4 0.010 –0.002 3.30 ±0.30 0.130 ±0.012 0.33 0.013 MIN 0.060 ±0.004 #4 0.018 ±0.004 #8 9.60 MAX 0.378 #1 9.20 ±0.20 0.362 ±0.008 ( 6.40 ±0.20 0.252 ±0.008 0.46 ±0.10 0.79 ) 0.031 8-DIP UC3842A/UC3843A Mechanical Dimensions (Continued) Package 8-SOP MIN #5 6.00 ±0.30 0.236 ±0.012 8° 0~ +0.10 0.15 -0.05 +0.004 0.006 -0.002 MAX0.10 MAX0.004 1.80 MAX 0.071 3.95 ±0.20 0.156 ±0.008 5.72 0.225 0.41 ±0.10 0.016 ±0.004 #4 1.27 0.050 #8 5.13 MAX 0.202 #1 4.92 ±0.20 0.194 ±0.008 ( 0.56 ) 0.022 1.55 ±0.20 0.061 ±0.008 0.1~0.25 0.004~0.001 0.50 ±0.20 0.020 ±0.008 5 UC3842A/UC3843A Ordering Information 6 Product Number Package UC3842AN 8 DIP UC3842AD 8 SOP UC3843AN 8 DIP UC3843AD 8 SOP Operating Temperature 0 ~ + 70°C UC3842A/UC3843A 7 UC3842A/UC3843A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR INTERNATIONAL. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 7/12/00 0.0m 001 Stock#DSxxxxxxxx ” 2000 Fairchild Semiconductor International