STMICROELECTRONICS VND5E050J-E

VND5E050J-E
VND5E050K-E
Double channel high side driver for automotive applications
Features
Max supply voltage
VCC
41V
Operating voltage range
VCC
4.5 to 28V
Max On-State resistance (per ch.)
RON
50 mΩ
Current limitation (typ)
ILIMH
27 A
Off-state supply current
IS
2 µA(1)
PowerSSO-12
PowerSSO-24
1. Typical value with all loads connected.
Applications
■
■
■
General
– Inrush current active management by
power limitation
– Very low standby current
– 3.0V CMOS compatible inputs
– Optimized electromagnetic emissions
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC
european directive
Diagnostic functions
– Open Drain status output
– On-state open-load detection
– Off-state open-load detection
– Output short to Vcc detection
– Overload and short to ground (power
limitation) indication
– Thermal shutdown indication
Protections
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss
of VCC
– Over temperature shutdown with auto
restart (thermal shutdown)
– Reverse battery protected (see Figure 32)
– Electrostatic discharge protection
July 2009
■
All types of resistive, inductive and capacitive
loads
Description
The VND5E050J-E and VND5E050K-E are
double channel high-side drivers manufactured in
the ST proprietary VIPower M0-5 technology
and housed in the tiny PowerSSO-12 and
PowerSSO-24 packages.
The VND5E050J-E and VND5E050K-E are
designed to drive automotive grounded loads
delivering protection, diagnostics and easy 3V
and 5V CMOS-compatible interface with any
microcontroller.
The devices integrate advanced protective
functions such as load current limitation, inrush
and overload active management by power
limitation, over temperature shut-off with
auto-restart and over-voltage active clamp.
A dedicated active low digital status pin is
associated with every output channel in order to
provide Enhanced diagnostic functions including
fast detection of overload and short-circuit to
ground, over temperature indication, short-circuit
to VCC diagnosis and on & off-state open-load
detection.
The diagnostic feedback of the whole device can
be disabled by pulling the STAT_DIS pin up, thus
allowing wired-ORing with other similar devices.
Doc ID 14472 Rev 3
1/40
www.st.com
1
Contents
VND5E050K-E
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1
4
5
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 22
3.1.1
Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 22
3.1.2
Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 23
3.2
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3
MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4
Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.5
Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 25
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1
PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2
PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2
PowerSSO-12 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.3
PowerSSO-24 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.4
PowerSSO-12 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.5
PowerSSO-24 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2/40
Doc ID 14472 Rev 3
VND5E050K-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 20.
Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switching (VCC = 13V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Status pin (VSD=0V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Openload detection (8V<VCC<18V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Electrical transient requirements (part 1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Electrical transient requirements (part 2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Electrical transient requirements (part 3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PowerSSO-12 thermal parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PowerSSO-24 thermal parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PowerSSO-24™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Doc ID 14472 Rev 3
3/40
List of figures
VND5E050K-E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
4/40
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Overload or Short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Intermittent Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Open-load with external pull-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Open-load without external pull-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Short to VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TJ evolution in overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Low level STAT_DIS current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
High level STAT_DIS current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Low level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Turn-On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Turn-Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
STAT_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
High level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Low level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Maximum turn-off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 25
PowerSSO-12 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Rthj-amb Vs. PCB copper area in open box free air condition (one channel on) . . . . . . . . 26
PowerSSO-12 thermal impedance junction ambient single pulse (one channel on) . . . . . 27
Thermal fitting model of a double channel HSD in PowerSSO-12 . . . . . . . . . . . . . . . . . . 27
PowerSSO-24 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Rthj-amb Vs. PCB copper area in open box free air condition (one channel on) . . . . . . . . 29
PowerSSO-24 thermal impedance junction ambient single pulse (one channel on) . . . . . 30
Thermal fitting model of a double channel HSD in PowerSSO-24 . . . . . . . . . . . . . . . . . . . 30
PowerSSO-12 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PowerSSO-24 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
PowerSSO-12 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
PowerSS0-24 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
PowerSSO-24 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Doc ID 14472 Rev 3
VND5E050K-E
Block diagram and pin description
Figure 1.
Block diagram
V CC
Signal Clamp
Undervoltage
IN1
Control & Diagnostic 1
Power
Clamp
DRIVER
IN2
CH 1
VON
Limitation
Over
temp.
Current
Limitation
OFF State
Open load
ST_
DIS
ON State
Open load
CONTROL & DIAGNOSTIC
Channels 2
1
Block diagram and pin description
CH 2
OUT2
ST1
ST2
OUT1
LOGIC
OVERLOAD PROTECTION
(ACTIVE POWER LIMITATION)
GND
Table 1.
Pin function
Name
VCC
OUTPUTn
GND
INPUTn
Function
Battery connection.
Power output.
Ground connection. Must be reverse battery protected by an external diode/resistor
network.
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
switch state.
STATUSn
Open drain digital diagnostic pin.
STAT_DIS
Active high CMOS compatible pin, to disable the STATUS pin.
Doc ID 14472 Rev 3
5/40
Block diagram and pin description
Figure 2.
VND5E050K-E
Configuration diagram (top view)
TAB = Vcc
GND
STAT_DIS
INPUT 1
STATUS 1
STATUS 2
INPUT 2
12
11
10
9
8
7
1
2
3
4
5
6
Vcc
OUTPUT 1
OUTPUT 1
OUTPUT 2
OUTPUT 2
Vcc
VCC
GND.
N.C.
STAT_DIS
INPUT1
STATUS1
N.C.
STATUS2
N.C.
INPUT2
N.C.
VCC
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
TAB = VCC
PowerSSO-12
Table 2.
6/40
PowerSSO-24
Suggested connections for unused and not connected pins
Connection / pin
Status
N.C.
Output
Input
STAT_DIS
Floating
X
X
X
X
X
To ground
Not allowed
X
Not allowed
Through 10KΩ
resistor
Through 10KΩ
resistor
Doc ID 14472 Rev 3
VND5E050K-E
2
Electrical specifications
Electrical specifications
Figure 3.
Current and voltage conventions
IS
VCC
VCC
VFn
ISD
IOUTn
STAT_DIS
OUTPUTn
VSD
VOUTn
IINn
ISTATn
INPUTn
STATUSn
VINn
VSTATn
GND
IGND
Note:
VFn = VOUTn - VCC during reverse battery condition.
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality document.
Table 3.
Absolute maximum ratings
Symbol
Value
Unit
DC supply voltage
41
V
- VCC
Reverse DC supply voltage
0.3
V
- IGND
DC reverse ground pin current
VCC
IOUT
- IOUT
Parameter
DC output current
Reverse DC output current
200
mA
Internally limited
A
15
A
IIN
DC input current
+10 / -1
mA
ISTAT
DC status current
+10 / -1
mA
+10 / -1
mA
104
mJ
ISTAT_DIS DC status disable current
EMAX
Maximum switching energy
(L=3 mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IOUT = IlimL(Typ.))
Doc ID 14472 Rev 3
7/40
Electrical specifications
Table 3.
VND5E050K-E
Absolute maximum ratings (continued)
Symbol
Value
Unit
VESD
Electrostatic discharge
(Human Body Model: R=1.5KΩ; C=100pF)
– Input
– Status
– STAT_DIS
– Output
– VCC
4000
4000
4000
5000
5000
V
V
V
V
V
VESD
Charge device model (CDM-AEC-Q100-011)
750
V
Tj
Tstg
2.2
Parameter
Junction operating temperature
-40 to 150
°C
Storage temperature
- 55 to 150
°C
Thermal data
Table 4.
Thermal data
Value
Symbol
8/40
Parameter
Rthj-case
Thermal resistance junction-case (max.)
(with one channel ON)
Rthj-amb
Thermal resistance junction-ambient
(max.)
Doc ID 14472 Rev 3
Unit
PowerSSO-12
PowerSSO-24
2.8
2.8
°C/W
See Figure 36
See Figure 40
°C/W
VND5E050K-E
2.3
Electrical specifications
Electrical characteristics
Values specified in this section are for 8 V<VCC<28 V; -40 °C<Tj<150 °C, unless otherwise
stated.
Table 5.
.
Power section
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VCC
Operating supply voltage
4.5
13
28
V
VUSD
Undervoltage shutdown
3.5
4.5
V
VUSDhyst
Undervoltage shutdown
hysteresis
0.5
On-state resistance(2)
IOUT=2A; Tj=25°C
IOUT=2A; Tj=150°C
IOUT=2A; VCC=5V; Tj=25°C
Clamp voltage
IS=20mA
IS
Supply current
Off-state; VCC=13V; Tj=25°C;
VIN=VOUT= 0V
On-state; VCC=13V; VIN=5V;
IOUT=0A
IL(off1)
Off-state output
current(2)
VIN=VOUT=0V; VCC=13V;
Tj=25°C
VIN=VOUT=0V; VCC=13V;
Tj=125°C
RON
Vclamp
VF
Output - VCC diode
voltage(2)
50
100
65
mΩ
mΩ
mΩ
46
52
V
2(1)
3
5(1)
6
µA
mA
0.01
3
41
0
V
0
µA
5
-IOUT=2 A; Tj=150°C
0.7
V
Max.
Unit
1. PowerMOS leakage included.
2. For each channel.
Table 6.
Symbol
Switching (VCC = 13V; Tj = 25°C)
Parameter
Test conditions
Min.
Typ.
td(on)
Turn- On delay time
RL= 6.5Ω (see Figure 6)
20
µs
td(off)
Turn- Off delay time
RL= 6.5Ω (see Figure 6)
40
µs
dVOUT/dt(on)
Turn- On voltage slope
RL= 6.5Ω
See
Figure 26
V/µs
dVOUT/dt(off)
Turn- Off voltage slope
RL= 6.5Ω
See
Figure 28
V/µs
WON
Switching energy
losses during twon
RL= 6.5Ω (see Figure 6)
0.21
mJ
WOFF
Switching energy
losses during twoff
RL= 6.5Ω (see Figure 6)
0.28
mJ
Doc ID 14472 Rev 3
9/40
Electrical specifications
Table 7.
Symbol
VND5E050K-E
Status pin (VSD=0V)
Parameter
Test conditions
Min.
Typ.
Max
Unit
VSTAT
Status low output
voltage
ISTAT=1.6 mA, VSD=0V
0.5
V
ILSTAT
Status leakage current
Normal Operation or VSD=5V,
VSTAT = 5V
10
µA
CSTAT
Status pin input
capacitance
Normal Operation or VSD=5V,
VSTAT = 5V
100
pF
VSCL
Status clamp voltage
ISTAT = 1mA
ISTAT = -1mA
7
V
V
Table 8.
Symbol
Parameter
Test conditions
DC short circuit current
VCC=13V;5V<VCC<28V
IlimL
Short circuit current
during thermal cycling
VCC=13V
TR<Tj<TTSD
TTSD
Shutdown temperature
TR
Reset temperature
TRS
Thermal reset of
STATUS
tSDL
VDEMAG
VON
-0.7
Protections (1)
IlimH
THYST
5.5
Min.
Typ.
Max.
Unit
19
27
38
38
A
A
7
150
175
TRS + 1
TRS + 5
A
200
°C
135
Thermal hysteresis
(TTSD-TR)
°C
7
Status delay in overload
conditions
Tj>TTSD (see Figure 4)
Turn-off output voltage
clamp
IOUT=2A; VIN=0; L=6mH
Output voltage drop
limitation
IOUT=0.1A;
Tj= -40°C...+150°C
(see Figure 5)
VCC-41
°C
VCC-46
°C
20
µs
VCC-52
V
25
mV
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.
Table 9.
Symbol
10/40
Openload detection (8V<VCC<18V)
Parameter
Test conditions
IOL
Openload on-state
detection threshold
VIN = 5V;
tDOL(on)
Openload on-state
detection delay
IOUT = 0A, VCC=13V
(see Figure 4)
Doc ID 14472 Rev 3
Min.
10
Typ.
Max.
Unit
70
mA
200
µs
VND5E050K-E
Electrical specifications
Table 9.
Openload detection (8V<VCC<18V) (continued)
Symbol
Parameter
tPOL
Delay between input
falling edge and status
rising edge in open-load
condition
IOUT = 0A (see Figure 4)
VOL
Openload off-state
voltage detection
threshold
VIN = 0V;
Output short circuit to
VCC detection delay at
turn-off
IL(off2)
td_vol
tDSTKON
Test conditions
Min.
Typ.
Max.
Unit
200
500
1200
µs
2
4
V
See Figure 4
180
tPOL
µs
Off-state output
current(1)
VIN= 0V; VOUT= 4V
(see Section 3.4: Open-load
detection in off-state)
-75
0
µA
Delay response from
output rising edge to
status falling edge in
open-load
VIN= 0V; VOUT= 4V
20
µs
Max.
Unit
0.9
V
1. For each channel.
Table 10.
Symbol
Logic input
Parameter
VIL
Input low level
IIL
Low level input current
VIH
Input high level
IIH
High level input current
VI(hyst)
Input hysteresis voltage
VIN =0.9 V
Input clamp voltage
VSDL
STAT_DIS low level voltage
ISDL
Low level STAT_DIS current
VSDH
STAT_DIS high level voltage
ISDH
High level STAT_DIS current
VSD(hyst)
STAT_DIS hysteresis voltage
Min.
Typ.
1
µA
2.1
V
VIN = 2.1 V
10
0.25
IIN = 1mA
IIN = -1mA
VICL
VSDCL
Test conditions
VSD = 0.9 V
5.5
V
Doc ID 14472 Rev 3
7
V
V
0.9
V
-0.7
1
µA
2.1
V
VSD = 2.1 V
STAT_DIS clamp voltage
10
0.25
ISD=1mA
ISD=-1mA
µA
µA
V
5.5
7
-0.7
V
V
11/40
Electrical specifications
Figure 4.
VND5E050K-E
Status timings
OPEN LOAD STATUS TIMING (without external pull-up)
IOUT < IOL
VIN
VOUT < VOL
OPEN LOAD STATUS TIMING (with external pull-up)
VOUT > VOL
VSTAT
VSTAT
tDOL(on)
tDOL(on)
tPOL
OVER TEMP STATUS TIMING
OUTPUT STUCK TO VCC
Tj > TTSD
IOUT > IOL
VIN
VOUT > VOL
VSTAT
VIN
VSTAT
tDOL(on)
Figure 5.
IOUT < IOL
VIN
tSDL
tDSTKON
tSDL
Output voltage drop limitation
Vcc-Vout
Tj=150oC
Tj=25oC
Tj=-40oC
Von
Von/Ron(T)
12/40
Doc ID 14472 Rev 3
Iout
VND5E050K-E
Electrical specifications
Figure 6.
Switching characteristics
VOUT
90%
80%
dVOUT/dt(off)
dVOUT/dt(on)
10%
tr
tf
t
INPUT
td(on)
td(off)
t
Table 11.
Truth table
Conditions
Input
Output
Sense (VCSD=0V)(1)
Normal operation
L
H
L
H
H
H
Over temperature
L
H
L
L
H
L
Undervoltage
L
H
L
L
X
X
Overload and
short circuit to GND
H
H
X
(no power limitation)
Cycling
(power limitation)
H
L
Output voltage > VOL
L
H
H
H
L(2)
H
Output current < IOL
L
H
L
H
H (3)
L
1. If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents
and external circuit.
2. The STATUS pin is low with a delay equal to tDSTKON after INPUT falling edge.
3. The STATUS pin becomes high with a delay equal to tPOL after INPUT falling edge.
Doc ID 14472 Rev 3
13/40
Electrical specifications
Table 12.
VND5E050K-E
Electrical transient requirements (part 1/3)
ISO 7637-2:
2004(E)
Test levels
test pulse
III
IV
Number of
pulses or
test times
1
-75V
-100V
5000 pulses
0.5 s
5s
2 ms, 10 Ω
2a
+37V
+50V
5000 pulses
0.2 s
5s
50 µs, 2 Ω
3a
-100V
-150V
1h
90 ms
100 ms
0.1 µs, 50 Ω
3b
+75V
+100V
1h
90 ms
100 ms
0.1 µs, 50 Ω
4
-6V
-7V
1 pulse
100 ms, 0.01 Ω
5b(1)
+65V
+87V
1 pulse
400 ms, 2 Ω
Burst cycle/pulse
repetition time
Delays and
Impedance
1. Valid in case of external load dump clamp: 40V maximum referred to ground.
Table 13.
Electrical transient requirements (part 2/3)
Test level results(1)
ISO 7637-2:
2004(E)
test pulse
III
IV
1
C
C
2a
C
C
3a
C
C
3b
C
C
4
C
C
5b(2)
C
C
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
Table 14.
14/40
Electrical transient requirements (part 3/3)
Class
Contents
C
All functions of the device are performed as designed after exposure to disturbance.
E
One or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
Doc ID 14472 Rev 3
VND5E050K-E
2.4
Electrical specifications
Waveforms
Figure 7.
Normal operation
Normal operation
INPUT
Nominal load
Nominal load
IOUT
VSTATUS
VST_DIS
Figure 8.
Undervoltage shutdown
Undervoltage shut-down
VCC
VUSD
VUSDhyst
INPUT
IOUT
UNDEFINED
VSTATUS
VST_DIS
Doc ID 14472 Rev 3
15/40
Electrical specifications
Figure 9.
VND5E050K-E
Overload or Short to GND
Overload or Short to GND
INPUT
ILimH >
Power Limitation
Thermal cycling
ILimL >
IOUT
VSTATUS
VST_DIS
Figure 10. Intermittent Overload
Intermittent Overload
INPUT
ILimH >
Overload
ILimL >
IOUT
VSTATUS
VST_DIS
16/40
Doc ID 14472 Rev 3
Nominal load
VND5E050K-E
Electrical specifications
Figure 11.
Open-load with external pull-up
Open Load
with external pull-up
INPUT
VOUT
VPU > VOL
VOL
IOUT
tDOL(on)
VSTATUS
VST_DIS
Figure 12. Open-load without external pull-up
Open Load
without external pull-up
INPUT
VOUT
IOUT < IOL
IOUT
IOL
tDOL(on)
VSTATUS
tPOL
VST_DIS
Doc ID 14472 Rev 3
17/40
Electrical specifications
VND5E050K-E
Figure 13. Short to VCC
Short to V CC
INPUT
Resistive
Short to VCC
Hard
Short to VCC
VOUT > VOL
VOUT > VOL
VOL
VOUT
IOUT > IOL
IOUT < IOL
IOL
IOUT
tDOL(on)
tDSTK(on)
VSTATUS
VST_DIS
Figure 14. TJ evolution in overload or short to GND
TJ evolution in
Overload or Short to GND
INPUT
Self-limitation of fast thermal transients
TTSD
THYST
TR
TJ_START
TJ
ILimH >
Power Limitation
< ILimL
IOUT
18/40
Doc ID 14472 Rev 3
VND5E050K-E
2.5
Electrical specifications
Electrical characteristics curves
Figure 15. Off-state output current
Figure 16. High level input current
Iloff (nA)
Iih (µA)
5
700
4,5
600
Vin=2.1V
Off State
Vcc=13V
Vin=Vout=0V
500
4
3,5
3
400
2,5
300
2
1,5
200
1
100
0,5
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
50
75
100
125
150
175
100
125
150
175
Tc (°C)
Figure 17. Input clamp voltage
Figure 18. Input high level
Vih (V)
Vicl (V)
4
7
6,8
3,5
lin=1mA
6,6
3
6,4
2,5
6,2
2
6
5,8
1,5
5,6
1
5,4
0,5
5,2
0
5
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
Tc (°C)
Tc (°C)
Figure 19. Input low level
Figure 20. Low level STAT_DIS current
Vil (V)
Isdl (µA)
2
5
1,8
4,5
1,6
4
1,4
3,5
Vsd= 0.9V
1,2
3
1
2,5
0,8
2
0,6
1,5
0,4
1
0,2
0,5
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
Tc (°C)
-25
0
25
50
75
100
125
150
175
Tc (°C)
Doc ID 14472 Rev 3
19/40
Electrical specifications
VND5E050K-E
Figure 21. On-state resistance vs Tcase
Figure 22. High level STAT_DIS current
Isdh (µA)
Ron (mOhm)
5
300
4,5
Vsd= 2.1V
Iout= 2A
Vcc=13V
250
4
3,5
200
3
2,5
150
2
100
1,5
1
50
0,5
0
0
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
100
125
150
175
150
175
150
175
Tc (°C)
Tc (°C)
Figure 23. On-state resistance vs VCC
Figure 24. Low level input current
Iil (µA)
Ron (mOhm)
5
100
4,5
Tc=150°C
Vin=0.9V
4
80
3,5
Tc=125°C
3
60
2,5
Tc=25°C
2
40
1,5
Tc=-40°C
1
20
0,5
0
0
0
5
10
15
20
25
30
35
40
-50
-25
0
25
50
75
100
125
Tc (°C)
Tc (°C)
Figure 25. ILIM vs Tcase
Figure 26. Turn-On voltage slope
Ilimh (A)
(dVout/dt )On (V/ms)
40
1000
900
35
Vcc=13V
Vcc=13V
RI=6.5 Ohm
800
700
30
600
25
500
400
20
300
200
15
100
10
0
-50
-25
0
25
50
75
100
125
150
Tc (°C)
20/40
-50
-25
0
25
50
75
Tc (°C)
Doc ID 14472 Rev 3
100
125
VND5E050K-E
Electrical specifications
Figure 27. Undervoltage shutdown
Figure 28. Turn-Off voltage slope
Vusd (V)
(dVout/dt )Off (V/ms)
8
600
550
7
Vcc=13V
RI= 6.5 Ohm
500
450
6
400
5
350
300
4
250
3
200
150
2
100
1
50
0
0
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (°C)
Figure 29. STAT_DIS clamp voltage
Figure 30. High level STAT_DIS voltage
VsdH(V)
Vsdcl(V)
4
10
9
3,5
Isd = 1 mA
8
3
7
2,5
6
2
5
4
1,5
3
1
2
0,5
1
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (°C)
Figure 31. Low level STAT_DIS voltage
VsdL(V)
3
2,5
2
1,5
1
0,5
0
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Doc ID 14472 Rev 3
21/40
Application information
3
VND5E050K-E
Application information
Figure 32. Application schematic
+5V
+5V
VCC
Rprot
STAT_DIS
Dld
Rprot
INPUT
μC
OUTPUT
Rprot
STATUS
GND
VGND
RGND
DGND
Note:
Channel 2 has the same internal circuit as channel 1.
3.1
GND protection network against reverse battery
3.1.1
Solution 1: resistor in the ground line (RGND only)
This can be used with any type of load.
The following is an indication on how to dimension the RGND resistor.
1.
RGND ≤ 600mV / (IS(on)max).
2.
RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power Dissipation in RGND (when VCC<0: during reverse battery situations) is:
PD= (-VCC)2/RGND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output
values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same RGND.
22/40
Doc ID 14472 Rev 3
VND5E050K-E
Application information
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).
3.1.2
Solution 2: diode (DGND) in the ground line
A resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
3.2
Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
VCC max DC rating. The same applies if the device is subject to transients on the VCC line
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
3.3
MCU I/Os protection
If a ground protection network is used and negative transient are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to
prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of µC µand the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os.
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHμC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
5kΩ ≤ Rprot ≤ 180kΩ.
Recommended values: Rprot =10kΩ.
Doc ID 14472 Rev 3
23/40
Application information
3.4
VND5E050K-E
Open-load detection in off-state
Off-state open-load detection requires an external pull-up resistor (RPU) connected between
output pin and a positive supply voltage (VPU) like the +5V line used to supply the
microprocessor.
The external resistor has to be selected according to the following requirements:
1.
no false open-load indication when load is connected: in this case we have to avoid
VOUT to be higher than VOlmin; this results in the following condition
VOUT=(VPU/(RL+RPU))RL<VOlmin.
2.
no misdetection when load is disconnected: in this case the VOUT has to be higher than
VOLmax; this results in the following condition RPU<(VPU–VOLmax)/IL(off2).
Because Is(OFF) may significantly increase if Vout is pulled high (up to several mA), the pullup resistor RPU should be connected to a supply that is switched OFF when the module is in
standby.
The values of VOLmin, VOLmax and IL(off2) are available in the Electrical Characteristics
section.
Figure 33. Open-load detection in off-state
V batt.
VPU
VCC
RPU
INPUT
DRIVER
+
LOGIC
IL(off2)
OUT
+
STATUS
R
VOL
GROUND
24/40
Doc ID 14472 Rev 3
RL
VND5E050K-E
3.5
Application information
Maximum demagnetization energy (VCC = 13.5V)
Figure 34. Maximum turn-off current versus inductance (for each channel)
100
A
B
C
I (A)
10
1
0,1
1
10
100
L (mH)
A: Tjstart = 150°C single pulse
B: Tjstart = 100°C repetitive pulse
C: Tjstart = 125°C repetitive pulse
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
Note:
Values are generated with RL = 0 Ω.
In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse
must not exceed the temperature specified above for curves A and B.
Doc ID 14472 Rev 3
25/40
Package and PCB thermal data
VND5E050K-E
4
Package and PCB thermal data
4.1
PowerSSO-12 thermal data
Figure 35. PowerSSO-12 PC board
Note:
Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4
area= 77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70μm (front and back side),
Copper areas: from minimum pad lay-out to 8cm2).
Figure 36. Rthj-amb Vs. PCB copper area in open box free air condition (one channel
on)
RTHj _amb( ° C/ W)
70
65
60
55
50
45
40
35
30
0
2
4
6
PCB Cu heat sink area ( cm^ 2)
26/40
Doc ID 14472 Rev 3
8
10
VND5E050K-E
Package and PCB thermal data
Figure 37. PowerSSO-12 thermal impedance junction ambient single pulse (one
channel on)
ZTH ( °C/ W)
100
Footprint
2 cm2
8 cm2
10
1
0,1
0,0001
0,001
0,01
0,1
1
Time ( s)
10
100
1000
Equation 1: pulse calculation formula
Z
THδ
= R
TH
⋅δ+Z
THtp
(1 – δ)
where δ = tP/T
Figure 38. Thermal fitting model of a double channel HSD in PowerSSO-12 (a)
a. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
Doc ID 14472 Rev 3
27/40
Package and PCB thermal data
Table 15.
28/40
VND5E050K-E
PowerSSO-12 thermal parameters
Area/island (cm2)
Footprint
R1= R7 (°C/W)
0.7
R2= R8 (°C/W)
2.8
R3 (°C/W)
4
R4 (°C/W)
2
8
8
8
7
R5 (°C/W)
22
15
10
R6 (°C/W)
26
20
15
C1= C7 (W.s/°C)
0.001
C2= C8 (W.s/°C)
0.0025
C3 (W.s/°C)
0.05
C4 (W.s/°C)
0.2
0.1
0.1
C5 (W.s/°C)
0.27
0.8
1
C6 (W.s/°C)
3
6
9
Doc ID 14472 Rev 3
VND5E050K-E
4.2
Package and PCB thermal data
PowerSSO-24 thermal data
Figure 39. PowerSSO-24 PC board
Note:
Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4
area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70µm (front and back side),
Copper areas: from minimum pad lay-out to 8cm2).
Figure 40. Rthj-amb Vs. PCB copper area in open box free air condition (one channel
on)
RTHj_amb(°C/W)
55
50
45
40
35
30
0
2
4
6
8
10
PCB Cu heatsink area (cm^2)
Doc ID 14472 Rev 3
29/40
Package and PCB thermal data
VND5E050K-E
Figure 41. PowerSSO-24 thermal impedance junction ambient single pulse (one
channel on)
Equation 2: pulse calculation formula
Z
THδ
= R
TH
⋅δ+Z
THtp
(1 – δ)
where δ = tP/T
Figure 42. Thermal fitting model of a double channel HSD in PowerSSO-24 (b)
b. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
30/40
Doc ID 14472 Rev 3
VND5E050K-E
Package and PCB thermal data
Table 16.
PowerSSO-24 thermal parameters
Area/island (cm2)
Footprint
R1=R7 (°C/W)
0.4
R2=R8 (°C/W)
2
R3 (°C/W)
6
R4 (°C/W)
7.7
R5 (°C/W)
2
8
9
9
8
R6 (°C/W)
28
17
10
C1=C7 (W.s/°C)
0.001
C2=C8 (W.s/°C)
0.0022
C3 (W.s/°C)
0.025
C4 (W.s/°C)
0.75
C5 (W.s/°C)
1
4
9
C6 (W.s/°C)
2.2
5
17
Doc ID 14472 Rev 3
31/40
Package and packing information
VND5E050K-E
5
Package and packing information
5.1
ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
5.2
PowerSSO-12 package information
Figure 43. PowerSSO-12 package dimensions
32/40
Doc ID 14472 Rev 3
VND5E050K-E
Package and packing information
Table 17.
PowerSSO-12 mechanical data
Symbol
Millimeters
Min.
Typ.
Max.
A
1.25
1.62
A1
0
0.1
A2
1.10
1.65
B
0.23
0.41
C
0.19
0.25
D
4.8
5.0
E
3.8
4.0
e
0.8
H
5.8
6.2
h
0.25
0.5
L
0.4
1.27
k
0°
8°
X
1.9
2.5
Y
3.6
4.2
ddd
0.1
Doc ID 14472 Rev 3
33/40
Package and packing information
5.3
VND5E050K-E
PowerSSO-24 package information
Figure 44. PowerSSO-24 package dimensions
34/40
Doc ID 14472 Rev 3
VND5E050K-E
Package and packing information
Table 18.
PowerSSO-24™ mechanical data
Millimeters
Symbol
Min
Typ
A
Max
2.45
A2
2.15
2.35
a1
0
0.1
b
0.33
0.51
c
0.23
0.32
D
10.10
10.50
E
7.4
7.6
e
0.8
e3
8.8
F
2.3
G
H
0.1
10.1
10.5
h
0.4
k
0°
8°
L
0.55
0.85
O
1.2
Q
0.8
S
2.9
T
3.65
U
1.0
N
10°
X
4.1
4.7
Y
6.5
7.1
Doc ID 14472 Rev 3
35/40
Package and packing information
5.4
VND5E050K-E
PowerSSO-12 packing information
Figure 45. PowerSSO-12 tube shipment (no suffix)
B
Base Q.ty
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
C
A
100
2000
532
1.85
6.75
0.6
All dimensions are in mm.
Figure 46. PowerSSO-12 tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
2500
2500
330
1.5
13
20.2
12.4
60
18.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (± 0.1)
P
D (± 0.05)
D1 (min)
F (± 0.1)
K (max)
P1 (± 0.1)
12
4
8
1.5
1.5
5.5
4.5
2
All dimensions are in mm.
End
Start
Top
cover
tape
No components
Components
Empty components pockets
saled with cover tape.
User direction of feed
36/40
Doc ID 14472 Rev 3
No components
500mm min
500mm min
VND5E050K-E
5.5
Package and packing information
PowerSSO-24 packing information
Figure 47. PowerSS0-24 tube shipment (no suffix)
C
Base Qty
Bulk Qty
Tube length (±0.5)
A
B
C (±0.1)
B
49
1225
532
3.5
13.8
0.6
All dimensions are in mm.
A
Figure 48. PowerSSO-24 tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Qty
Bulk Qty
A (max)
B (min)
C (± 0.2)
F
G (+2 / -0)
N (min)
T (max)
1000
1000
330
1.5
13
20.2
24.4
100
30.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (± 0.1)
P
D (± 0.05)
D1 (min)
F (± 0.1)
K (max)
P1 (± 0.1)
24
4
12
1.55
1.5
11.5
2.85
2
End
All dimensions are in mm.
Start
Top
cover
tape
No components Components
500mm min
No components
500mm min
Empty components pockets
sealed with cover tape.
User direction of feed
Doc ID 14472 Rev 3
37/40
Order codes
6
VND5E050K-E
Order codes
Table 19. Device summary
Package
38/40
Order codes
Tube
Tape and reel
PowerSSO-12
VND5E050J-E
VND5E050JTR-E
PowerSSO-24
VND5E050K-E
VND5E050KTR-E
Doc ID 14472 Rev 3
VND5E050K-E
7
Revision history
Revision history
Table 20.
Document revision history
Date
Revision
04-Feb-2008
1
Initial release.
2
Table 18: PowerSSO-24™ mechanical data:
– Deleted A (min) value
– Changed A (max) value from 2.47 to 2.45
– Changed A2 (max) value from 2.40 to 2.35
– Changed a1 (max) value from 0.075 to 0.1
– Added F row
– Updated k row
3
Updated Figure 44: PowerSSO-24 package dimensions.
Updated Table 18: PowerSSO-24™ mechanical data:
– Deleted G1 row
– Added O, Q, S, T and U rows
19-Jun-2009
22-Jul-2009
Changes
Doc ID 14472 Rev 3
39/40
VND5E050K-E
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2009 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
40/40
Doc ID 14472 Rev 3