RF1K49092 Data Sheet January 2002 3.5A/2.5A, 12V, 0.050/0.130 Ohm, Logic Level, Complementary LittleFET™ Power MOSFET Features This complementary power MOSFET is manufactured using an advanced MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. It is designed for use in applications such as switching regulators, switching converters, motor drivers, relay drivers, and low voltage bus switches. This product achieves full rated conduction at a gate bias in the 3V to 5V range, thereby facilitating true on-off power control directly from logic level (5V) integrated circuits. • rDS(ON) = 0.050Ω (N-Channel) rDS(ON) = 0.130Ω (P-Channel) • 3.5A, 12V (N-Channel) 2.5A, 12V (P-Channel) • Temperature Compensating PSPICE® Model • On-Resistance vs Gate Drive Voltage Curves • Peak Current vs Pulse Width Curve • UIS Rating Curve Formerly developmental type TA49092. • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Ordering Information Symbol PART NUMBER RF1K49092 PACKAGE MS-012AA BRAND D1 (8) D1 (7) RF1K49092 NOTE: When ordering, use the entire part number. For ordering in tape and reel, add the suffix 96 to the part number, i.e., RF1K4909296. S1 (1) G1 (2) D2 (6) D2 (5) S2 (3) G2 (4) Packaging JEDEC MS-012AA BRANDING DASH 5 1 2 3 ©2002 Fairchild Semiconductor Corporation 4 RF1K49092 Rev. B RF1K49092 Absolute Maximum Ratings TA = 25oC Unless Otherwise Specified N-CHANNEL P-CHANNEL UNITS Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . VDSS 12 -12 V Drain to Gate Voltage (RGS = 20kΩ, Note 1) . . . . . . . . .VDGR 12 -12 V Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±10 ±10 V Drain Current Continuous (Pulse Width = 5s). . . . . . . . . . . . . . . . . . . . . ID Pulsed (Figures 5, 26) . . . . . . . . . . . . . . . . . . . . . . . . . IDM 3.5 Refer to Peak Current Curve 2.5 Refer to Peak Current Curve A Pulsed Avalanche Rating (Figures 6, 27). . . . . . . . . . . . . EAS Refer to UIS Curve Refer to UIS Curve Power Dissipation TA = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0.016 2 0.016 W W/oC Operating and Storage Temperature . . . . . . . . . . . . TJ, TSTG -55 to 150 -55 to 150 oC Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . Tpkg 300 260 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. N-Channel Electrical Specifications PARAMETER TA = 25oC, Unless Otherwise Specified MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V, (Figure 13) 12 - - V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA, (Figure 12) Zero Gate Voltage Drain Current Gate to Source Leakage Current Drain to Source On Resistance Turn-On Time SYMBOL 1 - 2 V TA = 25o C - - 1 µA TA = 150o C - - 50 µA VGS = ±10V - - ±100 nA ID = 3.5A, VGS = 5V, (Figures 9, 11) - - 0.050 Ω VDD = 6V, ID ≈ 3.5A, RL = 1.71Ω, V GS = 5V, RGS = 25Ω (Figure 10) - - 100 ns - 18 - ns - 60 - ns td(OFF) - 50 - ns tf - 60 - ns tOFF - - 140 ns IDSS IGSS rDS(ON) tON Turn-On Delay Time Rise Time td(ON) tr Turn-Off Delay Time Fall Time Turn-Off Time TEST CONDITIONS VDS = 12V, VGS = 0V Total Gate Charge Qg(TOT) VGS = 0V to 10V Gate Charge at 5V Qg(5) VGS = 0V to 5V Qg(TH) VGS = 0V to 1V Threshold Gate Charge Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS Thermal Resistance Junction to Ambient RθJA VDD = 9.6V, ID = 3.5A, RL = 2.74Ω (Figure 15) VDS = 10V, VGS = 0V, f = 1MHz (Figure 14) - 20 25 nC - 12 15 nC - 0.9 1.2 nC - 750 - pF - 700 - pF - 275 - pF - - 62.5 oC/W MIN TYP MAX UNITS ISD = 3.5A - - 1.25 V ISD = 3.5A, dISD/dt = 100A/µs - - 70 ns Pulse width = 1s Device mounted on FR-4 material N-Channel Source to Drain Diode Specifications PARAMETER SYMBOL Source to Drain Voltage VSD Reverse Recovery Time trr ©2002 Fairchild Semiconductor Corporation TEST CONDITIONS RF1K49092 Rev. B RF1K49092 P-Channel Electrical Specifications PARAMETER TA = 25o C, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V, (Figure 34) -12 - - V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA, (Figure 33) Zero Gate Voltage Drain Current Gate to Source Leakage Current Drain to Source On Resistance Turn-On Time -1 - -2 V TA = 25o C - - -1 µA TA = 150o C - - -50 µA VGS = ±10V - - ±100 nA ID = 2.5A, VGS = -5V - - 0.130 Ω VDD = -6V, ID ≈ 2.5A, RL = 2.40Ω, V GS = -5V, RGS = 25Ω (Figure 31) - - 115 ns - 25 - ns - 65 - ns td(OFF) - 40 - ns tf - 45 - ns tOFF - - 110 ns - 19 24 nC - 10 14 nC - 0.8 1.1 nC - 775 - pF - 550 - pF - 150 - pF IDSS IGSS rDS(ON) tON Turn-On Delay Time Rise Time td(ON) tr Turn-Off Delay Time Fall Time Turn-Off Time VDS = -12V, VGS = 0V Total Gate Charge Qg(TOT) VGS = 0V to -10V Gate Charge at -5V Qg(-5) VGS = 0V to -5V Threshold Gate Charge Qg(TH) VGS = 0V to -1V Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS Thermal Resistance Junction-to-Ambient RθJA VDD = -9.6V, ID = 2.5A, RL = 3.84Ω (Figure 36) VDS = -10V, VGS = 0V, f = 1MHz (Figure 35) - - 62.5 oC/W MIN TYP MAX UNITS ISD = -2.5A - - -1.25 V ISD = -2.5A, dISD/dt = -100A/µs - - 55 ns Pulse width = 1s Device mounted on FR-4 material P-Channel Source to Drain Diode Specifications PARAMETER SYMBOL Source to Drain Voltage VSD Reverse Recovery Time trr TEST CONDITIONS Typical Performance Curves (N-Channel) 4.0 3.5 1.0 ID , DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 3.0 2.5 2.0 1.5 1.0 0.2 0.5 0.0 0 25 50 75 100 125 TA , AMBIENT TEMPERATURE (oC) 150 FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE ©2002 Fairchild Semiconductor Corporation 0.0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (oC) 150 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE RF1K49092 Rev. B RF1K49092 Typical Performance Curves (N-Channel) ZθJA, NORMALIZED THERMAL IMPEDANCE 10 1 (Continued) DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 0.1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE 0.01 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) 102 103 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE TJ = MAX RATED TA = 25oC VDSS MAX = 12V 10 5ms 10ms 1 100ms 1s 0.1 0.01 0.1 DC OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 200 IDM, PEAK CURRENT CAPABILITY (A) ID, DRAIN CURRENT (A) 100 100 I 125 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) ID , DRAIN CURRENT (A) 25 STARTING TJ = 25oC STARTING TJ = 150oC If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 1 0.1 101 VGS = 10V VGS = 5V VGS = 4.5V 20 VGS = 4V 15 10 VGS = 3V 5 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TA = 25oC 0 1 10 tAV, TIME IN AVALANCHE (ms) 10 0 FIGURE 5. PEAK CURRENT CAPABILITY 20 10 150 - TA 10 1 10-5 100 = I25 VGS = 5V FIGURE 4. FORWARD BIAS SAFE OPERATING AREA IAS, AVALANCHE CURRENT (A) TA = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 100 0 1 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V) 5 NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY ©2002 Fairchild Semiconductor Corporation FIGURE 7. SATURATION CHARACTERISTICS RF1K49092 Rev. B RF1K49092 Typical Performance Curves (N-Channel) (Continued) 250 25oC -55oC 20 VDD = 6V 150oC rDS(ON), ON-STATE RESISTANCE (mΩ) ID(ON), ON-STATE DRAIN CURRENT (A) 25 15 10 5 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 0 0.0 1.5 3.0 4.5 6.0 VGS, GATE TO SOURCE VOLTAGE (V) I D = 7.0A 200 150 I D = 3.5A I D = 1.75A 100 ID = 0.5A 50 0 2.5 7.5 FIGURE 8. TRANSFER CHARACTERISTICS 3.5 4.0 4.5 3.0 VGS, GATE TO SOURCE VOLTAGE (V) 5.0 FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 140 2.0 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 5V, ID = 3.5A 120 tr 100 t D(OFF) 80 60 tf 40 20 NORMALIZED ON RESISTANCE VDD = 6V, ID = 3.5A, RL = 1.71Ω SWITCHING TIME (ns) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = 10V 1.5 1.0 0.5 t D(ON) 0 0 20 10 30 40 50 0.0 -80 RGS, GATE TO SOURCE RESISTANCE (Ω) FIGURE 10. SWITCHING TIME vs GATE RESISTANCE 160 2.0 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250µA NORMALIZED GATE THRESHOLD VOLTAGE 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) FIGURE 11. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 2.0 1.5 1.0 0.5 0.0 -80 -40 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE ©2002 Fairchild Semiconductor Corporation ID = 250µA 1.5 1.0 0.5 0.0 -80 -40 0 40 80 120 TJ , JUNCTION TEMPERATURE (oC) 160 FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE RF1K49092 Rev. B RF1K49092 (Continued) 12 CISS VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD 900 VDS , DRAIN-SOURCE VOLTAGE (V) C, CAPACITANCE (pF) 1200 COSS 600 CRSS 300 5.00 VDD = BVDSS VDD = BVDSS 3.75 9 6 2.50 0.75 BVDSS 0.50 BVDSS 0.25 BVDSS 3 1.25 RL = 3.43Ω IG(REF) = 0.6mA VGS = 5V 0.00 0 I 0 0 2 4 6 8 I G ( REF ) 20 ---------------------I G ( ACT ) 10 VDS, DRAIN TO SOURCE VOLTAGE (V) VGS , GATE-SOURCE VOLTAGE (V) Typical Performance Curves (N-Channel) G ( REF ) 80 ---------------------I G ( ACT ) t, TIME (µs) NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms (N-Channel) VDS BVDSS L tP VARY tP TO OBTAIN REQUIRED PEAK IAS + RG VDS IAS VDD VDD - VGS DUT tP 0V IAS 0 0.01Ω tAV FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 17. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) td(OFF) tr VDS RL + RG DUT VDD tf 90% 90% 10% 0 10% 90% VGS 0 10% 50% 50% PULSE WIDTH VGS FIGURE 18. SWITCHING TIME TEST CIRCUIT ©2002 Fairchild Semiconductor Corporation FIGURE 19. RESISTIVE SWITCHING WAVEFORMS RF1K49092 Rev. B RF1K49092 Test Circuits and Waveforms (N-Channel) (Continued) VDS (ISOLATED SUPPLY) CURRENT REGULATOR VDD 12V BATTERY 0.2µF Qg(TOT) SAME TYPE AS DUT 50kΩ VDS VGS = 10V 0.3µF Qg(5) D VGS = 5V VGS G DUT VGS = 1V 0 Ig(REF) Qg(TH) S 0 IG CURRENT SAMPLING RESISTOR VDS ID CURRENT SAMPLING RESISTOR Ig(REF) 0 FIGURE 20. GATE CHARGE TEST CIRCUIT FIGURE 21. GATE CHARGE WAVEFORMS 1.2 -3.0 1.0 -2.5 ID , DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER Typical Performance Curves (P-Channel) 0.8 0.6 0.4 -1.5 -1.0 -0.5 0.2 0 -2.0 0 25 50 75 100 TA , AMBIENT TEMPERATURE (oC) 125 150 FIGURE 22. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE ZθJA, NORMALIZED THERMAL RESPONSE 10 1 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (oC) 150 FIGURE 23. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.1 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE 0.01 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) 102 103 FIGURE 24. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE ©2002 Fairchild Semiconductor Corporation RF1K49092 Rev. B RF1K49092 ID, DRAIN CURRENT (A) -100 (Continued) TJ = MAX RATED, TA = 25oC, VDSS(MAX) = -12V -10 5ms 10ms -1 100ms 1s DC -0.1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) -0.01 -0.1 -1 -10 -200 IDM, PEAK CURRENT CAPABILITY (A) Typical Performance Curves (P-Channel) TA = 25oC -100 I VGS = -10V 125 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10-4 10-3 VDS, DRAIN TO SOURCE VOLTAGE (V) 10-1 100 101 FIGURE 26. PEAK CURRENT CAPABILITY -20 -25 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TA = 25oC VGS = -10V -10 I D, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) 10-2 t, PULSE WIDTH (s) FIGURE 25. FORWARD BIAS SAFE OPERATING AREA STARTING TJ = 25oC STARTING TJ = 150oC If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BV DSS - VDD) +1] -1 0.1 150 - TA = I25 VGS = -5V -10 -1 10-5 -100 FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: -20 VGS = -5V -15 VGS = -4.5V -10 VGS = -4V -5 0 1 10 tAV, TIME IN AVALANCHE (ms) 100 VGS = -3V 0 -1 -2 -3 -4 -5 VDS, DRAIN TO SOURCE VOLTAGE (V) NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 27. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY -20 500 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = -6V rDS(ON), ON-STATE RESISTANCE (mΩ) ID(ON), ON-STATE DRAIN CURRENT (A) -25 150oC - 55oC 25oC -15 -10 -5 0 0.0 -1.5 -3.0 -4.5 -6.0 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 29. TRANSFER CHARACTERISTICS ©2002 Fairchild Semiconductor Corporation FIGURE 28. SATURATION CHARACTERISTICS -7.5 ID = -2.5A ID = -6.0A 400 I D = -1.5A 300 200 I D = -0.5A 100 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = -10V 0 -2.5 -3.0 -3.5 -4.0 -4.5 VGS, GATE TO SOURCE VOLTAGE (V) -5.0 FIGURE 30. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT RF1K49092 Rev. B RF1K49092 Typical Performance Curves (P-Channel) (Continued) 120 tr 80 tf 60 tD(OFF) 40 tD(ON) 20 1.5 1.0 0.5 0 0 20 10 30 40 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = -5V, ID = -2.5A 0 -80 50 -40 RGS, GATE TO SOURCE RESISTANCE (Ω) FIGURE 31. SWITCHING TIME AS A FUNCTION OF GATE RESISTANCE 2.0 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE NORMALIZED GATE THRESHOLD VOLTAGE VGS = VDS, ID = -250µA 1.5 1.0 0.5 -40 0 40 80 120 1.5 1.0 0.5 -40 0 40 80 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD COSS 600 CRSS 300 VDS , DRAIN-SOURCE VOLTAGE (V) CISS 900 -5.00 VDD = BVDSS VDD = BVDSS -3.75 -9 -6 -2.50 0.75 BVDSS 0.50 BVDSS 0.25 BVDSS -3 -1.25 RL = 3.84Ω IG(REF) = -0.5mA VGS = -5V 0.00 0 I G ( REF ) 0 -2 -4 -6 -8 VDS, DRAIN TO SOURCE VOLTAGE (V) -10 FIGURE 35. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE ©2002 Fairchild Semiconductor Corporation 160 FIGURE 34. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE -12 1200 120 TJ , JUNCTION TEMPERATURE (oC) FIGURE 33. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE C, CAPACITANCE (pF) ID = -250µA 0.0 -80 160 TJ, JUNCTION TEMPERATURE (oC) 0 160 FIGURE 32. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 2.0 0.0 -80 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) VGS , GATE-SOURCE VOLTAGE (V) SWITCHING TIME (ns) 100 NORMALIZED ON RESISTANCE 2.0 VDD = -6V, ID = -2.5A, RL = 2.40Ω 20 ---------------------I G ( ACT ) t, TIME (µs) I G ( REF ) 80 ---------------------I G ( ACT ) NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 36. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT RF1K49092 Rev. B RF1K49092 Test Circuits and Waveforms (P-Channel) VDS tAV L 0 VARY tP TO OBTAIN - RG REQUIRED PEAK IAS + VDD DUT 0V VDD tP VGS IAS IAS VDS tP 0.01Ω BVDSS FIGURE 37. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 38. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(OFF) td(ON) tf tr 0 RL - DUT VGS VDS VDD RG + 10% 10% 90% 90% VGS 0 10% 50% 50% PULSE WIDTH 90% FIGURE 39. SWITCHING TIME TEST CIRCUIT FIGURE 40. RESISTIVE SWITCHING WAVEFORMS -VDS (ISOLATED SUPPLY) CURRENT REGULATOR VDS Qg(TH) 0 DUT 12V BATTERY 0.2µF VGS= -1V 50kΩ 0.3µF VGS= -5V -VGS Qg(-5) D DUT G 0 Qg(TOT) S Ig(REF) IG CURRENT SAMPLING RESISTOR +VDS ID CURRENT SAMPLING RESISTOR FIGURE 41. GATE CHARGE TEST CIRCUIT ©2002 Fairchild Semiconductor Corporation VGS= -10V VDD 0 Ig(REF) FIGURE 42. GATE CHARGE WAVEFORMS RF1K49092 Rev. B RF1K49092 Soldering Precautions 1. The soldering process creates a considerable thermal stress on any semiconductor component. The melting temperature of solder is higher than the maximum rated temperature of the device. The amount of time the device is heated to a high temperature should be minimized to assure device reliability. Therefore, the following precautions should always be observed in order to minimize the thermal stress to which the devices are subjected. 2. Always preheat the device. 3. The delta temperature between the preheat and soldering should always be less than 100oC. Failure to preheat the device can result in excessive thermal stress which can damage the device. ©2002 Fairchild Semiconductor Corporation 4. The maximum temperature gradient should be less than 5oC per second when changing from preheating to soldering. 5. The peak temperature in the soldering process should be at least 30 oC higher than the melting point of the solder chosen. 6. The maximum soldering temperature and time must not exceed 260oC for 10 seconds on the leads and case of the device. 7. After soldering is complete, the device should be allowed to cool naturally for at least three minutes, as forced cooling will increase the temperature gradient and may result in latent failure due to mechanical stress. 8. During cooling, mechanical stress or shock should be avoided. RF1K49092 Rev. B RF1K49092 PSPICE Electrical Model SUBCKT RF1K49092 2 1 3; N-Channel Model rev 9/6/94 CA 12 8 9.77e-10 CB 15 14 9.19e-10 CIN 6 8 7.81e-10 DPLCAP 5 10 DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD DBREAK RDRAIN EBREAK 11 7 17 18 14.89 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 IT 8 17 1 ESG + GATE 1 9 16 EBREAK VTO + 21 MOS2 CIN 8 S1A 12 DBODY MOS1 RIN MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 + 17 18 6 8 LDRAIN 2 5 1e-9 LGATE 1 9 1.233e-9 LSOURCE 3 7 0.452e-9 S1A S1B S2A S2B 11 6 8 EVTO 20 + 18 LGATE RGATE RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 4.91e-3 RGATE 9 20 2.74 RIN 6 8 1e9 RSOURCE 8 7 RDSMOD 5e-3 RVTO 18 19 RVTOMOD 1 DRAIN 2 LDRAIN RSOURCE 7 LSOURCE 3 SOURCE S2A 13 8 S1B RBREAK 15 14 13 17 18 S2B RVTO 13 CA CB + EGS 6 8 EDS + 14 5 8 IT 19 VBAT + 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 0.3215 .MODEL DBDMOD D (IS = 7.00e-13 RS = 2.15e-2 TRS1 = 0.5e-3 TRS2 = 3.68e-6 CJO = 1.28e-9 TT = 1.8e-8) .MODEL DBKMOD D (RS = 1.28e-1 TRS1 = 1.69e-3 TRS2 = -2.0e-6) .MODEL DPLCAPMOD D (CJO = 0.84e-9 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 1.6 3KP = 11.5 5IS = 1e-3 0N = 1 0TOX = 1L = 1 uW = 1u) .MODEL RBKMOD RES (TC1 = 9.15e- 4TC2 = 3.13e-7) .MODEL RDSMOD RES (TC1 = 7.00e-4 TC2 = 5.00e-6) .MODEL RVTOMOD RES (TC1 = -2.155e- 3TC2 = -2.7e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.05 VOFF= -4.05) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.05 VOFF= -6.05) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.72 VOFF= 4.28) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 4.28 VOFF= -0.72) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991. ©2002 Fairchild Semiconductor Corporation RF1K49092 Rev. B RF1K49092 PSPICE Electrical Model SUBCKT RF1K49092 2 1 3 ;P-Channel Model rev 10/24/94 CA 12 8 8.75e-10 CB 15 14 8.65e-10 CIN 6 8 7.65e-10 DPLCAP 5 10 DBODY 5 7 DBDMOD DBREAK 7 11 DBKMOD DPLCAP 10 5 DPLCAPMOD RDRAIN EBREAK 5 11 17 18 -23.75 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 8 6 1 EVTO 20 6 8 18 1 IT 8 17 1 ESG + GATE 1 MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 7.36e-3 RGATE 9 20 6.1 RIN 6 8 1e9 RSOURCE 8 7 RDSMOD 4.56e-2 RVTO 18 19 RVTOMOD 1 EBREAK 17 18 16 VTO + 21 MOS2 11 6 MOS1 RIN DBREAK CIN 8 RSOURCE 7 LSOURCE 3 SOURCE S2A S1A 12 DBODY + 6 8 EVTO 9 20 + 18 8 LGATE RGATE LDRAIN 2 5 1e-9 LGATE 1 9 1.233e-9 LSOURCE 3 7 0.452e-9 S1A S1B S2A S2B DRAIN 2 LDRAIN 13 8 S1B RBREAK 15 14 13 17 18 S2B RVTO 13 CA CB + EGS 14 + 6 8 EDS 5 8 IT 19 VBAT + 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 -0.558 .MODEL DBDMOD D (IS = 3.0e-13 RS = 4.4e-2 TRS1 = 1.0e-3 TRS2 = -7.37e-6 CJO = 1.27e-9 TT = 2.2e-8) .MODEL DBKMOD D (RS = 7.84e-2 TRS1 = -4.27e-3 TRS2 = 5.77e-5) .MODEL DPLCAPMOD D (CJO = 2.85e-10 IS = 1e-30 N = 10) .MODEL MOSMOD PMOS (VTO = -2.1423 KP = 9.206 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 9.61e- 4TC2 = -1.09e-6) .MODEL RDSMOD RES (TC1 = 2.10e-3 TC2 = 6.99e-6) .MODEL RVTOMOD RES (TC1 = -1.82e- 3TC2 = 1.47e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 5.47 VOFF= 3.47) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 3.47 VOFF= 5.47) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.05 VOFF= -3.95) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.95 VOFF= 1.05) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991. ©2002 Fairchild Semiconductor Corporation RF1K49092 Rev. B TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DenseTrench™ DOME™ EcoSPARK™ E2CMOSTM EnSignaTM FACT™ FACT Quiet Series™ FAST FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench QFET™ QS™ QT Optoelectronics™ Quiet Series™ SILENT SWITCHER SMART START™ STAR*POWER™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™ UltraFET VCX™ STAR*POWER is used under license DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4