TLC7528C, TLC7528E, TLC7528I DUAL 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS SLAS062B – JANUARY 1987 – REVISED MARCH 2000 D D D D D D D DW OR N PACKAGE (TOP VIEW) Easily Interfaced to Microprocessors On-Chip Data Latches Monotonic Over the Entire A/D Conversion Range Interchangeable With Analog Devices AD7528 and PMI PM-7528 Fast Control Signaling for Digital Signal Processor (DSP) Applications Including Interface With TMS320 Voltage-Mode Operation CMOS Technology AGND OUTA RFBA REFA DGND DACA/DACB (MSB) DB7 DB6 DB5 DB4 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 OUTB RFBB REFB VDD WR CS DB0 (LSB) DB1 DB2 DB3 KEY PERFORMANCE SPECIFICATIONS FN PACKAGE (TOP VIEW) 8 bits 1/2 LSB 20 mW 100 ns 80 ns description RFBA OUTA AGND OUTB RFBB Resolution Linearity Error Power Dissipation at VDD = 5 V Settling Time at VDD = 5 V Propagation Delay Time at VDD = 5 V REFA DGND DACA/DACB (MSB) DB7 DB6 4 3 2 1 20 19 18 5 17 REFB VDD WR CS DB0 (LSB) DB5 DB4 DB3 DB2 DB1 The TLC7528C, TLC7528E, and TLC7528I are 16 6 dual, 8-bit, digital-to-analog converters designed 15 7 with separate on-chip data latches and feature 14 8 exceptionally close DAC-to-DAC matching. Data 9 10 11 12 13 is transferred to either of the two DAC data latches through a common, 8-bit, input port. Control input DACA/DACB determines which DAC is to be loaded. The load cycle of these devices is similar to the write cycle of a random-access memory, allowing easy interface to most popular microprocessor buses and output ports. Segmenting the high-order bits minimizes glitches during changes in the most significant bits, where glitch impulse is typically the strongest. These devices operate from a 5-V to 15-V power supply and dissipates less than 15 mW (typical). The 2- or 4-quadrant multiplying makes these devices a sound choice for many microprocessor-controlled gain-setting and signal-control applications. It can be operated in voltage mode, which produces a voltage output rather than a current output. Refer to the typical application information in this data sheet. The TLC7528C is characterized for operation from 0°C to 70°C. The TLC7528I is characterized for operation from – 25°C to 85°C. The TLC7528E is characterized for operation from – 40°C to 85°C. AVAILABLE OPTIONS PACKAGE TA SMALL OUTLINE (DW) CHIP CARRIER (FN) PLASTIC DIP (N) 0°C to 70°C TLC7528CDW TLC7528CFN TLC7528CN – 25°C to 85°C TLC7528IDW TLC7528IFN TLC7528IN – 40°C to 85°C TLC7528EDW TLC7528EFN TLC7528EN Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TLC7528C, TLC7528E, TLC7528I DUAL 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS SLAS062B – JANUARY 1987 – REVISED MARCH 2000 functional block diagram DB0 14 REFA 13 12 8 11 Data Inputs Input Buffer 10 Latch A 9 8 DB7 DACA/DACB WR CS ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 8 RFBA 2 OUTA DACA 1 AGND 7 8 6 16 Logic Control 15 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Latch B 8 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ DACB 18 REFB operating sequence tsu(CS) th(CS) tsu(DAC) th(DAC) CS DACA/DACB tw(WR) WR tsu(D) Data In Stable DB0 – DB7 2 3 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 th(D) 19 20 RFBB OUTB TLC7528C, TLC7528E, TLC7528I DUAL 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS SLAS062B – JANUARY 1987 – REVISED MARCH 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VDD (to AGND or DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 16.5 V Voltage between AGND and DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VDD Input voltage range, VI (to DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 Reference voltage, VrefA or VrefB (to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V Feedback voltage VRFBA or VRFBB (to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V Input voltage (voltage mode out A, out B to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 Output voltage, VOA or VOB (to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V Peak input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 µA Operating free-air temperature range, TA: TLC7528C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C TLC7528I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 25°C to 85°C TLC7528E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Case temperature for 10 seconds, TC: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions VDD = 4.75 V to 5.25 V MIN NOM MAX VDD = 14.5 V to 15.5 V MIN NOM MAX ± 10 Reference voltage, VrefA or VrefB High-level input voltage, VIH ± 10 2.4 Low-level input voltage, VIL V 13.5 0.8 CS setup time, tsu(CS) UNIT V 1.5 V 50 50 ns 0 0 ns DAC select setup time, tsu(DAC) 50 50 ns DAC select hold time, th(DAC) 10 10 ns Data bus input setup time tsu(D) 25 25 ns Data bus input hold time th(D) 10 10 ns Pulse duration, WR low, tw(WR) 50 50 ns CS hold time, th(CS) TLC7628C Operating free-air temperature, TA 0 70 0 70 TLC7628I – 25 85 – 25 85 TLC7628E – 40 85 – 40 85 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 °C 3 TLC7528C, TLC7528E, TLC7528I DUAL 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS SLAS062B – JANUARY 1987 – REVISED MARCH 2000 electrical characteristics over recommended operating free-air temperature range, VrefA = VrefB = 10 V, VOA and VOB at 0 V (unless otherwise noted) PARAMETER IIH IIL TEST CONDITIONS High-level input current VI = VDD VI = 0 Low-level input current VDD = 5 V MIN TYP† MAX µA µA 20 20 kΩ 5 12 DAC data latch loaded with 00000000, VrefA = ± 10 V ± 400 ± 200 OUTB DAC data latch loaded with 00000000, VrefB = ± 10 V ± 400 ± 200 ± 1% ± 1% 0.04 0.02 %/% 2 2 mA 0.5 0.5 mA DB0–DB7 10 10 pF WR, CS, DACA/DACB 15 15 pF DAC data latches loaded with 00000000 50 50 DAC data latches loaded with 11111111 120 120 Output leakage current DC supply sensitivity, ∆gain/∆VDD IDD Supply current (quiescent) IDD Supply current (standby) Ci Input capacitance ∆VDD = ± 10% All digital inputs at VIHmin or VILmax All digital inputs at 0 V or VDD (OUTA OUTB) Output capacitance (OUTA, † All typical values are at TA = 25°C. 4 10 – 10 OUTA Input resistance match (REFA to REFB) Co 12 UNIT – 10 10 5 Reference input impedance REFA or REFB to AGND IIkg Ik VDD = 15 V MIN TYP† MAX POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 nA pF TLC7528C, TLC7528E, TLC7528I DUAL 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS SLAS062B – JANUARY 1987 – REVISED MARCH 2000 operating characteristics over recommended operating free-air temperature range, VrefA = VrefB = 10 V, VOA and VOB at 0 V (unless otherwise noted) PARAMETER TEST CONDITIONS VDD = 5 V MIN TYP MAX VDD = 15 V MIN TYP MAX UNIT ± 1/2 ± 1/2 LSB 100 100 ns LSB Linearity error Settling time (to 1/2 LSB) See Note 1 Gain error See Note 2 AC feedthrough REFA to OUTA REFB to OUTB See Note 3 2.5 2.5 – 65 – 65 – 65 – 65 Temperature coefficient of gain See Note 4 0.007 Propagation delay (from digital input to 90% of final analog output current) See Note 5 80 Channel-to-channel isolation dB 0.0035 %FSR/°C 80 REFA to OUTB See Note 6 77 77 REFB to OUTA See Note 7 77 77 ns dB Digital-to-analog glitch impulse area Measured for code transition from 00000000 to 11111111, TA = 25°C 160 440 nV•s Digital crosstalk Measured for code transition from 00000000 to 11111111, TA = 25°C 30 60 nV•s Harmonic distortion NOTES: 1. 2. 3. 4. 5. 6. 7. Vi = 6 V, f = 1 kHz, TA = 25°C – 85 – 85 dB OUTA, OUTB load = 100 Ω, Cext = 13 pF; WR and CS at 0 V; DB0–DB7 at 0 V to VDD or VDD to 0 V. Gain error is measured using an internal feedback resistor. Nominal full scale range (FSR) = Vref – 1 LSB. Vref = 20 V peak-to-peak, 100-kHz sine wave; DAC data latches loaded with 00000000. Temperature coefficient of gain measured from 0°C to 25°C or from 25°C to 70°C. VrefA = VrefB = 10 V; OUTA/OUTB load = 100 Ω, Cext = 13 pF; WR and CS at 0 V; DB0–DB7 at 0 V to VDD or VDD to 0 V. Both DAC latches loaded with 11111111; VrefA = 20 V peak-to-peak, 100-kHz sine wave; VrefB = 0; TA = 25°C. Both DAC latches loaded with 11111111; VrefB = 20 V peak-to-peak, 100-kHz sine wave; VrefA = 0; TA = 25°C. PRINCIPLES OF OPERATION These devices contain two identical, 8-bit-multiplying D/A converters, DACA and DACB. Each DAC consists of an inverted R-2R ladder, analog switches, and input data latches. Binary-weighted currents are switched between DAC output and AGND, thus maintaining a constant current in each ladder leg independent of the switch state. Most applications require only the addition of an external operational amplifier and voltage reference. A simplified D/A circuit for DACA with all digital inputs low is shown in Figure 1. Figure 2 shows the DACA equivalent circuit. A similar equivalent circuit can be drawn for DACB. Both DACs share the analog ground terminal 1 (AGND). With all digital inputs high, the entire reference current flows to OUTA. A small leakage current (IIkg) flows across internal junctions, and as with most semiconductor devices, doubles every 10°C. Co is due to the parallel combination of the NMOS switches and has a value that depends on the number of switches connected to the output. The range of Co is 50 pF to 120 pF maximum. The equivalent output resistance (ro) varies with the input code from 0.8R to 3R where R is the nominal value of the ladder resistor in the R-2R network. These devices interface to a microprocessor through the data bus, CS, WR, and DACA/DACB control signals. When CS and WR are both low, the TLC7528 analog output, specified by the DACA/DACB control line, responds to the activity on the DB0–DB7 data bus inputs. In this mode, the input latches are transparent and input data directly affects the analog output. When either the CS signal or WR signal goes high, the data on the DB0–DB7 inputs is latched until the CS and WR signals go low again. When CS is high, the data inputs are disabled regardless of the state of the WR signal. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TLC7528C, TLC7528E, TLC7528I DUAL 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS SLAS062B – JANUARY 1987 – REVISED MARCH 2000 PRINCIPLES OF OPERATION The digital inputs of these devices provide TTL compatibility when operated from a supply voltage of 5 V. These devices can operate with any supply voltage in the range from 5 V to 15 V; however, input logic levels are not TTL compatible above 5 V. R R R REFA 2R 2R 2R 2R 2R RFB S2 S1 S3 RFBA S8 OUTA AGND DACA Data Latches and Drivers Figure 1. Simplified Functional Circuit for DACA RFBA RFB R OUTA REFA I 256 COUT IIkg AGND Figure 2. TLC7528 Equivalent Circuit, DACA Latch Loaded With 11111111 MODE SELECTION TABLE DACA/DACB CS WR DACA DACB L H X X L L H X L L X H Write Hold Hold Hold Hold Write Hold Hold L = low level, 6 H = high level, POST OFFICE BOX 655303 X = don’t care • DALLAS, TEXAS 75265 TLC7528C, TLC7528E, TLC7528I DUAL 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS SLAS062B – JANUARY 1987 – REVISED MARCH 2000 APPLICATION INFORMATION These devices are capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for 2-quadrant and 4-quadrant multiplication are shown in Figures 3 and 4. Tables 1 and 2 summarize input coding for unipolar and bipolar operation. VI(A) ± 10 V R1 (see Note A) RFBA OUTA 8 Latch VOA AGND Latch RECOMMENDED TRIM RESISTOR VALUES R1, R3 R2, R4 500 Ω 150 Ω ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ R4 (see Note A) OUTB 8 DACB C2 (see Note B) + Control Logic ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ RFBB – 8 6 CS 16 WR 5 DGND DACA + Input Buffer 7 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ REFA 8 DB7 DACA / DACB C1 (see Note B) – 17 VDD 14 DB0 R2 (see Note A) VOB AGND REFB AGND R3 (see Note A) VI(B) ± 10 V NOTES: A. R1, R2, R3, and R4 are used only if gain adjustment is required. See table for recommended values. Make gain adjustment with digital input of 255. B. C1 and C2 phase compensation capacitors (10 pF to 15 pF) are required when using high-speed amplifiers to prevent ringing or oscillation. Figure 3. Unipolar Operation (2-Quadrant Multiplication) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TLC7528C, TLC7528E, TLC7528I DUAL 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS SLAS062B – JANUARY 1987 – REVISED MARCH 2000 APPLICATION INFORMATION VI(A) ± 10 V R6 20 kΩ (see Note B) R1 (see Note A) DACA/ DACB 15 CS 16 WR 5 DGND OUTA 8 DACA RFBB Latch DACB REFB AGND R8 20 kΩ A3 AGND VOA R11 5 kΩ R4 (see Note A) OUTB 8 – A2 + (see Note B) C2 (see Note C) Control Logic 8 A1 AGND + 6 Latch R9 10 kΩ (see Note B) R3 (see Note A) A4 + 7 8 – Input Buffer R5 20 kΩ R7 10 kΩ – DB7 ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ C1 (see Note C) + DB0 17 14 R2 (see Note A) – VDD RFBA VOB R11 5 kΩ AGND R10 20 kΩ (see Note B) VI(B) ± 10 V NOTES: A. R1, R2, R3, and R4 are used only if gain adjustment is required. See table in Figure 3 for recommended values. Adjust R1 for VOA = 0 V with code 10000000 in DACA latch. Adjust R3 for VOB = 0 V with 10000000 in DACB latch. B. Matching and tracking are essential for resistor pairs R6, R7, R9, and R10. C. C1 and C2 phase compensation capacitors (10 pF to 15 pF) may be required if A1 and A3 are high-speed amplifiers. Figure 4. Bipolar Operation (4-Quadrant Operation) Table 1. Unipolar Binary Code DAC LATCH CONTENTS MSB LSB† ANALOG OUTPUT DAC LATCH CONTENTS MSB LSB‡ ANALOG OUTPUT 11111111 10000001 10000000 01111111 00000001 00000000 –VI (255/256) –VI (129/256) –VI (128/256) = – Vi/2 – VI (127/256) – VI (1/256) – VI (0/256) = 0 11111111 10000001 10000000 01111111 00000001 00000000 VI (127/128) VI (1/128) 0V – VI (1/128) – VI (127/128) – VI (128/128) † 1 LSB = (2–8)VI 8 Table 2. Bipolar (Offset Binary) Code ‡ 1 LSB = (2–7)VI POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC7528C, TLC7528E, TLC7528I DUAL 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS SLAS062B – JANUARY 1987 – REVISED MARCH 2000 APPLICATION INFORMATION microprocessor interface information 8 Address Bus A8 – A15 DACA/DACB Address Decode Logic CPU 8051 A CS A+1 WR TLC7528 DB0 WR DB7 ALE Latch 8 Data Bus AD0 – AD7 NOTE A: A = decoded address for TLC7528 DACA A + 1 = decoded address for TLC7528 DACB Figure 5. TLC7528 – Intel 8051 Interface 8 Address Bus A8 – A15 DACA/DACB VMA CPU 6800 Address Decode Logic A CS A+1 WR TLC7528 DB0 φ2 DB7 8 AD0 – AD7 Data Bus NOTE A: A = decoded address for TLC7528 DACA A + 1 = decoded address for TLC7528 DACB Figure 6. TLC7528 – 6800 Interface POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TLC7528C, TLC7528E, TLC7528I DUAL 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS SLAS062B – JANUARY 1987 – REVISED MARCH 2000 APPLICATION INFORMATION 8 Address Bus A8 – A15 DACA/DACB Address Decode Logic IORQ A CS TLC7528 WR A+1 CPU Z80-A DB0 DB7 WR 8 Data Bus D0 – D7 NOTE A: A = decoded address for TLC7528 DACA A + 1 = decoded address for TLC7528 DACB Figure 7. TLC7528 To Z-80A Interface programmable window detector The programmable window comparator shown in Figure 8 determines if voltage applied to the DAC feedback resistors are within the limits programmed into the data latches of these devices. Input signal range depends on the reference and polarity, that is, the test input range is 0 to –Vref. The DACA and DACB data latches are programmed with the upper and lower test limits. A signal within the programmed limits drives the output high. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC7528C, TLC7528E, TLC7528I DUAL 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS SLAS062B – JANUARY 1987 – REVISED MARCH 2000 APPLICATION INFORMATION VCC VDD Test Input 0 to –Vref 3 17 RFBA 1 kΩ OUTA – 4 2 DACA REFA + 8 14 – 7 Data Inputs DB0 – DB7 TLC7528 15 16 6 CS 1 WR DACA / DACB OUTB DACB + 5 20 – 18 REFB Vref PASS / FAIL Output AGND DGND RFBB 19 Figure 8. Digitally-Programmable Window Comparator (Upper- and Lower-Limit Tester) digitally controlled signal attenuator Figure 9 shows a TLC7528 configured as a two-channel programmable attenuator. Applications include stereo audio and telephone signal level control. Table 3 shows input codes vs attenuation for a 0 to 15.5 dB range. Attenuation dB = – 20 log10 D/256, D = digital input code VDD 17 4 VIA REFA RFBA 3 OUTA 2 DACA A1 DB0 – DB7 TLC7528 CS WR 20 VOB DACA / DACB OUTB DACB A2 REFB AGND RFBB DGND 14 – 7 Output 8 Data Bus 15 16 6 18 1 5 19 Figure 9. Digitally Controlled Dual Telephone Attenuator POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TLC7528C, TLC7528E, TLC7528I DUAL 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS SLAS062B – JANUARY 1987 – REVISED MARCH 2000 APPLICATION INFORMATION Table 3. Attenuation vs DACA, DACB Code ATTN (dB) DAC INPUT CODE CODE IN DECIMAL ATTN (dB) DAC INPUT CODE CODE IN DECIMAL 0 11111111 255 8.0 01100110 102 0.5 11110010 242 8.5 01100000 96 1.0 11100100 228 9.0 01011011 91 1.5 11010111 215 9.5 01010110 86 2.0 11001011 203 10.0 01010001 81 2.5 11000000 192 10.5 01001100 76 3.0 10110101 181 11.0 01001000 72 3.5 10101011 171 11.5 01000100 68 4.0 10100010 162 12.0 01000000 64 4.5 10011000 152 12.5 00111101 61 5.0 10011111 144 13.0 00111001 57 5.5 10001000 136 13.5 00110110 54 6.0 10000000 128 14.0 00110011 51 6.5 01111001 121 14.5 00110000 48 7.0 01110010 114 15.0 00101110 46 7.5 01101100 108 15.5 00101011 43 programmable state-variable filter This programmable state-variable or universal filter configuration provides low-pass, high-pass, and bandpass outputs, and is suitable for applications requiring microprocessor control of filter parameters. As shown in Figure 10, DACA1 and DACB1 control the gain and Q of the filter while DACA2 and DACB2 control the cutoff frequency. Both halves of the DACA2 and DACB2 must track accurately in order for the cutoff-frequency equation to be true. With the TLC7528, this is easy to achieve. fc 1 + 2p R1C1 The programmable range for the cutoff or center frequency is 0 to 15 kHz with a Q ranging from 0.3 to 4.5. This defines the limits of the component values. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC7528C, TLC7528E, TLC7528I DUAL 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS SLAS062B – JANUARY 1987 – REVISED MARCH 2000 APPLICATION INFORMATION C3 47 pF 15 16 5 6 RFBA DB0 – DB7 TLC7528 AGND 3 30 kΩ A1 R4 1 30 kΩ R3 CS OUTB DACB (RF) WR R5 RFBB DGND 20 A2 10 kΩ + VDD 8 14 – 7 Data In DACA (RS) – 17 2 + VI OUTA REFA – 4 19 High Pass Out REFB 18 DACA / DACB Bandpass Out DACA1 AND DACB1 C1 1000 pF 15 16 5 6 RFBA DB0 – DB7 TLC7528 C2 AGND 1 OUTB 20 1000 pF CS DACB (R2) WR A3 3 RFBB DGND 19 A4 Low Pass Out + Data In VDD 2 – 8 14 – 7 OUTA DACA (R1) + 17 REFA – 4 REFB 18 DACA / DACB DACA2 and DACB2 Circuit Equations: C1 = C2, R1 = R2, R4 = R5 Q + RR3 4 R · R F fb(DACB1) Where: R is the internal resistor connected between OUTB and RFBB fb R G – F R S NOTES: A. Op-amps A1, A2, A3, and A4 are TL287. B. CS compensates for the op-amp gain-bandwidth limitations. 256 (DAC ladder resistance) C. DAC equivalent resistance equals DAC digital code + Figure 10. Digitally Controlled State-Variable Filter POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TLC7528C, TLC7528E, TLC7528I DUAL 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS SLAS062B – JANUARY 1987 – REVISED MARCH 2000 APPLICATION INFORMATION voltage-mode operation It is possible to operate the current multiplying D/A converter of these devices in a voltage mode. In the voltage mode, a fixed voltage is placed on the current output terminal. The analog output voltage is then available at the reference voltage terminal. Figure 11 is an example of a current multiplying D/A, that operates in the voltage mode. R R R REF (Analog Output Voltage) 2R 2R 2R “0” 2R “1” R Out (Fixed Input Voltage) AGND Figure 11. Voltage-Mode Operation The following equation shows the relationship between the fixed input voltage and the analog output voltage: VO = VI (D/256) Where: VO = analog output voltage VI = fixed input voltage (must not be forced below 0 V.) D = digital input code converted to decimal In voltage-mode operation, these devices meet the following specification: PARAMETER Linearity error at REFA or REFB 14 TEST CONDITIONS VDD = 5 V, POST OFFICE BOX 655303 OUTA or OUTB at 2.5 V, • DALLAS, TEXAS 75265 MIN TA = 25°C MAX UNIT 1 LSB TLC7528C, TLC7528E, TLC7528I DUAL 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS SLAS062B – JANUARY 1987 – REVISED MARCH 2000 MECHANICAL DATA DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 16 PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 16 0.010 (0,25) M 9 0.419 (10,65) 0.400 (10,15) 0.010 (0,25) NOM 0.299 (7,59) 0.291 (7,39) Gage Plane 0.010 (0,25) 1 8 0°– 8° A 0.050 (1,27) 0.016 (0,40) Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) PINS ** 0.004 (0,10) 16 20 24 28 A MAX 0.410 (10,41) 0.510 (12,95) 0.610 (15,49) 0.710 (18,03) A MIN 0.400 (10,16) 0.500 (12,70) 0.600 (15,24) 0.700 (17,78) DIM 4040000 / D 01/00 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TLC7528C, TLC7528E, TLC7528I DUAL 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS SLAS062B – JANUARY 1987 – REVISED MARCH 2000 MECHANICAL DATA N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE 16 PINS SHOWN PINS ** 14 16 18 20 A MAX 0.775 (19,69) 0.775 (19,69) 0.920 (23,37) 0.975 (24,77) A MIN 0.745 (18,92) 0.745 (18,92) 0.850 (21,59) 0.940 (23,88) DIM A 16 9 0.260 (6,60) 0.240 (6,10) 1 8 0.070 (1,78) MAX 0.035 (0,89) MAX 0.325 (8,26) 0.300 (7,62) 0.020 (0,51) MIN 0.015 (0,38) Gauge Plane 0.200 (5,08) MAX Seating Plane 0.010 (0,25) NOM 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.430 (10,92) MAX 0.010 (0,25) M 14/18 PIN ONLY 4040049/D 02/00 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 (20-pin package is shorter than MS-001). 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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