TI TLC1543CN

TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
10-Bit Resolution A/D Converter
11 Analog Input Channels
Three Built-In Self-Test Modes
Inherent Sample-and-Hold Function
Total Unadjusted Error . . . ± 1 LSB Max
On-Chip System Clock
End-of-Conversion (EOC) Output
Terminal Compatible With TLC542
CMOS Technology
DB, DW, J, OR N PACKAGE
(TOP VIEW)
A0
A1
A2
A3
A4
A5
A6
A7
A8
GND
description
In addition to a high-speed A /D converter and versatile
control capability, these devices have an on-chip
14-channel multiplexer that can select any one of 11
analog inputs or any one of three internal self-test
voltages. The sample-and-hold function is automatic.
At the end of A /D conversion, the end-of-conversion
(EOC) output goes high to indicate that conversion is
complete. The converter incorporated in the devices
features differential high-impedance reference inputs
that facilitate ratiometric conversion, scaling, and
isolation of analog circuitry from logic and supply noise.
A switched-capacitor design allows low-error conversion over the full operating free-air temperature range.
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
EOC
I/O CLOCK
ADDRESS
DATA OUT
CS
REF +
REF –
A10
A9
FK OR FN PACKAGE
(TOP VIEW)
A2
A1
A0
VCC
EOC
The TLC1542C, TLC1542I, TLC1542M, TLC1542Q,
TLC1543C, TLC1543I, and TLC1543Q are CMOS
10-bit switched-capacitor successive-approximation
analog-to-digital converters. These devices have three
inputs and a 3-state output [chip select (CS),
input-output clock (I/O CLOCK), address input
(ADDRESS), and data output (DATA OUT)] that
provide a direct 4-wire interface to the serial port of a
host processor. These devices allow high-speed data
transfers from the host.
1
A3
A4
A5
A6
A7
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
I/O CLOCK
ADDRESS
DATA OUT
CS
REF +
A8
GND
A9
A10
REF –
D
D
D
D
D
D
D
D
D
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
AVAILABLE OPTIONS
PACKAGE
SMALL
OUTLINE
(DB)
TA
0°C to 70°C
SMALL OUTLINE
(DW)
CHIP CARRIER
(FN)
PLASTIC DIP
(N)
TLC1542CDW
TLC1542CFN
TLC1542CN
TLC1543CDW
TLC1543CFN
TLC1543CN
TLC1542IDW
TLC1542IFN
TLC1542IN
TLC1543IDB
TLC1543IDW
TLC1543IFN
TLC1543IN
TLC1542QDB
TLC1542QDW
TLC1542QFN
TLC1542QN
TLC1543QDB
TLC1543QDW
TLC1543QFN
TLC1543QN
TLC1543CDB
– 40°C to 85°C
– 40°C to 125°C
CHIP CARRIER
(FK)
CERAMIC DIP
(J)
TLC1542MFK
TLC1542MJ
– 55°C to 125°C
functional block diagram
REF+
14
REF –
13
1
A0
2
A1
3
4
A2
A3
5
6
7
A4
A5
A6
8
9
A7
A8
A9
10
14-Channel
Analog
Multiplexer
11
4
12
A10
10-Bit
Analog-to-Digital
Converter
(switched capacitors)
Sample and
Hold
Output
Data
Register
Input Address
Register
10
10-to-1 Data
Selector and
Driver
16 DATA
OUT
4
3
System
Clock,
Control Logic,
and I/O
Counters
Self-Test
Reference
ADDRESS
I/O CLOCK
CS
17
19
EOC
18
15
typical equivalent inputs
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE
1 kΩ TYP
INPUT CIRCUIT IMPEDANCE DURING HOLD MODE
A0 – A10
A0 – A10
Ci = 60 pF TYP
(equivalent input
capacitance)
2
POST OFFICE BOX 655303
5 MΩ TYP
• DALLAS, TEXAS 75265
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
Terminal Functions
TERMINAL
I/O
DESCRIPTION
17
I
Serial address input. A 4-bit serial address selects the desired analog input or test voltage that is to
be converted next. The address data is presented with the MSB first and shifts in on the first four rising
edges of I/O CLOCK. After the four address bits have been read into the address register, this input
is ignored for the remainder of the current conversion period.
1 – 9, 11, 12
I
Analog signal inputs. The 11 analog inputs are applied to these terminals and are internally multiplexed.
The driving source impedance should be less than or equal to 1 kΩ.
CS
15
I
Chip select. A high-to-low transition on this input resets the internal counters and controls and enables
DATA OUT, ADDRESS, and I/O CLOCK within a maximum of a setup time plus two falling edges of
the internal system clock. A low-to-high transition disables ADDRESS and I/O CLOCK within a setup
time plus two falling edges of the internal system clock.
DATA OUT
16
O
The 3-state serial output for the A/D conversion result. This output is in the high-impedance state when
CS is high and active when CS is low. With a valid chip select, DATA OUT is removed from the
high-impedance state and is driven to the logic level corresponding to the MSB value of the previous
conversion result. The next falling edge of I/O CLOCK drives this output to the logic level corresponding
to the next most significant bit, and the remaining bits shift out in order with the LSB appearing on the
ninth falling edge of I/O CLOCK. On the tenth falling edge of I/O CLOCK, DATA OUT is driven to a low
logic level so that serial interface data transfers of more than ten clocks produce zeroes as the unused
LSBs.
EOC
19
O
End of conversion. This output goes from a high to a low logic level on the trailing edge of the tenth I/O
CLOCK and remains low until the conversion is complete and data are ready for transfer.
GND
10
I
The ground return terminal for the internal circuitry. Unless otherwise noted, all voltage measurements
are with respect to this terminal.
I/O CLOCK
18
I
Input/output clock. This terminal receives the serial I/O CLOCK input and performs the following four
functions:
1) It clocks the four input address bits into the address register on the first four rising edges of the I/O
CLOCK with the multiplex address available after the fourth rising edge.
2) On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplex input
begins charging the capacitor array and continues to do so until the tenth falling edge of
I/O CLOCK.
3) It shifts the nine remaining bits of the previous conversion data out on DATA OUT.
4) It transfers control of the conversion to the internal state controller on the falling edge of the tenth
clock.
REF +
14
I
The upper reference voltage value (nominally VCC) is applied to this terminal. The maximum input
voltage range is determined by the difference between the voltage applied to this terminal and the
voltage applied to the REF – terminal.
REF –
13
I
The lower reference voltage value (nominally ground) is applied to this terminal.
VCC
20
I
Positive supply voltage
NAME
ADDRESS
A0 – A10
NO.
detailed description
With chip select (CS) inactive (high), the ADDRESS and I/O CLOCK inputs are initially disabled and DATA OUT
is in the high-impedance state. When the serial interface takes CS active (low), the conversion sequence begins
with the enabling of I/O CLOCK and ADDRESS and the removal of DATA OUT from the high-impedance state.
The serial interface then provides the 4-bit channel address to ADDRESS and the I/O CLOCK sequence to I/O
CLOCK. During this transfer, the serial interface also receives the previous conversion result from DATA OUT.
I/O CLOCK receives an input sequence that is between 10 and 16 clocks long from the host serial interface.
The first four I/O clocks load the address register with the 4-bit address on ADDRESS, selecting the desired
analog channel, and the next six clocks providing the control timing for sampling the analog input.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
detailed description (continued)
There are six basic serial-interface timing modes that can be used with the device. These modes are determined
by the speed of I/O CLOCK and the operation of CS as shown in Table 1. These modes are (1) a fast mode with
a 10-clock transfer and CS inactive (high) between conversion cycles, (2) a fast mode with a 10-clock transfer
and CS active (low) continuously, (3) a fast mode with an 11- to 16-clock transfer and CS inactive (high) between
conversion cycles, (4) a fast mode with a 16-clock transfer and CS active (low) continuously, (5) a slow mode
with an 11- to 16-clock transfer and CS inactive (high) between conversion cycles, and (6) a slow mode with
a 16-clock transfer and CS active (low) continuously.
The MSB of the previous conversion appears at DATA OUT on the falling edge of CS in mode 1, mode 3, and
mode 5, on the rising edge of EOC in mode 2 and mode 4, and following the sixteenth clock falling edge in
mode 6. The remaining nine bits are shifted out on the next nine falling edges of I/O CLOCK. Ten bits of data
are transmitted to the host-serial interface through DATA OUT. The number of serial clock pulses used also
depends on the mode of operation, but a minimum of ten clock pulses is required for conversion to begin. On
the tenth clock falling edge, the EOC output goes low and returns to the high logic level when conversion is
complete and the result can be read by the host. Also, on the tenth clock falling edge, the internal logic takes
DATA OUT low to ensure that the remaining bit values are zero when the I/O CLOCK transfer is more than ten
clocks long.
Table 1 lists the operational modes with respect to the state of CS, the number of I/O serial transfer clocks that
can be used, and the timing edge on which the MSB of the previous conversion appears at the output.
Table 1. Mode Operation
MODES
Fast Modes
Slow Modes
NO. OF
I/O CLOCKS
CS
MSB AT DATA OUT †
TIMING
DIAGRAM
Mode 1
High between conversion cycles
10
CS falling edge
Figure 9
Mode 2
Low continuously
10
EOC rising edge
Figure 10
Mode 3
High between conversion cycles
CS falling edge
Figure 11
Mode 4
Low continuously
11 to 16‡
16‡
EOC rising edge
Figure 12
Mode 5
High between conversion cycles
CS falling edge
Figure 13
Mode 6
Low continuously
11 to 16‡
16‡
16th clock falling edge
Figure 14
† These edges also initiate serial-interface communication.
‡ No more than 16 clocks should be used.
fast modes
The device is in a fast mode when the serial I/O CLOCK data transfer is completed before the conversion is
completed. With a 10-clock serial transfer, the device can only run in a fast mode since a conversion does not
begin until the falling edge of the tenth I/O CLOCK.
mode 1: fast mode, CS inactive (high) between conversion cycles, 10-clock transfer
In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer is ten clocks long. The
falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge
of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time.
Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time plus two falling
edges of the internal system clock.
mode 2: fast mode, CS active (low) continuously, 10-clock transfer
In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer is ten clocks long. After
the initial conversion cycle, CS is held active (low) for subsequent conversions; the rising edge of EOC then
begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the previous
conversion to appear immediately on this output.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
mode 3: fast mode, CS inactive (high) between conversion cycles, 11- to 16-clock transfer
In this mode, CS is inactive (high) between serial I/O CLOCK transfers, and each transfer can be 11 to 16 clocks
long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The
rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified
delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time
plus two falling edges of the internal system clock.
mode 4: fast mode, CS active (low) continuously, 16-clock transfer
In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks
long. After the initial conversion cycle, CS is held active (low) for subsequent conversions; the rising edge of
EOC then begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the
previous conversion to appear immediately on this output.
slow modes
In a slow mode, the conversion is completed before the serial I/O CLOCK data transfer is completed. A slow
mode requires a minimum 11-clock transfer into I/O CLOCK, and the rising edge of the eleventh clock must
occur before the conversion period is complete; otherwise, the device loses synchronization with the host-serial
interface and CS has to be toggled to initialize the system. The eleventh rising edge of the I/O CLOCK must
occur within 9.5 µs after the tenth I/O clock falling edge.
mode 5: slow mode, CS inactive (high) between conversion cycles, 11- to 16-clock transfer
In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 11 to 16 clocks
long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The
rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified
delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time
plus two falling edges of the internal system clock.
mode 6: slow mode, CS active (low) continuously, 16-clock transfer
In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks
long. After the initial conversion cycle, CS is held active (low) for subsequent conversions. The falling edge of
the sixteenth I/O CLOCK then begins each sequence by removing DATA OUT from the low state, allowing the
MSB of the previous conversion to appear immediately at DATA OUT. The device is then ready for the next
16-clock transfer initiated by the serial interface.
address bits
The 4-bit analog channel-select address for the next conversion cycle is presented to the ADDRESS terminal
(MSB first) and is clocked into the address register on the first four leading edges of I/O CLOCK. This address
selects one of 14 inputs (11 analog inputs or three internal test inputs).
analog inputs and test modes
The 11 analog inputs and the three internal test inputs are selected by the 14-channel multiplexer according
to the input address as shown in Tables 2 and 3. The input multiplexer is a break-before-make type to reduce
input-to-input noise injection resulting from channel switching.
Sampling of the analog input starts on the falling edge of the fourth I/O CLOCK, and sampling continues for six
I/O CLOCK periods. The sample is held on the falling edge of the tenth I/O CLOCK. The three test inputs are
applied to the multiplexer, sampled, and converted in the same manner as the external analog inputs.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
analog inputs and test modes (continued)
Table 2. Analog-Channel-Select Address
ANALOG INPUT
SELECTED
VALUE SHIFTED INTO
ADDRESS INPUT
BINARY
HEX
A0
0000
0
A1
0001
1
A2
0010
2
A3
0011
3
A4
0100
4
A5
0101
5
A6
0110
6
A7
0111
7
A8
1000
8
A9
1001
9
A10
1010
A
Table 3. Test-Mode-Select Address
INTERNAL
SELF-TEST
VOLTAGE
SELECTED†
Vref+ – Vref–
2
VALUE SHIFTED INTO
ADDRESS INPUT
BINARY
HEX
1011
B
OUTPUT RESULT (HEX)‡
200
Vref–
1100
C
000
Vref+
1101
D
3FF
† Vref+ is the voltage applied to the REF+ input, and Vref– is the voltage applied to the REF–
input.
‡ The output results shown are the ideal values and vary with the reference stability and
with internal offsets.
converter and analog input
The CMOS threshold detector in the successive-approximation conversion system determines each bit by
examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the
conversion process, the analog input is sampled by closing the SC switch and all ST switches simultaneously.
This action charges all the capacitors to the input voltage.
In the next phase of the conversion process, all ST and SC switches are opened and the threshold detector
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF –)
voltage. In the switching sequence, ten capacitors are examined separately until all ten bits are identified and
then the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector
looks at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the REF+ voltage, and the
equivalent nodes of all the other capacitors on the ladder are switched to REF –. If the voltage at the summing
node is greater than the trip point of the threshold detector (approximately one-half VCC ), a 0 bit is placed in
the output register and the 512-weight capacitor is switched to REF –. If the voltage at the summing node is less
than the trip point of the threshold detector, a 1 bit is placed in the register and the 512-weight capacitor remains
connected to REF + through the remainder of the successive-approximation process. The process is repeated
for the 256-weight capacitor, the 128-weight capacitor, and so forth down the line until all bits are counted.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
converter and analog input (continued)
With each step of the successive-approximation process, the initial charge is redistributed among the
capacitors. The conversion process relies on charge redistribution to count and weigh the bits from MSB to LSB.
SC
Threshold
Detector
512
Node 512
REF –
256
128
REF+
REF+
REF –
ST
REF –
ST
16
8
REF+
REF –
ST
4
REF+
REF –
ST
REF+
REF –
ST
2
1
REF+
REF+
REF –
ST
REF –
ST
To Output
Latches
1
REF –
ST
ST
VI
Figure 1. Simplified Model of the Successive-Approximation System
chip-select operation
The trailing edge of CS starts all modes of operation, and CS can abort a conversion sequence in any mode.
A high-to-low transition on CS within the specified time during an ongoing cycle aborts the cycle, and the device
returns to the initial state (the contents of the output data register remain at the previous conversion result).
Exercise care to prevent CS from being taken low close to completion of conversion because the output data
can be corrupted.
reference voltage inputs
There are two reference inputs used with the device: REF + and REF –. These voltage values establish the upper
and lower limits of the analog input to produce a full-scale and zero reading respectively. The values of REF +,
REF–, and the analog input should not exceed the positive supply or be lower than GND consistent with the
specified absolute maximum ratings. The digital output is at full scale when the input signal is equal to or higher
than REF + and at zero when the input signal is equal to or lower than REF –.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6.5 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.3 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.3 V
Positive reference voltage, Vref+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.1 V
Negative reference voltage, Vref– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.1 V
Peak input current (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Peak total input current (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 30 mA
Operating free-air temperature range, TA: TLC1542C, TLC1543C . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
TLC1542I, TLC1543I . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
TLC1542Q, TLC1543Q . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C
TLC1542M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to digital ground with REF – and GND wired together (unless otherwise noted).
recommended operating conditions
Supply voltage, VCC
MIN
NOM
MAX
4.5
5
5.5
Positive reference voltage, Vref + (see Note 2)
VCC
0
Negative reference voltage, Vref – (see Note 2)
Differential reference voltage, Vref + – Vref – (see Note 2)
2.5
Analog input voltage (see Note 2)
High-level control input voltage, VIH
Low-level control input voltage, VIL
0
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
VCC
V
V
V
VCC + 0.2
VCC
2
V
V
V
0.8
Setup time, address bits at data input before I/O CLOCK↑, tsu(A) (see Figure 4)
UNIT
V
100
ns
Hold time, address bits after I/O CLOCK↑, th(A) (see Figure 4)
0
ns
Hold time, CS low after last I/O CLOCK↓, th(CS) (see Figure 5)
0
ns
1.425
µs
Setup time, CS low before clocking in first address bit, tsu(CS) (see Note 3 and Figure 5)
Clock frequency at I/O CLOCK (see Note 4)
0
Pulse duration, I/O CLOCK high, twH(I/O)
190
Pulse duration, I/O CLOCK low, twL(I/O)
190
Transition time, I/O CLOCK, tt(I/O) (see Note 5 and Figure 6)
Transition time, ADDRESS and CS, tt(CS)
TLC1542C, TLC1543C
Operating free-air
free air temperature,
temperature TA
2.1
MHz
ns
ns
1
µs
10
µs
0
70
TLC1542I, TLC1543I
– 40
85
TLC1542Q, TLC1543Q
– 40
125
TLC1542M
– 55
125
°C
NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied
to REF– convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (Vref + – Vref – ); however,
the electrical specifications are no longer applicable.
3. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the
minimum CS setup time has elapsed.
4. For 11- to 16-bit transfers, after the tenth I/O CLOCK falling edge (≤ 2 V) at least 1 I/O CLOCK rising edge (≥ 2 V) must occur within
9.5 µs.
5. This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of
normal room temperature, the devices function with input clock transition time as slow as 1 µs for remote data-acquisition
applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
electrical characteristics over recommended operating free-air temperature range,
VCC = Vref+ = 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
VOH
High level output voltage
High-level
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
IOH = –1.6 mA
IOH = – 20 µA
VOL
Low level output voltage
Low-level
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
IOL = 1.6 mA
IOL = 20 µA
0.4
Off-state
(high impedance state)
(high-impedance-state)
output current
VO = VCC,
CS at VCC
10
IOZ
VO = 0,
CS at VCC
– 10
IIH
IIL
High-level input current
Low-level input current
VI = VCC
VI = 0
ICC
Operating supply current
CS at 0 V
Selected channel leakage
current TLC1542/TLC1543
C, I, or Q
Selected channel at VCC,
Unselected channel at 0 V
Selected channel at 0 V,
Unselected channel at VCC
Selected channel at VCC,
TA = 25°C
Unselected channel at 0 V,
Selected channel at 0 V,
TA = 25°C
Unselected channel at VCC,
Selected channel at VCC,
Unselected channel at 0 V
Selected channel at 0 V,
Unselected channel at VCC
Vref + = VCC,
Vref – = GND
Selected channel leakage
current TLC1542M
Maximum static analog
reference current into REF +
Ci
Input
capacitance
2.4
UNIT
V
VCC – 0.1
0.1
V
µA
0.005
2.5
µA
– 0.005
– 2.5
µA
0.8
2.5
mA
1
µA
–1
1
–1
µA
2.5
– 2.5
10
Analog inputs
7
Control inputs
5
µA
pF
† All typical values are at VCC = 5 V, TA = 25°C.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
operating characteristics over recommended operating free-air temperature range,
VCC = Vref+ = 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz (unless otherwise noted)
TEST CONDITIONS
EL
EZS
EFS
Linearity error (see Note 6)
Zero-scale error (see Note 7)
Full-scale error (see Note 7)
Total unadjusted error (see Note 8)
MIN
TYP†
MAX
UNIT
TLC1542C, I, or Q
± 0.5
LSB
TLC1543C, I, or Q
±1
LSB
TLC1542M
±1
LSB
TLC1542C, I, or Q
See Note 2
±1
LSB
TLC1543C, I, or Q
See Note 2
±1
LSB
TLC1542M
See Note 2
±1
LSB
TLC1542C, I, or Q
See Note 2
±1
LSB
TLC1543C, I, or Q
See Note 2
±1
LSB
TLC1542M
See Note 2
±1
LSB
TLC1542C, I, or Q
±1
LSB
TLC1543C, I, or Q
±1
LSB
±1
LSB
TLC1542M
Self-test output code (see Table 3 and Note 9)
ADDRESS = 1011
512
ADDRESS = 1100
0
ADDRESS = 1101
1023
tconv
Conversion time
See timing diagrams
21
µs
tc
Total cycle time (access, sample, and conversion)
See timing diagrams
and Note 10
21
+10 I/O
CLOCK
periods
µs
tacq
Channel acquisition time (sample)
See timing diagrams
and Note 10
tv
td(I/O-DATA)
Valid time, DATA OUT remains valid after I/O CLOCK↓
See Figure 6
Delay time, I/O CLOCK↓ to DATA OUT valid
See Figure 6
6
10
I/O
CLOCK
periods
ns
240
ns
td(I/O-EOC)
Delay time, tenth I/O CLOCK↓ to EOC↓
See Figure 7
70
240
ns
td(EOC-DATA) Delay time, EOC↑ to DATA OUT (MSB)
See Figure 8
100
ns
† All typical values are at TA = 25°C.
NOTES: 2. Analog input voltages greater than that applied to REF + convert as all ones (1111111111), while input voltages less than that applied
to REF – convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (Vref + – Vref – ); however,
the electrical specifications are no longer applicable.
6. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
7. Zero-scale error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the
difference between 1111111111 and the converted output for full-scale input voltage.
8. Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
9. Both the input address and the output codes are expressed in positive logic.
10. I/O CLOCK period = 1/(I/O CLOCK frequency) (see Figure 6)
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
operating characteristics over recommended operating free-air temperature range,
VCC = Vref+ = 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz (unless otherwise noted) (continued)
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
tPZH, tPZL
tPHZ, tPLZ
Enable time, CS↓ to DATA OUT (MSB driven)
See Figure 3
1.3
µs
Disable time, CS↑ to DATA OUT (high impedance)
See Figure 3
150
ns
tr(EOC)
tf(EOC)
Rise time, EOC
See Figure 8
300
ns
Fall time, EOC
See Figure 7
300
ns
tr(DATA)
tf(DATA)
Rise time, data bus
See Figure 6
300
ns
Fall time, data bus
See Figure 6
300
ns
9
µs
td(I/O-CS)
Delay time, tenth I/O CLOCK↓ to CS↓ to abort conversion
(see Note 11)
† All typical values are at TA = 25°C.
NOTE 11. Any transitions of CS are recognized as valid only if the level is maintained for a setup time plus two falling edges of the internal clock
(1.425 µs) after the transition.
PARAMETER MEASUREMENT INFORMATION
VCC
Test Point
VCC
Test Point
RL = 2.18 kΩ
RL = 2.18 kΩ
DATA OUT
EOC
12 kΩ
CL = 50 pF
12 kΩ
CL = 100 pF
Figure 2. Load Circuits
Address
Valid
2V
CS
tPZH, tPZL
DATA
OUT
2V
0.8 V
ADDRESS
0.8 V
tPHZ, tPLZ
2.4 V
90%
0.4 V
10%
Figure 3. DATA OUT Enable and Disable
Voltage Waveforms
POST OFFICE BOX 655303
th(A)
tsu(A)
I/O CLOCK
0.8 V
Figure 4. ADDRESS Setup and Hold TIme
Voltage Waveforms
• DALLAS, TEXAS 75265
11
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
2V
CS
0.8 V
tsu(CS)
th(CS)
I/O CLOCK
First
Clock
0.8 V
Last
Clock
0.8 V
Figure 5. I/O CLOCK Setup and Hold Time Voltage Waveforms
tt(I/O)
tt(I/O)
2V
2V
I/O CLOCK
0.8 V
0.8 V
0.8 V
I/O CLOCK Period
td(I/O-DATA)
tv
DATA OUT
2.4 V
2.4 V
0.4 V
0.4 V
tr(DATA), tf(DATA)
Figure 6. I/O CLOCK and DATA OUT Voltage Waveforms
I/O CLOCK
10th
Clock
0.8 V
td(I/O-EOC)
2.4 V
0.4 V
EOC
tf(EOC)
Figure 7. I/O CLOCK and EOC Voltage Waveforms
tr(EOC)
2.4 V
EOC
0.4 V
td(EOC-DATA)
2.4 V
DATA OUT
0.4 V
Valid MSB
Figure 8. EOC and DATA OUT Voltage Waveforms
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
timing diagrams
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
Access Cycle B
DATA
OUT
7
8
9
10
Sample Cycle B
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
1
Hi-Z State
A9
A8
A7
A6
A5
A4
A3
A2
Previous Conversion Data
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
MSB
A1
A0
B9
ÎÎÎÎ
ÎÎÎÎ
LSB
ADDRESS
B3
MSB
B2
B1
B0
LSB
C3
EOC
Shift in New Multiplexer Address;
Simultaneously Shift Out Previous
Conversion Value
Initialize
A/D Conversion
Interval
Initialize
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock
after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 9. Timing for 10-Clock Transfer Using CS
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
timing diagrams (continued)
Must be High on Power Up
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
Access Cycle B
DATA
OUT
A9
A8
A7
7
8
9
A6
A5
A4
A3
A2
A1
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
A0
LSB
ADDRESS
B3
MSB
B2
B1
1
Sample Cycle B
Previous Conversion Data
MSB
10
B0
LSB
Low Level
B9
ÎÎÎÎ
ÎÎÎÎ
C3
EOC
Shift in New Multiplexer Address;
Simultaneously Shift Out Previous
Conversion Value
Initialize
A/D Conversion
Interval
Initialize
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock
after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 10. Timing for 10-Clock Transfer Not Using CS
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
timing diagrams (continued)
ÏÏÏ
ÏÏÏ
ÏÏÏ
ÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
See Note B
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
Access Cycle B
DATA
OUT
A9
A8
A7
8
9
A6
A5
A4
A3
A2
A1
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ ÎÎÎ
B3
MSB
B2
B1
10
11
Sample Cycle B
Previous Conversion Data
MSB
ADDRESS
7
B0
LSB
A0
LSB
Low
Level
16
1
Hi-Z
B9
C3
EOC
Shift in New Multiplexer Address;
Simultaneously Shift Out Previous
Conversion Value
Initialize
A/D Conversion
Interval
Initialize
NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the
minimum CS setup time has elapsed.
B. A low-to-high transition of CS disables ADDRESS and the I/O CLOCK within a maximum of a setup time plus two falling edges of
the internal system clock.
Figure 11. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Interval Shorter Than Conversion)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
timing diagrams (continued)
Must Be High on Power Up
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
Access Cycle B
DATA
OUT
A9
A8
A7
7
8
9
14
15
A6
A5
A4
A3
A2
See Note B
A1
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
A0
Low Level
B2
B1
B9
ÎÎÎÎ
ÎÎÎÎ
LSB
ADDRESS
B3
MSB
1
16
Sample Cycle B
Previous Conversion Data
MSB
10
B0
LSB
C3
EOC
Shift in New Multiplexer Address;
Simultaneously Shift Out Previous
Conversion Value
Initialize
A/D Conversion
Interval
Initialize
NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the
minimum CS setup time has elapsed.
B. The first I/O CLOCK must occur after the rising edge of EOC.
Figure 12. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Interval Shorter Than Conversion)
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
timing diagrams (continued)
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
Access Cycle B
DATA
OUT
A9
A8
A7
7
8
9
A6
A5
A4
A3
A2
A1
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ADDRESS
B3
MSB
B2
B1
11
16
1
See Note B
Sample Cycle B
Previous Conversion Data
MSB
10
ÏÏÏ
ÏÏÏ
ÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÏÏÏ
ÏÏÏ
B0
LSB
A0
LSB
Low
Level
Hi-Z State
B9
C3
EOC
Shift in New Multiplexer Address;
Simultaneously Shift Out Previous
Conversion Value
Initialize
A/D Conversion
Interval
Initialize
NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the
minimum CS setup time has elapsed.
B. The 11th rising edge of the I/O CLOCK sequence must occur before the conversion is complete to prevent losing serial interface
synchronization.
Figure 13. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Interval Longer Than Conversion)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
timing diagrams (continued)
Must be High on Power Up
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
Access Cycle B
DATA
OUT
A9
A8
A7
8
9
A6
A5
A4
A3
A2
B2
B1
14
15
See Note B
A1
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
B3
MSB
10
Sample Cycle B
Previous Conversion Data
MSB
ADDRESS
7
A0
Low Level
16
1
See Note C
B9
ÎÎÎÎ
ÎÎÎÎ
LSB
B0
LSB
C3
EOC
Shift in New Multiplexer Address;
Simultaneously Shift Out Previous
Conversion Value
Initialize
A/D Conversion
Interval
NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the
minimum CS setup time has elapsed.
B. The 11th rising edge of the I/O CLOCK sequence must occur before the conversion is complete to prevent losing serial interface
synchronization.
C. The I/O CLOCK sequence is exactly 16 clock pulses long.
Figure 14. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Interval Longer Than Conversion)
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
APPLICATION INFORMATION
1023
1111111111
See Notes A and B
1022
1111111110
1021
1111111101
VFT = VFS – 1/2 LSB
513
1000000001
512
1000000000
VZT =VZS + 1/2 LSB
Step
Digital Output Code
VFS
511
0111111111
VZS
0000000001
1
0000000000
0
0.0048
0.0096
2.4528
2.4576
2.4624
4.9056
4.9080
2
0.0024
0000000010
4.9104
0
4.9152
VI – Analog Input Voltage – V
NOTES: A. This curve is based on the assumption that Vref + and Vref – have been adjusted so that the voltage at the transition from digital 0
to 1 (VZT) is 0.0024 V and the transition to full scale (VFT) is 4.908 V. 1 LSB = 4.8 mV.
B. The full-scale value (VFS) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (VZS) is
the step whose nominal midstep value equals zero.
Figure 15. Ideal Conversion Characteristics
TLC1542/43
1
2
3
4
5
Analog
Inputs
6
7
8
9
11
12
15
A0
CS
A1
I/O CLOCK
A2
ADDRESS
18
17
Processor
A3
A4
DATA OUT
A5
EOC
16
Control
Circuit
19
A6
A7
14
A8
REF+
A9
REF–
13
5-V DC Regulator
A10
GND
10
To Source
Ground
Figure 16. Serial Interface
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
APPLICATION INFORMATION
simplified analog input analysis
Using the equivalent circuit in Figure 17, the time required to charge the analog input capacitance from 0 to VS
within 1/2 LSB can be derived as follows:
The capacitance charging voltage is given by
(
VC = VS 1– e
– t c /RtCi
)
(1)
where
Rt = Rs + ri
The final voltage to 1/2 LSB is given by
VC (1/2 LSB) = VS – (VS /2048)
(2)
Equating equation 1 to equation 2 and solving for time tc gives
(
VS – (VS/2048) = VS 1– e
– t c /RtCi
)
(3)
and
tc (1/2 LSB) = Rt × Ci × ln(2048)
(4)
Therefore, with the values given the time for the analog input signal to settle is
tc (1/2 LSB) = (Rs + 1 kΩ) × 60 pF × ln(2048)
(5)
This time must be less than the converter sample time shown in the timing diagrams.
Driving Source†
TLC1542/3
Rs
VS
VI
ri
VC
1 kΩ MAX
Ci
50 pF MAX
VI = Input Voltage at A0 – A10
VS = External Driving Source Voltage
Rs = Source Resistance
ri = Input Resistance
Ci = Equivalent Input Capacitance
† Driving source requirements:
• Noise and distortion for the source must be equivalent to the
resolution of the converter.
• Rs must be real at the input frequency.
Figure 17. Equivalent Input Circuit Including the Driving Source
20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
MECHANICAL DATA
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
28 PIN SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,15 NOM
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°– 8°
1,03
0,63
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 / D 02/98
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
MECHANICAL DATA
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PIN SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
16
0.010 (0,25) M
9
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.293 (7,45)
Gage Plane
0.010 (0,25)
1
8
0°– 8°
A
0.050 (1,27)
0.016 (0,40)
Seating Plane
0.104 (2,65) MAX
0.012 (0,30)
0.004 (0,10)
0.004 (0,10)
PINS **
16
20
24
A MAX
0.410
(10,41)
0.510
(12,95)
0.610
(15,49)
A MIN
0.400
(10,16)
0.500
(12,70)
0.600
(15,24)
DIM
4040000 / D 02/98
NOTES: A.
B.
C.
D.
22
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MS-013
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
MECHANICAL DATA
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
B
A
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
25
5
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
MECHANICAL DATA
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
D
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
E
18
D2 / E2
E1
D2 / E2
14
8
0.021 (0,53)
0.013 (0,33)
0.007 (0,18) M
0.050 (1,27)
9
13
0.008 (0,20) NOM
D/E
D2 / E2
D1 / E1
NO. OF
PINS
**
MIN
MAX
MIN
MAX
MIN
MAX
20
0.385 (9,78)
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.169 (4,29)
28
0.485 (12,32)
0.495 (12,57)
0.450 (11,43)
0.456 (11,58)
0.191 (4,85)
0.219 (5,56)
44
0.685 (17,40)
0.695 (17,65)
0.650 (16,51)
0.656 (16,66)
0.291 (7,39)
0.319 (8,10)
52
0.785 (19,94)
0.795 (20,19)
0.750 (19,05)
0.756 (19,20)
0.341 (8,66)
0.369 (9,37)
68
0.985 (25,02)
0.995 (25,27)
0.950 (24,13)
0.958 (24,33)
0.441 (11,20)
0.469 (11,91)
84
1.185 (30,10)
1.195 (30,35)
1.150 (29,21)
1.158 (29,41)
0.541 (13,74)
0.569 (14,45)
4040005 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
MECHANICAL DATA
J (R-GDIP-T**)
CERAMIC DUAL-IN-LINE PACKAGE
14 PIN SHOWN
PINS **
14
16
18
20
A MAX
0.310
(7,87)
0.310
(7,87)
0.310
(7,87)
0.310
(7,87)
A MIN
0.290
(7,37)
0.290
(7,37)
0.290
(7,37)
0.290
(7,37)
B MAX
0.785
(19,94)
0.785
(19,94)
0.910
(23,10)
0.975
(24,77)
B MIN
0.755
(19,18)
0.755
(19,18)
C MAX
0.300
(7,62)
0.300
(7,62)
0.300
(7,62)
0.300
(7,62)
C MIN
0.245
(6,22)
0.245
(6,22)
0.245
(6,22)
0.245
(6,22)
DIM
B
14
8
C
1
7
0.065 (1,65)
0.045 (1,14)
0.100 (2,54)
0.070 (1,78)
0.020 (0,51) MIN
0.930
(23,62)
A
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.100 (2,54)
0°–15°
0.023 (0,58)
0.015 (0,38)
0.014 (0,36)
0.008 (0,20)
4040083/D 08/98
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
Falls within MIL STD 1835 GDIP1-T14, GDIP1-T16, GDIP1-T18, GDIP1-T20, and GDIP1-T22.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
MECHANICAL DATA
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PIN SHOWN
PINS **
14
16
18
20
A MAX
0.775
(19,69)
0.775
(19,69)
0.920
(23.37)
0.975
(24,77)
A MIN
0.745
(18,92)
0.745
(18,92)
0.850
(21.59)
0.940
(23,88)
DIM
A
16
9
0.260 (6,60)
0.240 (6,10)
1
8
0.070 (1,78) MAX
0.035 (0,89) MAX
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.010 (0,25) M
0°– 15°
0.010 (0,25) NOM
14/18 PIN ONLY
4040049/C 08/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)
26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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