MICROCHIP TC500

TC500/A/510/514
Precision Analog Front Ends
Features:
General Description:
• Precision (up to 17 bits) A/D Converter “Front
End”
• 3-Pin Control Interface to Microprocessor
• Flexible: User Can Trade-off Conversion Speed
for Resolution
• Single-Supply Operation (TC510/TC514)
• 4 Input, Differential Analog MUX (TC514)
• Automatic Input Voltage Polarity Detection
• Low Power Dissipation:
- (TC500/TC500A): 10 mW
- (TC510/TC514): 18 mW
• Wide Analog Input Range:
- ±4.2V (TC500A/TC510)
• Directly Accepts Bipolar and Differential
Input Signals
TheTC500/A/510/514 family are precision analog front
ends that implement dual slope A/D converters having
a maximum resolution of 17 bits plus sign. As a
minimum, each device contains the integrator, zero
crossing comparator and processor interface logic. The
TC500 is the base (16-bit max) device and requires
both positive and negative power supplies. The
TC500A is identical to the TC500 with the exception
that it has improved linearity, allowing it to operate to a
maximum resolution of 17 bits. The TC510 adds an onboard negative power supply converter for singlesupply operation. The TC514 adds both a negative
power supply converter and a 4-input differential
analog multiplexer.
Applications:
• Precision Analog Signal Processor
• Precision Sensor Interface
• High Accuracy DC Measurements
Each device has the same processor control interface
consisting of 3 wires: control inputs (A and B) and zerocrossing comparator output (CMPTR). The processor
manipulates A, B to sequence the TC5XX through four
phases of conversion: auto-zero, integrate, de-integrate and integrator zero. During the auto-zero phase,
offset voltages in the TC5XX are corrected by a closed
loop feedback mechanism. The input voltage is applied
to the integrator during the integrate phase. This
causes an integrator output dv/dt directly proportional
to the magnitude of the input voltage. The higher the
input voltage, the greater the magnitude of the voltage
stored on the integrator during this phase. At the start
of the de-integrate phase, an external voltage
reference is applied to the integrator and, at the same
time, the external host processor starts its on-board
timer. The processor maintains this state until a
transition occurs on the CMPTR output, at which time
the processor halts its timer. The resulting timer count
is the converted analog data. Integrator zero (the final
phase of conversion) removes any residue remaining
in the integrator in preparation for the next conversion.
The TC500/A/510/514 offer high resolution (up to 17
bits), superior 50/60 Hz noise rejection, low-power
operation, minimum I/O connections, low input bias
currents and lower cost compared to other converter
technologies having similar conversion speeds.
© 2006 Microchip Technology Inc.
DS21428D-page 1
TC500/A/510/514
Package Types
28-Pin PDIP/SOIC
16-Pin PDIP/SOIC/CERDIP
CINT 1
16 VDD
VOUT –
1
28 CAP–
VSS
2
15 DGND
CINT
2
27 DGND
CAZ
3
14 CMPTR OUT
CAZ
3
26 CAP+
BUF
4
13 B
BUF
4
25 VDD
ACOM
5
TC500/
TC500A
12 A
ACOM
5
24 OSC
CREF – 6
11 VIN+
CREF –
6
23 CMPTR OUT
CREF+
10 VIN –
CREF+
7
VREF –
8
VREF+
9
20 A0
CH4–
10
19 A1
7
VREF − 8
9 VREF+
24-Pin PDIP/SOIC
22 A
TC514
21 B
VOUT –
1
24
CAP–
CH3–
11
18 CH1+
CINT
2
23
DGND
CH2–
12
17 CH2+
CAZ
3
22
CAP+
CH1–
13
16 CH3+
N/C
14
15 CH4+
BUF
4
21
VDD
ACOM
5
20
OSC
CREF –
6
19
CMPTR OUT
CREF+
7
18
A
VREF –
8
17
B
VREF+
9
16
VIN+
N/C 10
15
VIN –
N/C 11
14
N/C
N/C 12
13
N/C
TC510
Typical Application
RINT
CREF
A0
CH1+
CH2+
CH3+
CH4+
CH1CH2CH3CH4-
A1
CREF+
VREF+
CAZ
VREF-
BUF
CREFBuffer
SWR SWR
DIF.
MUX
(TC514)
CINT
CINT
CAZ
Integrator
-
SWI
+
SWRI- SWRI-
A
0
0
1
1
+
+
SWZ
SWI
VSS
Level
Shift
CMPTR
Output
SWIZ SWZ
Polarity
Detection
SWRI+ SWRISW1
DC-TO-DC
Converter
(TC510 & TC514)
Analog
Switch
Control
Signals
VOUT-
1.0 μF
COUT-
DS21428D-page 2
Control Logic
Converter Sate
Zero Integrator Output
Auto-Zero
Signal Integrate
De-integrate
TC500
TC500A
TC510
CMPTR 1
CMPTR 2 TC514
+
ACOM
OSC
B
0
1
0
1
Phase
Decoding
Logic
DGND
CAP- CAP+
1.0 μF
VSS
(TC500
TC500A)
A
B
Control Logic
© 2006 Microchip Technology Inc.
TC500/A/510/514
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings†
TC510/TC514 Positive Supply Voltage
(VDD to GND) ......................................... +10.5V
TC500/TC500A Supply Voltage
(VDD to VSS) .............................................. +18V
† Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only and functional
operation of the device at these or any other conditions
above those indicated in the operation sections of the
specifications is not implied. Exposure to Absolute
Maximum Rating conditions for extended periods may
affect device reliability.
TC500/TC500A Positive Supply Voltage
(VDD to GND) ............................................ +12V
TC500/TC500A Negative Supply Voltage
(VSS to GND)................................................-8V
Analog Input Voltage (VIN+ or VIN-) ............VDD to VSS
Logic Input Voltage...............VDD +0.3V to GND - 0.3V
Voltage on OSC:
........................... -0.3V to (VDD +0.3V) for VDD < 5.5V
Ambient Operating Temperature Range:
................................................................ 0°C to +70°C
Storage Temperature Range: ............. -65°C to +150°C
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, TC510/TC514: VDD = +5V, TC500/TC500A: VSS = ±5V.
CAZ = CREF = 0.47 μF.
Parameters
TA = +25°C
Sym
Min.
Typ.
TA = 0°C to 70°C
Max.
Min.
Typ.
Units
Conditions
Max.
Analog
60
—
—
—
—
—
μV
—
—
0.005
—
0.005
0.012
% F.S.
—
—
0.003
—
0.003
0.009
—
0.005
0.015
—
0.015
0.060
% F.S.
TC500/TC510/TC514
—
—
0.010
—
0.010
0.045
% F.S.
Note 1, Note 2,
TC500A
NL
—
0.003
0.008
—
—
—
% F.S.
TC500/TC510/TC514,
Note 1, Note 2
—
—
0.005
—
—
—
% F.S.
TC500A
Zero-scale Temp.
Coefficient
ZSTC
—
—
—
—
1
2
μV/°C
Over Operating
Temperature Range
Full-scale Symmetry
Error (Rollover Error)
SYE
—
0.01
—
—
0.03
—
% F.S.
Note 1
Full-scale
Temperature
Coefficient
FSTC
—
—
—
—
10
—
ppm/°C Over Operating
Temperature Range;
External Reference
TC = 0 ppm/°C
Resolution
Zero-scale Error with
Auto-zero Phase
ZSE
End Point Linearity
ENL
Best-Case Straight
Line Linearity
TC500A
IIN
—
6
—
—
—
—
pA
VCMR
VSS + 1.5
—
VDD – 1.5
VSS + 1.5
—
VDD – 1.5
V
Integrator Output
Swing
VSS + 0.9
—
VDD – 0.9
VSS + 0.9
—
VSS + 0.9
V
Analog Input Signal
Range
VSS + 1.5
—
VDD – 1.5 VSS + 1.5
—
VSS + 1.5
V
Input Current
Common Mode
Voltage Range
Note 1:
2:
3:
Note 1
TC500/TC510/TC514
VIN = 0V
ACOM = GND = 0V
Integrate time ≥ 66 msec, auto-zero time ≥ 66 msec, VINT (peak) ≈ 4V.
End point linearity at ±1/4, ±1/2, ±3/4 F.S. after full-scale adjustment.
Rollover error is related to CINT, CREF, CAZ characteristics.
© 2006 Microchip Technology Inc.
DS21428D-page 3
TC500/A/510/514
DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, TC510/TC514: VDD = +5V, TC500/TC500A: VSS = ±5V.
CAZ = CREF = 0.47 μF.
Parameters
TA = +25°C
Sym
TA = 0°C to 70°C
Units
Conditions
Min.
Typ.
Max.
Min.
Typ.
Max.
VREF
VSS +1
—
VDD – 1
VSS +1
—
VDD – 1
V
VREF- VREF+
Comparator Logic 1,
Output High
VOH
4
—
—
4
—
—
V
ISOURCE = 400 μA
Comparator Logic 0,
Output Low
VOL
—
—
0.4
—
—
0.4
V
ISINK = 2.1 mA
Logic 1, Input High
Voltage
VIH
3.5
—
—
3.5
—
—
V
Logic 0, Input Low
Voltage
VIL
—
—
1
—
—
1
V
Logic Input Current
IL
—
—
—
—
0.3
Comparator Delay
tD
—
2
—
—
3
—
μsec
-2.5
—
2.5
-2.5
—
2.5
V
VDD = 5V
—
6
10
—
—
—
kΩ
VDD = 5V
Voltage Reference
Range
Digital
μA
Logic ‘1’ or ‘0’
Multiplexer (TC514 Only)
Maximum Input
Voltage
Drain/Source ON
Resistance
RDSON
Power (TC510/TC514 Only)
Supply Current
IS
—
1.8
2.4
—
—
3.5
mA
VDD = 5V, A = 1, B = 1
Power Dissipation
PD
—
18
—
—
—
—
mW
VDD = 5V
Positive Supply
Operating Voltage
Range
VDD
4.5
—
5.5
4.5
—
5.5
V
Operating Source
Resistance
ROUT
—
60
85
—
—
100
Ω
—
100
—
—
—
—
kHz
Note 1
—
—
-10
—
—
-10
mA
VDD = 5V
Oscillator Frequency
Maximum Current
Out
IOUT
IOUT = 10 mA
Power (TC500/TC500A Only)
Supply Current
IS
—
1
1.5
—
—
2.5
mA
VS = ±5V, A = B = 1
Power Dissipation
PD
—
10
—
—
—
—
mW
VDD = 5V, VSS = -5V
Positive Supply
Operating Range
VDD
4.5
—
7.5
4.5
—
7.5
V
Negative Supply
Operating Range
VSS
-4.5
—
-7.5
- 4.5
—
-7.5
V
Note 1:
2:
3:
Integrate time ≥ 66 msec, auto-zero time ≥ 66 msec, VINT (peak) ≈ 4V.
End point linearity at ±1/4, ±1/2, ±3/4 F.S. after full-scale adjustment.
Rollover error is related to CINT, CREF, CAZ characteristics.
DS21428D-page 4
© 2006 Microchip Technology Inc.
TC500/A/510/514
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
-0
5
4
TA = +25°C
V+ = 5V
Output Voltage (V)
Output Voltage (V)
3
2
1
0
-1
-2
-3
-4
-5
Slope 60Ω
-3
-4
-5
-6
-7
0
10
20
30
40
60
50
Load Current (mA)
70
0
80
Output Voltage vs. Load
4
6
8 10 12 14
Output Current (mA)
16
18 20
Output Voltage vs. Output
100
Output Source Resistance (Ω)
V+ = 5V, TA = +25°C
Osc. Freq. = 100 kHz
175
150
CAP = 1 µF
125
100
CAP = 10 µF
75
50
25
0
2
FIGURE 2-4:
Current.
200
Output Ripple (mV PK-PK)
-2
-8
FIGURE 2-1:
Current.
0
1
FIGURE 2-2:
Current.
2
3
4
5
6
7
Load Current (mA)
8
Output Ripple vs. Load
90
V+ = 5V
IOUT = 10 mA
80
70
60
50
40
-50
9 10
0
25
50
Temperature (°C)
-25
FIGURE 2-5:
vs. Temperature.
100
10
1
1
FIGURE 2-3:
Capacitance.
10
100
Oscillator Capacitance (pF)
1000
Oscillator Frequency vs.
© 2006 Microchip Technology Inc.
75
100
Output Source Resistance
150
TA = +25°C
V+ = 5V
Oscillator Frequency (kHz)
Oscillator Frequency (kHz)
TA = +25°C
-1
V+ = 5V
125
100
75
50
-50
-25
FIGURE 2-6:
Temperature.
0
25
75
50
Temperature (°C)
100
125
Oscillator Frequency vs.
DS21428D-page 5
TC500/A/510/514
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
Pin No.
TC500,
TC500A
TC510
TC514
Symbol
1
2
2
CINT
Integrator output. Integrator capacitor connection.
2
Not Used
Not Used
VSS
Negative power supply input (TC500/TC500A only).
3
3
3
CAZ
Auto-zero input. The auto-zero capacitor connection.
4
4
4
BUF
5
5
5
ACOM
6
6
6
CREF-
Input. Negative reference capacitor connection.
7
7
7
CREF+
Input. Positive reference capacitor connection.
8
8
8
VREF-
Input. External voltage reference (-) connection.
9
9
9
VREF+
Input. External voltage reference (+) connection.
10
15
Not Used
VIN-
11
16
Not Used
VIN+
12
18
22
A
Input. Converter phase control MSB. (See input B.)
13
17
21
B
Input. Converter phase control LSB. The states of A, B place the TC5XX in one of
four required phases. A conversion is complete when all four phases have been
executed:
Phase control input pins: AB = 00: Integrator zero
01: Auto-zero
10: Integrate
11: De-integrate
14
19
23
Function
Buffer output. The Integrator capacitor connection.
This pin is grounded in most applications. It is recommended that ACOM and the
input common pin (Ven- or CHn-) be within the analog Common Mode Range (CMR).
Negative analog input.
Positive analog input.
CMPTR Zero crossing comparator output. CMPTR is high during the integration phase when
OUT a positive input voltage is being integrated and is low when a negative input voltage
is being integrated. A high-to-low transition on CMPTR signals the processor that the
De-integrate phase is completed. CMPTR is undefined during the auto-zero phase. It
should be monitored to time the integrator zero phase.
15
23
27
DGND
16
21
25
VDD
Input. Digital ground.
—
22
26
CAP+
Input. Negative power supply converter capacitor (+) connection.
—
24
28
CAP-
Input. Negative power supply converter capacitor (-) connection.
—
1
1
VOUT-
Output. Negative power supply converter output and reservoir capacitor connection.
This output can be used to power other devices in the circuit requiring a negative
bias voltage.
—
20
24
OSC
Oscillator control input. The negative power supply converter normally runs at a
frequency of 100 kHz. The converter oscillator frequency can be slowed down (to
reduce quiescent current) by connecting an external capacitor between this pin and
VDD (see Section 2.0 “Typical Performance Curves”).
Input. Power supply positive connection.
—
—
18
CH1+
Positive analog input pin. MUX channel 1.
—
—
13
CH1-
Negative analog input pin. MUX channel 1.
—
—
17
CH2+
Positive analog input pin. MUX channel 2.
—
—
12
CH2-
Negative analog input pin. MUX channel 2.
—
—
16
CH3+
Positive analog input pin. MUX channel 3.
—
—
11
CH3-
Negative analog input pin. MUX channel 3.
—
—
15
CH4+
Positive analog input pin. MUX channel 4.
—
—
10
CH4-
Negative analog input pin. MUX channel 4
—
—
20
A0
Multiplexer input channel select input LSB (see A1).
—
—
19
A1
Multiplexer input channel select input MSB.
Phase control input pins: A1, A0 = 00 = Channel 1
01 = Channel 2
10 = Channel 3
11 = Channel 4
DS21428D-page 6
© 2006 Microchip Technology Inc.
TC500/A/510/514
DETAILED DESCRIPTION
4.1
Dual Slope Conversion Principles
Actual data conversion is accomplished in two
phases: input signal integration and reference voltage
de-integration.
The integrator output is initialized to 0V prior to the start
of integration. During integration, analog switch S1 connects VIN to the integrator input where it is maintained
for a fixed time period (TINT). The application of VIN
causes the integrator output to depart 0V at a rate determined by the magnitude of VIN and a direction determined by the polarity of VIN. The de-integration phase is
initiated immediately at the expiration of TINT.
During de-integration, S1 connects a reference voltage
(having a polarity opposite that of VIN) to the integrator
input. At the same time, an external precision timer is
started. The de-integration phase is maintained until
the comparator output changes state, indicating the
integrator has returned to its starting point of 0V. When
this occurs, the precision timer is stopped. The deintegration time period (TDEINT), as measured by the
precision timer, is directly proportional to the magnitude
of the applied input voltage (see Figure 4-3).
A simple mathematical equation relates the input
signal, reference voltage and integration time:
multiples of the integration period are, theoretically,
completely removed, since the average value of a sine
wave of frequency (1/T) averaged over a period (T) is
zero.
Integrating converters often establish the integration
period to reject 50/60 Hz line frequency interference
signals. The ability to reject such signals is shown by a
normal mode rejection plot (Figure 4-1). Normal mode
rejection is limited in practice to 50 to 65 dB, since the
line frequency can deviate by a few tenths of a percent
(Figure 4-2).
Normal Mode Rejection (dB)
4.0
30
T = Measurment
Period
20
10
0
0.1/T
1/T
Input Frequency
10/T
FIGURE 4-1:
Integrating Converter
Normal Mode Rejection.
EQUATION 4-1:
Where:
VREF = Reference Voltage
TINT = Signal Integration time (fixed)
tDEINT = Reference Voltage Integration time (variable)
For a constant VIN:
EQUATION 4-2:
VIN
T DEINT
= V REF -----------------T INT
The dual slope converter accuracy is unrelated to the
integrating resistor and capacitor values as long as
they are stable during a measurement cycle.
80
Normal Mode Rejeciton (dB)
V REF C DEINT
T
1
------------------------ ∫ INT V IN ( T )DT = ------------------------------RINT C INT
R INT C INT 0
70
t = 0.1 sec
60
50
40
30
DEV
SIN 60 p t (1 ± 100 )
60 p t (1 ± DEV)
100
DEV = Deviation from 60 Hz
t = Integration Period
Normal Mode = 20 LOG
REJECTION
20
0.01
0.1
1.0
Line Frequency Deviation from 60 Hz (%)
FIGURE 4-2:
Line Frequency Deviation.
An inherent benefit is noise immunity. Input noise
spikes are integrated (averaged to zero) during the
integration periods. Integrating ADCs are immune to
the large conversion errors that plague successive
approximation converters in high noise environments.
Integrating converters provide inherent noise rejection
with at least a 20dB/decade attenuation rate.
Interference signals with frequencies at integral
© 2006 Microchip Technology Inc.
DS21428D-page 7
TC500/A/510/514
CINT
RINT
Analog
Input (VIN)
Integrator
–
TC510
VINT
–
Comparator
+
±
+
S1
Ref
Voltage
Switch Driver
Polarity Control
Phase
Control
Control
Logic
Integrator
Output
A
VIN ≈ VREF
VIN ≈ 1/2 VREF
TINT
FIGURE 4-3:
DS21428D-page 8
CMPTR Out
VSUPPLY
VINT
B
I/O
Microcomputer
ROM
Timer
RAM
Counter
TDEINT
Basic Dual Slope Converter.
© 2006 Microchip Technology Inc.
TC500/A/510/514
5.0
TC500/A/510/514 CONVERTER
OPERATION
The internal analog switch status for each of these
phases is summarized in Table 5-1. This table
references the Typical Application.
The TC500/A/510/514 incorporates an auto-zero and
Integrator phase in addition to the input signal Integrate
and reference De-integrate phases. The addition of
these phases reduce system errors, calibration steps
and shorten overrange recovery time. A typical
measurement cycle uses all four phases in the
following order:
1.
2.
3.
4.
Auto-zero.
Input signal integration.
Reference de-integration.
Integrator output zero.
TABLE 5-1:
INTERNAL ANALOG GATE STATUS
Conversion Phase
Auto-zero (A = 0, B = 1)
Input Signal Integration (A = 1, B = 0)
Reference Voltage De-integration
(A =1, B = 1)
Integrator Output Zero (A = 0, B = 0)
* Assumes a positive polarity input signal.
5.1
SWI
SWR+
SWR-
SWZ
SWR
SW1
SWIZ
—
—
—
Closed
Closed
Closed
—
Closed
—
—
—
—
—
—
—
*
Closed
—
—
—
Closed
—
—
—
—
—
Closed
Closed
Closed
SW–RI
would be closed for a negative input signal.
Auto-zero Phase (AZ)
During this phase, errors due to buffer, integrator and
comparator offset voltages are nulled out by charging
CAZ (auto-zero capacitor) with a compensating error
voltage.
The external input signal is disconnected from the
internal circuitry by opening the two SWI switches. The
internal input points connect to analog common. The
reference capacitor is charged to the reference voltage
potential through SWR. A feedback loop, closed around
the integrator and comparator, charges the capacitor
(CAZ) with a voltage to compensate for buffer amplifier,
integrator and comparator offset voltages.
5.2
Analog Input Signal Integration
Phase (INT)
The TC5XX integrates the differential voltage between
the VIN+ and VIN– inputs. The differential voltage must
be within the device’s Common mode range VCMR. The
input signal polarity is normally checked via software at
the end of this phase: CMPTR = 1 for positive polarity;
CMPTR = 0 for negative polarity.
© 2006 Microchip Technology Inc.
5.3
Reference Voltage De-integration
Phase (DINT)
The previously charged reference capacitor is
connected with the proper polarity to ramp the
integrator output back to zero. An externally-provided,
precision timer is used to measure the duration of this
phase. The resulting time measurement is proportional
to the magnitude of the applied input voltage.
5.4
Integrator Output Zero Phase (IZ)
This phase ensures the integrator output is at 0V when
the auto-zero phase is entered, and that only system
offset voltages are compensated. This phase is used at
the end of the reference voltage de-integration phase
and MUST be used for ALL TC5XX applications having
resolutions of 12-bits or more. If this phase is not used,
the value of the auto-zero capacitor (CAZ) must be
about 2 to 3 times the value of the integration capacitor
(CINT) to reduce the effects of charge sharing. The integrator output zero phase should be programmed to
operate until the output of the comparator returns high.
The overall timing system is shown in Figure 5-1.
DS21428D-page 9
TC500/A/510/514
TTIME
Converter Status
Auto-zero
Integrate
Full-scale Input
Reference
De-integrate
Overshoot Integrator
Output
Zero
Integrator
0
Voltage VINT
Comparator Delay
Undefined
Comparator
Output
A
0 For Negative Input
1 For Positive Input
A=0
A=1
A=1
A=0
B=1
B=0
B=1
B=0
AB Inputs
B
Controller
Operation
Begin Conversion with
Auto-Zero Phase
Time Input
Integration
Phase
Capture
De-integration
Time
Integrator
Ready for Next
Output
Conversion
Zero Phase (Auto-Zero is
Complete
Idle State)
Sample Input Polarity
Typically = TINT
TINT
(Positive Input Shown)
Comparator Delay +
Processor Latency
Minimizing
Overshoot
will Minimize
I.O.Z. Time
Notes: The length of this phase is chosen almost arbitrarily
but needs to be long enough to null out worst case errors
(see text).
FIGURE 5-1:
DS21428D-page 10
Typical Dual Slope A/D Converter System Timing.
© 2006 Microchip Technology Inc.
TC500/A/510/514
6.0
ANALOG SECTION
6.1
Differential Inputs (VIN+, VIN–)
The difference in reference for (+) or (-) input voltages
will cause a rollover error. This error can be minimized
by using a large reference capacitor in comparison to
the stray capacitance.
The TC5XX operates with differential voltages within
the input amplifier Common mode range. The amplifier
Common mode range extends from 1.5V below
positive supply to 1.5V above negative supply. Within
this Common mode voltage range, Common mode
rejection is typically 80 dB. Full accuracy is maintained,
however, when the inputs are no less than 1.5V from
either supply.
6.4
Phase Control Inputs (A, B)
The A, B unlatched logic inputs select the TC5XX
operating phase. The A, B inputs are normally driven
by a microprocessor I/O port or external logic.
6.5
Comparator Output
The integrator output also follows the Common mode
voltage. The integrator output must not be allowed to
saturate. A worst-case condition exists, for example,
when a large, positive Common mode voltage, with a
near full-scale negative differential input voltage, is
applied. The negative input signal drives the integrator
positive when most of its swing has been used up by
the positive Common mode voltage. For these critical
applications, the integrator swing can be reduced. The
integrator output can swing within 0.9V of either supply
without loss of linearity.
By monitoring the comparator output during the fixed
signal integrate time, the input signal polarity can be
determined by the microprocessor controlling the
conversion. The comparator output is high for positive
signals and low for negative signals during the signal
integrate phase (see Figure 6-1).
6.2
The internal comparator delay is 2 μsec, typically.
Figure 6-1 shows the comparator output for large
positive and negative signal inputs. For signal inputs at
or near zero volts, however, the integrator swing is very
small. If Common mode noise is present, the
comparator can switch several times during the
beginning of the signal integrate period. To ensure that
the polarity reading is correct, the comparator output
should be read and stored at the end of the signal
integrate phase.
Analog Common
Analog common is used as VIN return during system
zero and reference de-integrate. If VIN– is different from
analog common, a Common mode voltage exists in the
system. This signal is rejected by the excellent CMR of
the converter. In most applications, VIN– will be set at a
fixed known voltage (i.e., power supply common). A
Common mode voltage will exist when VIN– is not
connected to analog common.
6.3
Differential Reference
(VREF+, VREF–)
The reference voltage can be anywhere within 1V of
the power supply voltage of the converter. Rollover
error is caused by the reference capacitor losing or
gaining charge due to stray capacitance on its nodes.
Signal
Integrate
Reference
Deintegrate
During the reference de-integrate phase, the
comparator output will make a high-to-low transition as
the integrator output ramp crosses zero. The transition
is used to signal the processor that the conversion is
complete.
The comparator output is undefined during the autozero phase and is used to time the integrator output
zero phase. (See Section 8.6 “Integrator Output Zero
Phase”).
Signal
Integrate
Reference
De-integrate
Integrator
Output
Zero
Crossing
Comparator
Output
Zero
Crossing
Comparator
Output
A. Positive Input Signal
FIGURE 6-1:
Integrator
Output
B. Negative Input Signal
Comparator Output.
© 2006 Microchip Technology Inc.
DS21428D-page 11
TC500/A/510/514
7.0
TYPICAL APPLICATIONS
7.1
Component Value Selection
TABLE 7-1:
Conversions
Per Second
Typical Value of
CREF, CAZ (μF)
Suggested* Part
Number
>7
0.1
SMR5 104K50J01L4
2 to 7
0.22
SMR5 224K50J02L4
2 or less
0.47
SMR5 474K50J04L4
The procedure outlined below allows the user to arrive
at values for the following TC5XX design variables:
1.
2.
3.
4.
Integration Phase Timing.
Integrator Timing Components (RINT, CINT).
Auto-zero and Reference Capacitors.
Voltage Reference.
7.2
Select Integration Time
Integration time must be picked as a multiple of the
period of the line frequency. For example, TINT times of
33 msec, 66 msec and 132 msec maximize 60 Hz line
rejection.
7.3
DINT and IZ Phase Timing
The duration of the DINT phase is a function of the
amount of voltage stored on the integrator during TINT
and the value of VREF. The DINT phase must be initiated
immediately following INT and terminated when an integrator output zero-crossing is detected. In general, the
maximum number of counts chosen for DINT is twice
that of INT (with VREF chosen at VIN(MAX) /2).
CREF AND CAZ SELECTION
* Manufactured by Evox Rifa, Inc.
7.6
Calculate Integrating Capacitor
(CINT)
The integrating capacitor must be selected to maximize
integrator output voltage swing. The integrator output
voltage swing is defined as the absolute value of VDD
(or VSS) less 0.9V (i.e., IVDD - 0.9VI or IVSS + 0.9VI).
Using the 20 μA buffer maximum output current, the
value of the integrating capacitor is calculated using the
following equation.
EQUATION 7-2:
–6
( T INT ) ( 20 × 10 )
C INT = --------------------------------------------( VS – 0.9 )
Where:
TINT = Integration Period
VS = IVDDI or IVSSI, whichever is less (TC500/A)
7.4
Calculate Integrating Resistor
(RINT)
The desired full-scale input voltage and amplifier output
current capability determine the value of RINT. The
buffer and integrator amplifiers each have a full-scale
current of 20 μA.
The value of RINT is, therefore, directly calculated in the
following equation:
VS = IVDDI (TC510, TC514)
It is critical that the integrating capacitor has a very low
dielectric absorption. Polypropylene capacitors are an
example of one such dialectic. Polyester and polybicarbonate capacitors may also be used in less critical
applications. Table 7-2 summarizes recommended
capacitors for CINT.
TABLE 7-2:
EQUATION 7-1:
RECOMMENDED CAPACITOR
FOR CINT
Suggested
Part Number*
VIN ( MAX )
RINT ( in MΩ ) = ----------------------20
Value
Where:
0.1
SMR5 104K50J01L4
VIN(MAX) = Maximum input voltage (full count voltage)
0.22
SMR5 224K50J02L4
RINT = Integrating Resistor (in MΩ)
0.33
SMR5 334K50J03L4
For loop stability, RINT should be ≥ 50 kΩ.
0.47
SMR5 474K50J04L4
* Manufactured by Evox Rifa, Inc.
7.5
Select Reference (CREF) and Autozero (CAZ) Capacitors
CREF and CAZ must be low leakage capacitors (such as
polypropylene). The slower the conversion rate, the
larger the value CREF must be. Recommended
capacitors for CREF and CAZ are shown in Table 7-1.
Larger values for CAZ and CREF may also be used to
limit rollover errors.
DS21428D-page 12
7.7
Calculate VREF
The reference de-integration voltage is calculated
using the following equation:
EQUATION 7-3:
( V S – 0.9 ) ( C INT ) ( RINT )
V REF = ----------------------------------------------------------- V
2 ( R INT )
© 2006 Microchip Technology Inc.
TC500/A/510/514
8.0
DESIGN CONSIDERATIONS
8.1
Noise
The threshold noise (NTH) is the algebraic sum of the
integrator and comparator noise and is typically 30 μV.
Figure 8-1 illustrates how the value of the reference
voltage can affect the final count. Such errors can be
reduced by increased integration times, in the same
way that 50/60 Hz noise is rejected. The signal-tonoise ratio is related to the integration time (TINT) and
the integration time constant (RINT, CINT) as follows:
EQUATION 8-1:
tINT
⎛ V IN
⎞
- • --------------------------------------⎟
S/N (dB) = 20 log ⎜ ---------------------–6 ( R
⎝ 30 × 10
INT ) • ( C INT )⎠
8.2
System Timing
To obtain maximum performance from the TC5XX, the
overshoot at the end of the de-integration phase must
be minimized. Also, the integrator output zero phase
must be terminated as soon as the comparator output
returns high (see Figure 5-1).
Figure 5-1 shows the overall timing for a typical system
in which a TC5XX is interfaced to a microcontroller. The
microcontroller drives the A, B inputs with I/O lines and
monitors the comparator output (CMPTR) using an I/O
line or dedicated timer capture control pin. It may be
necessary to monitor the state of the CMPTR output in
addition to having it control a timer directly for the
Reference de-integration phase (this is further
explained below.)
8.4
Input Signal Integrate Phase
The length of this phase is constant from one
conversion to the next and depends on system
parameters and component value selections. The
calculation of TINT is shown elsewhere in this data
sheet. At some point near the end of this phase, the
microcontroller should sample CMPTR to determine
the input signal polarity. This value is, in effect, the Sign
Bit for the overall conversion result. Optimally, CMPTR
should be sampled just before this phase is terminated
by changing AB from 10 to 11. The consideration here
is that, during the initial stage of input integration when
the integrator voltage is low, the comparator may be
affected by noise and its output unreliable. Once
integration is well underway, the comparator will be in a
defined state.
8.5
Reference De-integration
The length of this phase must be precisely measured
from the transition of AB from 10 to 11 to the fallingedge of CMPTR. The comparator delay contributes
some error in timing this phase. The typical delay is
specified to be 2 μsec. This should be considered in the
context of the length of a single count when
determining overall system performance and possible
single count errors. Additionally, overshoot will result in
charge accumulating on the integrator once its output
crosses zero. This charge must be nulled during the
integrator output zero phase.
The timing diagram in Figure 5-1 is not to scale, as the
timing in a real system depends on many system
parameters and component value selections. There
are four critical timing events (as shown in Figure 5-1):
sampling the input polarity, capturing the de-integration
time, minimizing overshoot and properly executing the
integrator output zero phase.
8.3
Auto-zero Phase
The length of this phase is usually set to be equal to the
input signal integration time. This decision is virtually
arbitrary since the magnitudes of the various system
errors are not known. Setting the auto-zero time equal
to the Input Integrate time should be more than
adequate to null out system errors. The system may
remain in this phase indefinitely (i.e., auto-zero is the
appropriate Idle state for a TC5XX device).
© 2006 Microchip Technology Inc.
DS21428D-page 13
TC500/A/510/514
S
S
S
30V
NTH
NTH
Slope (S) =
8.6
VREF
N = Noise Threshold
RINT CINT TH
Noise Threshold.
Integrator Output Zero Phase
The comparator delay and the controller’s response
latency may result in overshoot, causing charge
buildup on the integrator at the end of a conversion.
This charge must be removed or performance will
degrade. The integrator output zero phase should be
activated (AB = 00) until CMPTR goes high. It is
absolutely critical that this phase be terminated
immediately so that overshoot is not allowed to occur in
the opposite direction. At this point, it can be assured
that the integrator is near zero. Auto-zero should be
entered (AB = 01) and the TC5XX held in this state until
the next cycle is begun (see Figure 8-2).
Integrator
Output
Zero
Crossing
Overshoot
Comparator
Output Comp
Integrate
Phase
FIGURE 8-2:
DS21428D-page 14
High VREF
Normal VREF
Low VREF
FIGURE 8-1:
NTH
De-integrate Phase
Integrator
Zero Phase
8.7
8.7.1
Using the TC510/TC514
NEGATIVE SUPPLY VOLTAGE
CONVERTER (TC510, TC514)
A capacitive charge pump is employed to invert the
voltage on VDD for negative bias within the TC510/
TC514. This voltage is also available on the VOUT- pin
to provide negative bias elsewhere in the system. Two
external capacitors are required to perform the
conversion.
Timing is generated by an internal state machine driven
from an on-board oscillator. During the first phase,
capacitor CF is switched across the power supply and
charged to VS+. This charge is transferred to capacitor
COUT- during the second phase. The oscillator normally
runs at 100 kHz to ensure minimum output ripple. This
frequency can be reduced by placing a capacitor from
OSC to VDD. The relationship between the capacitor
value is shown in Section 2.0 “Typical Performance
Curves”.
8.7.2
ANALOG INPUT MULTIPLEXER
(TC514)
The TC514 is equipped with a four-input differential
analog multiplexer. Input channels are selected using
select inputs (A1, A0). These are high-true control
signals (i.e., channel 0 is selected when (A1, A0 = 00).
Overshoot.
© 2006 Microchip Technology Inc.
TC500/A/510/514
9.0
DESIGN EXAMPLES
Refer to Figures 9-1 to 9-4.
Given:
Required Resolution: 16 bits (65,536
counts).
Maximum VIN: ±2V
Power Supply Voltage: +5V
60 Hz System
Step 1.
Pick integration time (tINT) as a multiple
of the line frequency:
1/60 Hz = 16.6 msec. Use 4x line
frequency.
= 66 msec
Step 2.
Calculate RINT:
RINT = VIN(MAX) /20 μA 2 /20 μA
= 100 kΩ
Step 3.
Calculate CINT for maximum (4V)
integrator output swing.
CINT = (tINT) (20 x 10 –6) / (VS - 0.9)
= (.066) (20 x 10 –6) / (4.1)
= 0.32 μF (use closest value: 0.33 μF)
Note:
Step 4.
Microchip recommended capacitor:
Evox Rifa p/n: 5MR5 334K50J03L4.
Choose CREF and CAZ based on
conversion rate.
Conversions/sec:
= 1/(TAZ + TINT + 2 TINT + 2 msec)
= 1/(66 msec +66 msec
+132 msec +2 msec)
= 3.7 conversions/sec
From which CAZ = CREF = 0.22 μF
(see Table 7-1)
Note:
Step 5.
Microchip recommended capacitor:
Evox Rifa p/n: 5MR5 224K50J02L4
Calculate VREF:
EQUATION 9-1:
( V S – 0.9 ) ( C INT ) ( RINT )
V REF = ----------------------------------------------------------2 ( T INT )
–6
5
=
( 4.1 ) ( 0.33 × 1 ) ( 10 -)
------------------------------------------------------------2 ( 0.66 )
= 1.025
© 2006 Microchip Technology Inc.
DS21428D-page 15
TC500/A/510/514
1
VOUTCINT
0.33 μF 2
CINT
CAZ
0.22 μF 3
CAZ
1 μF
4
+5V
RINT
100 kΩ
MCP1525
5
6
TC510
VDD
BUF
1 μF
Typical Waveforms
+5V
Pin 2
22
21
VIN+
+5V
PICmicro
Microcontroller
CMPTR
CREF+
A
9 V
REF+
B
8
VIN+
VREF-
Pin 19
19
Pin 2
18
VIN-
17
Pin 19
16
INPUT+
VIN- 15
INPUT-
TC510 Design Sample.
1 μF
CINT
0.33 μF
CAZ
0.22 μF
VOUT-
RINT
100 kΩ
CREF
R2 0.22 μF
10 kΩ
R3, 10 kΩ
C1
0.01 μF
CAP-
2 C
INT
3
CAZ
4
+5V
1 μF
23
ACOM
1
MCP1525
CAP+
CREF-
7
C1
0.01 μF
FIGURE 9-1:
DGND
24
®
CREF
R2 0.22 μF
10 kΩ
R3, 10 kΩ
1 μF
CAP-
BUF
5
6
7
DGND
CAP+
TC514
A0
ACOM
CREFCREF+
9 V
REF+
8
VDD
VREF-
A1
CMPTR
28
27
25
+5V
22
19
PICmicro®
Microcontroller
Analog
Mux Logic
23
22
B
21
CH1-
+5V
26
A
CH1+
1 μF
18
13
INPUT 1+
INPUT 1Typical Waveforms
CH2+
17
CH2-
12
CH3+
16
CH3-
11
CH4+
15
CH4-
10
INPUT 2+
PIN 2
INPUT 2VIN+
INPUT 3+
INPUT 3-
PIN 23
INPUT4+
INPUT4-
PIN 2
VINPIN 23
FIGURE 9-2:
DS21428D-page 16
TC514 Design Example.
© 2006 Microchip Technology Inc.
TC500/A/510/514
+5V
21
VDD
1
VOUT-
CAP-
1 μF
24
CAP+ 22
7
CREF+
1 μF
CREF- 6
0.22 μF
MCP1525
VREF+ 9
TC510
0.01 μF
VREF-
PC
Printer
Port
PORT
0378
Hex
BUF
B
CINT 2
19 CMPTR
VIN+ 16
3
17
10
VIN- 15
DGND
23
FIGURE 9-3:
1 μF
4 100 kΩ
0.22 μF
CAZ 3
18
10 kΩ
8
A
2
10 kΩ
ACOM 5
0.33 μF
100 kΩ
+
0.01 μF
Input
–
TC510 To IBM® Compatible Printer Port.
© 2006 Microchip Technology Inc.
DS21428D-page 17
TC500/A/510/514
+5V
+
Input 1
–
+
Input 2
–
+
Input 3
–
+
Input 4
–
18
13
17
Port
0378
Hex
CH1–
CAP+
15
22
3
21
10
23
10 kΩ
MCP1525
0.22 μF
CREF- 6
10 kΩ
CH3–
VREF+ 9
CH4+
10 CH4–
19
1 μF
26
CREF+ 7
16 CH3+
11
1 μF
CH2+
12 CH2–
20
Analog
Mux Control Logic
IBM®
Printer Port
2
25 1
28
CH1+ VDD VOUT CAP–
10 kΩ
0.01 μF
TC514
VREF-
8
A0
100 kΩ
A1
BUF 4
A
CAZ 3
B
0.22 μF
CINT 2
0.33 μF
CMPTR
ACOM
5
DGND
27
FIGURE 9-4:
DS21428D-page 18
TC514 To IBM® Compatible Printer Port.
© 2006 Microchip Technology Inc.
TC500/A/510/514
10.0
PACKAGING INFORMATION
10.1
Package Marking Information
16-Lead CERDIP (300 mil)
Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
16-Lead PDIP (300 mil)
TC500AIJE
0441256
Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
16-Lead SOIC (300 mil)
TC500CPE
0441256
Example:
XXXXXXXXXXXXX
XXXXXXXXXXXXX
YYWWNNN
Legend: XX...X
YY
WW
NNN
TC500ACOE
0441256
Customer specific information*
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters for customer specific information.
*
Standard marking consists of Microchip part number, year code, week code, traceability code.
For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.
© 2006 Microchip Technology Inc.
DS21428D-page 19
TC500/A/510/514
Package Marking Information (Continued)
24-Lead PDIP (300 mil)
Example:
XXXXXXXXXXXXX
YYWWNNN
24-Lead SOIC (300 mil)
TC510CPF
0441256
Example:
XXXXXXXXXXXXX
XXXXXXXXXXXXX
YYWWNNN
28-Lead PDIP (300 mil)
TC510COG
0441256
Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
28-Lead SOIC (300 mil)
XXXXXXXXXXXXX
XXXXXXXXXXXXX
XXXXXXXXXXXXX
YYWWNNN
DS21428D-page 20
TC514CPJ
0441256
Example:
TC514COI
0441256
© 2006 Microchip Technology Inc.
TC500/A/510/514
16-Lead Ceramic Dual In-line (JE) – 300 mil (CERDIP)
E1
D
2
n
1
E
A2
A
L
c
A1
B1
eB
p
B
Units
Dimension Limits
n
p
Number of Pins
Pitch
Top to Seating Plane
Standoff §
Shoulder to Shoulder Width
Ceramic Pkg. Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
*Controlling Parameter
JEDEC Equivalent: MS-030
A
A1
E
E1
D
L
c
B1
B
eB
MIN
.160
.015
.290
.280
.752
.125
.008
.045
.015
.325
INCHES*
NOM
18
.100
.180
.030
.305
.288
.760
.163
.012
.055
.018
.360
MAX
.200
.040
.325
.296
.780
.200
.014
.065
.021
.410
MILLIMETERS
NOM
18
2.54
4.06
4.57
0.38
0.76
7.37
7.75
7.11
7.32
19.10
19.30
4.14
3.18
0.20
0.30
1.14
1.40
0.38
0.46
8.25
9.14
MIN
MAX
5.08
1.02
8.25
7.52
19.81
5.08
0.36
1.65
0.53
10.41
Drawing No. C04-003
© 2006 Microchip Technology Inc.
DS21428D-page 21
TC500/A/510/514
16-Lead Plastic Dual In-line (PE) – 300 mil (PDIP)
E1
D
2
α
n
1
E
A2
A
L
c
A1
β
B1
eB
p
B
Units
Dimension Limits
MILLIMETERS
INCHES*
MIN
NOM
MAX
MIN
NOM
MAX
Pitch
n
p
Top to Seating Plane
A
.140
.155
.170
3.56
3.94
4.32
Molded Package Thickness
A2
.115
.130
.145
2.92
3.30
3.68
Base to Seating Plane
A1
.015
Shoulder to Shoulder Width
E
.300
.313
.325
7.62
7.94
8.26
Molded Package Width
E1
.240
.250
.260
6.10
6.35
6.60
Overall Length
D
.740
.750
.760
18.80
19.05
19.30
Tip to Seating Plane
L
.125
.130
.135
3.18
3.30
3.43
Lead Thickness
c
.008
.012
.015
0.20
0.29
0.38
Upper Lead Width
B1
.045
.058
.070
1.14
1.46
1.78
Lower Lead Width
B
.014
.018
.022
.036
0.46
0.56
Overall Row Spacing
eB
.310
.370
.430
7.87
9.40
10.92
Mold Draft Angle Top
α
5
10
15
5
10
15
Mold Draft Angle Bottom
β
5
10
15
5
10
15
Number of Pins
16
16
.100
2.54
0.38
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-017
DS21428D-page 22
Revised 07-21-05
© 2006 Microchip Technology Inc.
TC500/A/510/514
16-Lead Plastic Small Outline (OE) – Wide, 300 mil (SOIC)
E
p
E1
D
2
1
n
B
h
α
45°
c
A2
A
φ
β
L
Units
Dimension Limits
n
p
INCHES*
NOM
16
.050
.099
.091
.008
.407
.295
.406
.020
.033
4
.011
.017
12
12
MAX
MILLIMETERS
NOM
16
1.27
2.36
2.50
2.24
2.31
0.10
0.20
10.01
10.34
7.39
7.49
10.10
10.30
0.25
0.50
0.41
0.84
0
4
0.23
0.28
0.36
0.42
0
12
0
12
MAX
Number of Pins
Pitch
Overall Height
A
.093
.104
2.64
Molded Package Thickness
A2
.088
.094
2.39
Standoff
§
.004
.012
0.30
A1
Overall Width
E
.394
.420
10.67
Molded Package Width
E1
.291
.299
7.59
Overall Length
D
.398
.413
10.49
Chamfer Distance
h
.010
.029
0.74
Foot Length
L
.016
.050
1.27
φ
Foot Angle
0
8
8
c
Lead Thickness
.009
.013
0.33
Lead Width
B
.014
.020
0.51
α
Mold Draft Angle Top
0
15
15
β
Mold Draft Angle Bottom
0
15
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-102
© 2006 Microchip Technology Inc.
MIN
A1
MIN
DS21428D-page 23
TC500/A/510/514
24-Lead Skinny Plastic Dual In-line (PF) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
B1
β
p
B
eB
Units
Dimension Limits
MILLIMETERS
INCHES*
MIN
NOM
MAX
MIN
NOM
MAX
Pitch
n
p
Top to Seating Plane
A
.140
.150
.160
3.56
3.81
4.06
Molded Package Thickness
A2
.115
.130
.145
2.92
3.30
3.68
Base to Seating Plane
A1
.015
Shoulder to Shoulder Width
E
.295
.310
.325
7.49
7.87
8.26
Molded Package Width
E1
.240
.250
.260
6.10
6.35
6.60
Overall Length
D
1.245
1.250
1.255
31.62
31.75
31.88
Tip to Seating Plane
L
c
.120
.125
.130
3.05
3.18
3.30
.008
.012
.015
0.20
0.29
0.38
Upper Lead Width
B1
.045
.053
.060
1.14
1.33
1.52
Lower Lead Width
B
.014
.018
.022
0.36
0.46
0.56
Overall Row Spacing
eB
α
.310
.370
.430
7.87
9.40
10.92
5
10
15
5
10
15
5
10
15
5
10
15
Number of Pins
Lead Thickness
Mold Draft Angle Top
Mold Draft Angle Bottom
β
24
24
.100
2.54
0.38
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.
JEDEC Equivalent: MS-001 AF
Drawing No. C04-043
Revised 09-14-05
DS21428D-page 24
© 2006 Microchip Technology Inc.
TC500/A/510/514
24-Lead Plastic Small Outline (OG) – Wide, 300 mil (SOIC)
E
E1
e
D
B
2
n
1
α
h
h
c
A
β
L
φ
A1
Units
Dimension Limits
Number of Pins
A2
MILLIMETERS*
INCHES
MIN
NOM
n
MAX
MIN
NOM
24
MAX
24
Pitch
e
Overall Height
A
.093
--
.104
2.35
--
2.65
Molded Package Thickness
A2
.081
--
.100
2.05
--
2.55
Standoff
A1
.004
--
.012
0.10
--
0.30
Overall Width
E
.406 BSC
Molded Package Width
E1
.295 BSC
7.50 BSC
Overall Length
D
.607 BSC
15.40 BSC
.050 BSC
1.27 BSC
10.30 BSC
Chamfer Distance
h
.010
--
.030
0.25
--
0.75
Foot Length
.016
--
.050
0.40
--
1.27
Foot Angle
L
φ
Lead Thickness
c
.008
--
.013
0.20
--
0.33
Lead Width
B
α
.012
--
.020
0.31
Mold Draft Angle Top
Mold Draft Angle Bottom
β
0°
--
8°
0°
--
8°
--
0.51
5°
--
15°
5°
--
15°
5°
--
15°
5°
--
15°
* Controlling Parameter per JEDEC MS-103 Revision C.
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
JEDEC Equivalent: MS-013 AD
Revised 07-19-05
Drawing No. C04-025
© 2006 Microchip Technology Inc.
DS21428D-page 25
TC500/A/510/514
28-Lead Skinny Plastic Dual In-line (PJ) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
β
B1
A1
eB
Units
Number of Pins
Pitch
p
B
Dimension Limits
n
p
INCHES*
MIN
NOM
MILLIMETERS
MAX
MIN
NOM
28
MAX
28
.100
2.54
Top to Seating Plane
A
.140
.150
.160
3.56
3.81
4.06
Molded Package Thickness
A2
.125
.130
.135
3.18
3.30
3.43
Base to Seating Plane
A1
.015
8.26
0.38
Shoulder to Shoulder Width
E
.300
.310
.325
7.62
7.87
Molded Package Width
E1
.275
.285
.295
6.99
7.24
7.49
Overall Length
D
1.345
1.365
1.385
34.16
34.67
35.18
Tip to Seating Plane
L
c
.125
.130
.135
3.18
3.30
3.43
.008
.012
.015
0.20
0.29
0.38
B1
.040
.053
.065
1.02
1.33
1.65
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
§
B
.016
.019
.022
0.41
0.48
0.56
eB
α
.320
.350
.430
8.13
8.89
10.92
5
10
15
5
10
15
β
Mold Draft Angle Bottom
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MO-095
Drawing No. C04-070
DS21428D-page 26
© 2006 Microchip Technology Inc.
TC500/A/510/514
28-Lead Plastic Small Outline (OI) – Wide, 300 mil (SOIC)
E
E1
p
D
B
2
1
n
h
α
45°
c
A2
A
φ
β
L
Units
Dimension Limits
n
p
A1
INCHES*
NOM
28
.050
.099
.091
.008
.407
.295
.704
.020
.033
4
.011
.017
12
12
MAX
MILLIMETERS
NOM
28
1.27
2.36
2.50
2.24
2.31
0.10
0.20
10.01
10.34
7.32
7.49
17.65
17.87
0.25
0.50
0.41
0.84
0
4
0.23
0.28
0.36
0.42
0
12
0
12
MAX
Number of Pins
Pitch
Overall Height
A
.093
.104
2.64
Molded Package Thickness
A2
.088
.094
2.39
Standoff
§
A1
.004
.012
0.30
Overall Width
E
.394
.420
10.67
Molded Package Width
E1
.288
.299
7.59
Overall Length
D
.695
.712
18.08
Chamfer Distance
h
.010
.029
0.74
Foot Length
L
.016
.050
1.27
φ
Foot Angle Top
0
8
8
c
Lead Thickness
.009
.013
0.33
Lead Width
B
.014
.020
0.51
α
Mold Draft Angle Top
0
15
15
β
Mold Draft Angle Bottom
0
15
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
© 2006 Microchip Technology Inc.
MIN
MIN
DS21428D-page 27
TC500/A/510/514
10.2
Product Tape and Reel Specifications
Component Taping Orientation for 16-Pin SOIC (Wide) Devices
User Direction of Feed
Pin 1
W
P
Standard Reel Component Orientation
for 713 Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size
Package
Carrier Width (W)
Pitch (P)
Part Per Full Reel
Reel Size
16 mm
12 mm
1000
13 in
16-Pin SOIC (W)
Component Taping Orientation for 24-Pin SOIC (Wide) Devices
User Direction of Feed
Pin 1
W
P
Standard Reel Component Orientation
for 713 Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size
Package
24-Pin SOIC (W)
DS21428D-page 28
Carrier Width (W)
Pitch (P)
Part Per Full Reel
Reel Size
24 mm
12 mm
1000
13 in
© 2006 Microchip Technology Inc.
TC500/A/510/514
Product Tape and Reel Specifications (Continued)
Component Taping Orientation for 28-Pin SOIC (Wide) Devices
User Direction of Feed
Pin 1
W
P
Standard Reel Component Orientation
for 713 Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size
Package
28-Pin SOIC (W)
© 2006 Microchip Technology Inc.
Carrier Width (W)
Pitch (P)
Part Per Full Reel
Reel Size
24 mm
12 mm
1000
13 in
DS21428D-page 29
TC500/A/510/514
NOTES:
DS21428D-page 30
© 2006 Microchip Technology Inc.
TC500/A/510/514
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
/XX
Device
Temperature
Range
Package
Device
Temperature Range
Package:
TC500
TC500A
TC510
TC514
C
I
16 Bit Analog Processor
16 Bit Analog Processor
Precision Analog Front End
Precision Analog Front End
=
=
0°C to +70°C (Commercial)
-25°C to +85°C (Industrial)
JE
PE
OE
OE713
=
=
=
=
PF
OG
OG713
=
=
=
PJ
OI
OI713
=
=
=
Ceramic Dual In-line, (300 mil Body), 16-lead
Plastic DIP, (300 mil Body), 16-lead
Plastic SOIC, (300 mil Body), 16-lead
Plastic SOIC, (300 mil Body), 16-lead
(Tape and Reel)
Plastic DIP, (300 mil Body), 24-lead
Plastic SOIC, (300 mil Body), 24-lead
Plastic SOIC, (300 mil Body), 24-lead
(Tape and Reel)
Plastic DIP, (300 mil Body), 28-lead
Plastic SOIC, (300 mil Body), 28-lead
Plastic SOIC, (300 mil Body), 28-lead
(Tape and Reel)
Examples:
a)
TC500ACOE:
b)
TC500ACOE713:
c)
TC500ACPE:
d)
TC500AIJE:
a)
TC500COE:
b)
TC500COE713:
c)
TC500CPE:
d)
TC500IJE:
a)
TC510COG:
b)
TC510COG713:
c)
TC510CPF:
a)
TC514COI:
b)
TC514COI713:
c)
TC514CPJ:
Commercial Temp.,
16LD SOIC package.
Commercial Temp.,
16LD SOIC package,
Tape and Reel.
Commercial Temp.,
16LD PDIP package.
Industrial Temp.,
16LD CERDIP package.
Commercial Temp.,
16LD SOIC package.
Commercial Temp.,
16LD SOIC package,
Tape and Reel.
Commercial Temp.,
16LD PDIP package.
Industrial Temp.,
16LD CERDIP package.
Commercial Temp.,
24LD PDIP package.
Commercial Temp.,
24LD PDIP package,
Tape and Reel.
Commercial Temp.,
24LD PDIP package.
Commercial Temp.,
28LD PDIP package.
Commercial Temp.,
28LD PDIP package,
Tape and Reel.
Commercial Temp.,
28LD PDIP package.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.
2.
3.
Your local Microchip sales office
The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
© 2006 Microchip Technology Inc.
DS21428D-page 31
TC500/A/510/514
NOTES:
DS21428D-page 32
© 2006 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. Use of Microchip’s products as critical components in
life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Linear Active Thermistor,
MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM,
PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo,
PowerMate, PowerTool, Real ICE, rfLAB, rfPICDEM, Select
Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,
WiperLock and Zena are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2006, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2006 Microchip Technology Inc.
DS21428D-page 33
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
India - Bangalore
Tel: 91-80-2229-0061
Fax: 91-80-2229-0062
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
India - New Delhi
Tel: 91-11-5160-8631
Fax: 91-11-5160-8632
Austria - Wels
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
China - Chengdu
Tel: 86-28-8676-6200
Fax: 86-28-8676-6599
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
China - Fuzhou
Tel: 86-591-8750-3506
Fax: 86-591-8750-3521
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Korea - Gumi
Tel: 82-54-473-4301
Fax: 82-54-473-4302
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
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Fax: 82-2-558-5932 or
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Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
China - Shunde
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
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Tel: 86-29-8833-7250
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Malaysia - Penang
Tel: 60-4-646-8870
Fax: 60-4-646-5086
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
10/31/05
DS21428D-page 34
© 2006 Microchip Technology Inc.