TI TAS5142DDV

TM
TAS5142
www.ti.com
SLES126B – DECEMBER 2004 – REVISED MAY 2005
STEREO DIGITAL AMPLIFIER POWER STAGE
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2×100 W at 10% THD+N Into 4-Ω BTL (1)
2×80 W at 10% THD+N Into 6-Ω BTL
2×65 W at 10% THD+N Into 8-Ω BTL
4×40 W at 10% THD+N Into 3-Ω SE
4×30 W at 10% THD+N Into 4-Ω SE
1×160 W at 10% THD+N Into 3-Ω PBTL
1×200 W at 10% THD+N Into 2-Ω PBTL (1)
>100 dB SNR (A-Weighted)
<0.1% THD+N at 1 W
Two Thermally Enhanced Package Options:
– DKD (36-pin PSOP3)
– DDV (44-pin HTSSOP)
High-Efficiency Power Stage (>90%) With
140-mΩ Output MOSFETs
Power-On Reset for Protection on Power Up
Without Any Power-Supply Sequencing
Integrated Self-Protection Circuits Including
Undervoltage, Overtemperature, Overload,
Short Circuit
Error Reporting
EMI Compliant When Used With
Recommended System Design
Intelligent Gate Drive
APPLICATIONS
•
•
•
Mini/Micro Audio System
DVD Receiver
Home Theater
DESCRIPTION
The TAS5142 is a third-generation, high-performance, integrated stereo digital amplifier power stage
with an improved protection system. The TAS5142 is
capable of driving a 4-Ω bridge-tied load (BTL) at up
to 100 W per channel with low integrated noise at the
output, low THD+N performance, and low idle power
dissipation.
A low-cost, high-fidelity audio system can be built
using a TI chipset, comprising a modulator (e.g.,
TAS5508) and the TAS5142. This system only
requires a simple passive LC demodulation filter to
deliver high-quality, high-efficiency audio amplification
with proven EMI compliance. This device requires two
power supplies, at 12 V for GVDD and VDD, and at
32 V for PVDD. The TAS5142 does not require
power-up sequencing due to internal power-on reset.
The efficiency of this digital amplifier is greater than
90% into 6 Ω, which enables the use of smaller
power supplies and heatsinks.
The TAS5142 has an innovative protection system
integrated on-chip, safeguarding the device against a
wide range of fault conditions that could damage the
system. These safeguards are short-circuit protection,
overcurrent protection, undervoltage protection, and
overtemperature protection. The TAS5142 has a new
proprietary current-limiting circuit that reduces the
possibility of device shutdown during high-level music
transients. A new programmable overcurrent detector
allows the use of lower-cost inductors in the
demodulation output filter.
BTL OUTPUT POWER vs SUPPLY VOLTAGE
120
TC = 75°C
THD+N @ 10%
110
100
90
PO − Output Power − W
FEATURES
4Ω
80
70
60
6Ω
50
40
30
8Ω
20
10
0
0
4
8
12
16
20
24
28
32
PVDD − Supply Voltage − V
G002
(1) It is not recommended to drive 200 W (total power) into the
DDV package continuously. For multichannel systems that
require two channels to be driven at full power with the
DDV package option, it is recommended to design the
system so that the two channels are in two separate
devices.
PurePath Digital™
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PurePath Digital, PowerPad are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2005, Texas Instruments Incorporated
TAS5142
www.ti.com
SLES126B – DECEMBER 2004 – REVISED MAY 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
GENERAL INFORMATION
Terminal Assignment
The TAS5142 is available in two thermally enhanced packages:
• 36-pin PSOP3 package (DKD)
• 44-pin HTSSOP PowerPad™ package (DDV)
Both package types contain a heat slug that is located on the top side of the device for convenient thermal
coupling to the heatsink.
DDV PACKAGE
(TOP VIEW)
DKD PACKAGE
(TOP VIEW)
GVDD_B
OTW
SD
PWM_A
RESET_AB
PWM_B
OC_ADJ
GND
AGND
VREG
M3
M2
M1
PWM_C
RESET_CD
PWM_D
VDD
GVDD_C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
GVDD_A
BST_A
PVDD_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
PVDD_D
BST_D
GVDD_D
P0018-01
GVDD_B
OTW
NC
NC
SD
PWM_A
RESET_AB
PWM_B
OC_ADJ
GND
AGND
VREG
M3
M2
M1
PWM_C
RESET_CD
PWM_D
NC
NC
VDD
GVDD_C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
GVDD_A
BST_A
NC
PVDD_A
PVDD_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
PVDD_D
PVDD_D
NC
BST_D
GVDD_D
P0016-02
2
TAS5142
www.ti.com
SLES126B – DECEMBER 2004 – REVISED MAY 2005
GENERAL INFORMATION (continued)
MODE Selection Pins for Both Packages
MODE PINS
(1)
(2)
PWM INPUT
M3
M2
M1
0
0
0
2N
0
0
1
Reserved
0
1
0
1N
(1)
0
1
1
1N
(1)
1N
(1)
1
0
0
1
0
1
1
1
0
1
1
1
(1)
OUTPUT CONFIGURATION
PROTECTION SCHEME
2 channels BTL output
BTL mode
(2)
AD modulation
2 channels BTL output
BTL mode
(2)
AD modulation
1 channel PBTL output
PBTL mode. Only PWM_A input is used.
4 channels SE output
Protection works similarly to BTL mode (2). Only
difference in SE mode is that OUT_X is Hi-Z
instead of a pulldown through internal pulldown
resistor.
AD/BD modulation
AD modulation
Reserved
The 1N and 2N naming convention is used to indicate the required number of PWM lines to the power stage per channel in a specific
mode.
An overload protection (OLP) occurring on A or B causes both channels to shut down. An OLP on C or D works similarly. Global errors
like overtemperature error (OTE), undervoltage protection (UVP), and power-on reset (POR) affect all channels.
Package Heat Dissipation Ratings (1)
(1)
(2)
PARAMETER
TAS5142DKD
TAS5142DDV
RθJC (°C/W)—2 BTL or 4 SE channels (8 transistors)
1.28
1.28
RθJC (°C/W)—1 BTL or 2 SE channel(s) (4 transistors)
2.56
2.56
RθJC (°C/W)—(1 transistor)
8.6
8.6
Pad area (2)
80 mm2
36 mm2
JC is junction-to-case, CH is case-to-heatsink.
RθCH is an important consideration. Assume a 2-mil thickness of typical thermal grease between the pad area and the heatsink. The
RθCH with this condition is 0.8°C/W for the DKD package and 1.8°C/W for the DDV package.
3
TAS5142
www.ti.com
SLES126B – DECEMBER 2004 – REVISED MAY 2005
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
TAS5142
VDD to AGND
–0.3 V to 13.2 V
GVDD_X to AGND
–0.3 V to 13.2 V
PVDD_X to GND_X
(2)
–0.3 V to 50 V
OUT_X to GND_X
(2)
–0.3 V to 50 V
BST_X to GND_X
(2)
–0.3 V to 63.2 V
VREG to AGND
–0.3 V to 4.2 V
GND_X to GND
–0.3 V to 0.3 V
GND_X to AGND
–0.3 V to 0.3 V
GND to AGND
–0.3 V to 0.3 V
PWM_X, OC_ADJ, M1, M2, M3 to AGND
–0.3 V to 4.2 V
RESET_X, SD, OTW to AGND
–0.3 V to 7 V
Maximum continuous sink current (SD, OTW)
9 mA
Maximum operating junction temperature range, TJ
0°C to 125°C
Storage temperature
–40°C to 125°C
Lead temperature, 1,6 mm (1/16 inch) from case for 10 seconds
260°C
Minimum pulse duration, low
50 ns
(1)
(2)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.
ORDERING INFORMATION
TA
PACKAGE
DESCRIPTION
0°C to 70°C
TAS5142DKD
36-pin PSOP3
0°C to 70°C
TAS5142DDV
44-pin HTSSOP
For the most current specification and package information, see the TI Web site at www.ti.com.
4
TAS5142
www.ti.com
SLES126B – DECEMBER 2004 – REVISED MAY 2005
Terminal Functions
TERMINAL
NAME
(1)
DKD NO.
DDV NO.
FUNCTION
(1)
DESCRIPTION
AGND
9
11
P
Analog ground
BST_A
35
43
P
HS bootstrap supply (BST), external capacitor to OUT_A required
BST_B
28
34
P
HS bootstrap supply (BST), external capacitor to OUT_B required
BST_C
27
33
P
HS bootstrap supply (BST), external capacitor to OUT_C required
BST_D
20
24
P
HS bootstrap supply (BST), external capacitor to OUT_D required
GND
8
10
P
Ground
GND_A
32
38
P
Power ground for half-bridge A
GND_B
31
37
P
Power ground for half-bridge B
GND_C
24
30
P
Power ground for half-bridge C
GND_D
23
29
P
Power ground for half-bridge D
GVDD_A
36
44
P
Gate-drive voltage supply requires 0.1-µF capacitor to AGND
GVDD_B
1
1
P
Gate-drive voltage supply requires 0.1-µF capacitor to AGND
GVDD_C
18
22
P
Gate-drive voltage supply requires 0.1-µF capacitor to AGND
GVDD_D
19
23
P
Gate-drive voltage supply requires 0.1-µF capacitor to AGND
M1
13
15
I
Mode selection pin
M2
12
14
I
Mode selection pin
M3
11
13
I
Mode selection pin
NC
–
3, 4, 19, 20, 25,
42
–
No connect. Pins may be grounded.
OC_ADJ
7
9
O
Analog overcurrent programming pin requires resistor to ground
OTW
2
2
O
Overtemperature warning signal, open-drain, active-low
OUT_A
33
39
O
Output, half-bridge A
OUT_B
30
36
O
Output, half-bridge B
OUT_C
25
31
O
Output, half-bridge C
OUT_D
22
28
O
Output, half-bridge D
PVDD_A
34
40, 41
P
Power supply input for half-bridge A requires close decoupling of
0.1-µF capacitor to GND_A.
PVDD_B
29
35
P
Power supply input for half-bridge B requires close decoupling of
0.1-µF capacitor to GND_B.
PVDD_C
26
32
P
Power supply input for half-bridge C requires close decoupling of
0.1-µF capacitor to GND_C.
PVDD_D
21
26, 27
P
Power supply input for half-bridge D requires close decoupling of
0.1-µF capacitor to GND_D.
PWM_A
4
6
I
Input signal for half-bridge A
PWM_B
6
8
I
Input signal for half-bridge B
PWM_C
14
16
I
Input signal for half-bridge C
PWM_D
16
18
I
Input signal for half-bridge D
RESET_AB
5
7
I
Reset signal for half-bridge A and half-bridge B, active-low
RESET_CD
15
17
I
Reset signal for half-bridge C and half-bridge D, active-low
SD
3
5
O
Shutdown signal, open-drain, active-low
VDD
17
21
P
Power supply for digital voltage regulator requires 0.1-µF capacitor
to GND.
VREG
10
12
P
Digital regulator supply filter pin requires 0.1-µF capacitor to AGND.
I = input, O = output, P = power
5
TAS5142
www.ti.com
SLES126B – DECEMBER 2004 – REVISED MAY 2005
SYSTEM BLOCK DIAGRAM
OTW
System
Microcontroller
SD
TAS5508
OTW
SD
BST_A
BST_B
RESET_AB
RESET_CD
VALID
PWM_A
LeftChannel
Output
OUT_A
Output
H-Bridge 1
Input
H-Bridge 1
PWM_B
OUT_B
Bootstrap
Capacitors
2nd-Order L-C
Output Filter
for Each
Half-Bridge
2-Channel
H-Bridge
BTL Mode
OUT_C
PWM_C
4
32 V
PVDD
System
Power
Supply
GND
12 V
VAC
6
4
PVDD
Power
Supply
Decoupling
OC_ADJ
AGND
VREG
M3
OUT_D
2nd-Order L-C
Output Filter
for Each
Half-Bridge
BST_C
VDD
M2
GND
PVDD_A, B, C, D
M1
GVDD_A, B, C, D
Input
H-Bridge 2
PWM_D
Hardwire
Mode
Control
Output
H-Bridge 2
GND_A, B, C, D
RightChannel
Output
BST_D
Bootstrap
Capacitors
4
GVDD
VDD
VREG
Power Supply
Decoupling
Hardwire
OC Limit
GND
GVDD (12 V)/VDD (12 V)
B0047-01
TAS5142
www.ti.com
SLES126B – DECEMBER 2004 – REVISED MAY 2005
FUNCTIONAL BLOCK DIAGRAM
VDD
Undervoltage
Protection
OTW
Internal Pullup
Resistors to VREG
SD
M1
Protection
and
I/O Logic
M2
M3
4
VREG
VREG
Power
On
Reset
AGND
Temp.
Sense
GND
RESET_AB
Overload
Protection
RESET_CD
Isense
OC_ADJ
GVDD_D
BST_D
PVDD_D
PWM_D
PWM
Rcv.
Ctrl.
Timing
Gate
Drive
OUT_D
BTL/PBTL−Configuration
Pulldown Resistor
GND_D
GVDD_C
BST_C
PVDD_C
PWM_C
PWM
Rcv.
Ctrl.
Timing
Gate
Drive
OUT_C
BTL/PBTL−Configuration
Pulldown Resistor
GND_C
GVDD_B
BST_B
PVDD_B
PWM_B
PWM
Rcv.
Ctrl.
Timing
Gate
Drive
OUT_B
BTL/PBTL−Configuration
Pulldown Resistor
GND_B
GVDD_A
BST_A
PVDD_A
PWM_A
PWM
Rcv.
Ctrl.
Timing
Gate
Drive
OUT_A
BTL/PBTL−Configuration
Pulldown Resistor
GND_A
B0034-02
7
TAS5142
www.ti.com
SLES126B – DECEMBER 2004 – REVISED MAY 2005
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
UNIT
PVDD_X
Half-bridge supply
DC supply voltage
0
32
34
V
GVDD_X
Supply for logic regulators and gate-drive
circuitry
DC supply voltage
10.8
12
13.2
V
VDD
Digital regulator input
DC supply voltage
10.8
12
13.2
V
3
4
2
3
RL (BTL)
RL (SE)
Output filter: L = 10 µH, C = 470 nF.
Output AD modulation, switching
frequency > 350 kHz
Load impedance
RL (PBTL)
LOutput (BTL)
LOutput (SE)
Output-filter inductance
Minimum output inductance under
short-circuit condition
LOutput (PBTL)
FPWM
PWM frame rate
TJ
Junction temperature
1.5
2
5
10
5
10
5
10
192
384
0
Ω
µH
432
kHz
125
°C
AUDIO SPECIFICATIONS (BTL)
PVDD_X = 32 V, GVDD = VDD = 12 V, BTL mode, RL = 4 Ω, audio frequency = 1 kHz, AES17 filter, FPWM = 384 kHz, case
temperature = 75°C, unless otherwise noted. Audio performance is recorded as a chipset, using TAS5508 PWM processor
with an effective modulation index limit of 96.1%. All performance is in accordance with recommended operating conditions
unless otherwise specified.
PARAMETER
PO
Power output per channel, DKD package
TEST CONDITIONS
TAS5142
MIN
TYP
RL = 4 Ω, 10% THD, clipped input
signal
100
RL = 6 Ω, 10% THD, clipped input
signal
80
RL = 8 Ω, 10% THD, clipped input
signal
65
RL = 4 Ω, 0 dBFS, unclipped input
signal
80
RL = 6 Ω, 0 dBFS, unclipped input
signal
60
RL = 8 Ω, 0 dBFS, unclipped input
signal
50
0 dBFS
0.3%
1W
0.1%
MAX
UNIT
W
THD+N
Total harmonic distortion + noise
Vn
Output integrated noise
A-weighted
140
µV
SNR
Signal-to-noise ratio
(1)
A-weighted
102
dB
A-weighted, input level = –60 dBFS
using TAS5508 modulator
102
A-weighted, input level = –60 dBFS
using TAS5518 modulator
110
DNR
Pidle
(1)
(2)
Dynamic range
Power dissipation due to idle losses (IPVDD_X)
PO = 0 W, 4 channels switching (2)
dB
2
W
SNR is calculated relative to 0-dBFS input level.
Actual system idle losses are affected by core losses of output inductors.
AUDIO SPECIFICATIONS (Single-Ended Output)
PVDD_X = 32 V, GVDD = VDD = 12 V, SE mode, RL = 4 Ω, audio frequency = 1 kHz, AES17 filter, FPWM = 384 kHz, case
temperature = 75°C, unless otherwise noted. Audio performance is recorded as a chipset, using TAS5086 PWM processor
with an effective modulation index limit of 96.1%. All performance is in accordance with recommended operating conditions
8
TAS5142
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SLES126B – DECEMBER 2004 – REVISED MAY 2005
AUDIO SPECIFICATIONS (Single-Ended Output) (continued)
PVDD_X = 32 V, GVDD = VDD = 12 V, SE mode, RL = 4 Ω, audio frequency = 1 kHz, AES17 filter, FPWM = 384 kHz, case
temperature = 75°C, unless otherwise noted. Audio performance is recorded as a chipset, using TAS5086 PWM processor
with an effective modulation index limit of 96.1%. All performance is in accordance with recommended operating conditions
unless otherwise specified.
unless otherwise specified.
PARAMETER
PO
Power output per channel, DKD package
TEST CONDITIONS
TAS5142
MIN
TYP
RL = 3 Ω, 10% THD, clipped input
signal
40
RL = 4 Ω, 10% THD, clipped input
signal
30
RL = 3 Ω, 0 dBFS, unclipped input
signal
30
RL = 4 Ω, 0 dBFS, unclipped input
signal
20
MAX
UNIT
W
0 dBFS
0.2%
1W
0.1%
THD+N
Total harmonic distortion + noise
Vn
Output integrated noise
A-weighted
90
µV
SNR
Signal-to-noise ratio (1)
A-weighted
100
dB
DNR
Dynamic range
A-weighted, input level = –60 dBFS
using TAS5508 modulator
100
dB
Pidle
Power dissipation due to idle losses (IPVDD_X)
PO = 0 W, 4 channels switching (2)
2
W
(1)
(2)
SNR is calculated relative to 0-dBFS input level.
Actual system idle losses are affected by core losses of output inductors.
AUDIO SPECIFICATIONS (PBTL)
PVDD_X = 32 V, GVDD = VDD = 12 V, PBTL mode, RL = 3 Ω, audio frequency = 1 kHz, AES17 filter, FPWM = 384 kHz, case
temperature = 75°C, unless otherwise noted. Audio performance is recorded as a chipset, using TAS5508 PWM processor
with an effective modulation index limit of 96.1%. All performance is in accordance with recommended operating conditions
unless otherwise specified.
PARAMETER
PO
Power output per channel, DKD package
TEST CONDITIONS
TAS5142
MIN
TYP
RL = 3 Ω, 10% THD, clipped input
signal
160
RL = 2 Ω, 10% THD, clipped input
signal
200
RL = 3 Ω, 0 dBFS, unclipped input
signal
120
RL = 2 Ω, 0 dBFS, unclipped input
signal
150
MAX
UNIT
W
0 dBFS
0.2%
1W
0.1%
THD+N
Total harmonic distortion + noise
Vn
Output integrated noise
A-weighted
140
µV
SNR
Signal-to-noise ratio (1)
A-weighted
102
dB
A-weighted, input level = –60 dBFS
using TAS5508 modulator
102
A-weighted, input level = –60 dBFS
using TAS5518 modulator
110
DNR
Pidle
(1)
(2)
Dynamic range
Power dissipation due to idle losses (IPVDD_X)
PO = 0 W, 1 channel switching (2)
dB
2
W
SNR is calculated relative to 0-dBFS input level.
Actual system idle losses are affected by core losses of output inductors.
9
TAS5142
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SLES126B – DECEMBER 2004 – REVISED MAY 2005
ELECTRICAL CHARACTERISTICS
RL= 4 Ω, FPWM = 384 kHz, unless otherwise noted. All performance is in accordance with recommended operating conditions
unless otherwise specified.
PARAMETER
TEST CONDITIONS
TAS5142
MIN
TYP
MAX
3
3.3
3.6
Operating, 50% duty cycle
7
17
Idle, reset mode
6
11
UNIT
Internal Voltage Regulator and Current Consumption
VREG
Voltage regulator, only used as a
reference node
IVDD
VDD supply current
IGVDD_X
Gate supply current per half-bridge
IPVDD_X
Half-bridge idle current
VDD = 12 V
50% duty cycle
V
mA
5
16
Reset mode
0.3
1
50% duty cycle, without output filter or load
15
25
mA
7
25
µA
Reset mode, no switching
mA
Output Stage MOSFETs
RDSon,LS
Drain-to-source resistance, LS
TJ = 25°C, includes metallization resistance,
GVDD = 12 V
140
155
mΩ
RDSon,HS
Drain-to-source resistance, HS
TJ = 25°C, includes metallization resistance,
GVDD = 12 V
140
155
mΩ
I/O Protection
Undervoltage protection limit,
GVDD_X
Vuvp,G
Vuvp,hyst
9.8
(1)
V
250
mV
OTW (1)
Overtemperature warning
OTWHYST (1)
Temperature drop needed below
OTW temp. for OTW to be inactive
after the OTW event
OTE (1)
Overtemperature error
OTEOTWdifferential (1)
OTE-OTW differential
30
°C
OTEHYST (1)
A reset event must occur for SD to
be released following an OTE event.
25
°C
OLPC
Overload protection counter
FPWM = 384 kHz
1.25
ms
IOC
Overcurrent limit protection
Resistor—programmable, high-end,
ROCP = 18 kΩ
7.9
IOCT
Overcurrent response time
ROCP
OC programming resistor range
Resistor tolerance = 5%
18
RPD
Internal pulldown resistor at the
output of each half-bridge
Connected when RESET is active to provide
bootstrap capacitor charge. Not used in SE
mode
115
125
135
25
145
155
9.7
°C
°C
165
11.4
210
°C
A
ns
69
2.5
kΩ
kΩ
Static Digital Specifications
VIH
High-level input voltage
VIL
Low-level input voltage
Leakage
Input leakage current
PWM_A, PWM_B, PWM_C, PWM_D, M1,
M2, M3, RESET_AB, RESET_CD
2
V
–10
0.8
V
10
µA
kΩ
OTW/SHUTDOWN (SD)
RINT_PU
Internal pullup resistance, OTW to
VREG, SD to VREG
VOH
High-level output voltage
VOL
Low-level output voltage
IO = 4 mA
0.2
FANOUT
Device fanout OTW, SD
No external pullup
30
(1)
10
Specified by design
Internal pullup resistor
External pullup of 4.7 kΩ to 5 V
20
26
32
3
3.3
3.6
4.5
5
0.4
V
V
Devices
TAS5142
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SLES126B – DECEMBER 2004 – REVISED MAY 2005
TYPICAL CHARACTERISTICS, BTL CONFIGURATION
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
OUTPUT POWER
vs
SUPPLY VOLTAGE
120
TC = 75°C
PVDD = 32 V
One Channel
TC = 75°C
THD+N @ 10%
110
100
90
PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise − %
10
1
6Ω
4Ω
0.1
8Ω
4Ω
80
70
60
6Ω
50
40
30
8Ω
20
10
0
0.01
1
10
0
100
4
8
16
20
24
28
32
G002
G001
Figure 1.
Figure 2.
UNCLIPPED OUTPUT POWER
vs
SUPPLY VOLTAGE
SYSTEM EFFICIENCY
vs
OUTPUT POWER
100
120
110
TC = 75°C
90
100
80
8Ω
90
70
80
Efficiency − %
PO − Output Power − W
12
PVDD − Supply Voltage − V
PO − Output Power − W
4Ω
70
60
50
6Ω
40
6Ω
4Ω
60
50
40
30
30
20
20
8Ω
10
10
TC = 25°C
0
0
0
4
8
12
16
20
24
28
0
32
PVDD − Supply Voltage − V
G003
Figure 3.
20
40
60
80 100 120 140 160 180 200 220
PO − Output Power − W
G004
Figure 4.
11
TAS5142
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SLES126B – DECEMBER 2004 – REVISED MAY 2005
TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
SYSTEM POWER LOSS
vs
OUTPUT POWER
SYSTEM OUTPUT POWER
vs
CASE TEMPERATURE
40
130
TC = 25°C
110
4Ω
6Ω
100
PO − Output Power − W
30
Power Loss − W
4Ω
120
35
25
6Ω
20
15
10
90
80
70
60
50
8Ω
40
30
5
20
8Ω
10
0
THD+N @ 10%
0
0
20 40 60 80 100 120 140 160 180 200 220
PO − Output Power − W
10
20
30
40
50
G005
Figure 5.
0
TC = 75°C
−10
−20
−30
Noise Amplitude − dBr
70
Figure 6.
NOISE AMPLITUDE
vs
FREQUENCY
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
0
2
4
6
8
10
12
14
16
18
20
22
f − Frequency − kHz
G007
Figure 7.
12
60
80
90 100 110 120
TC − Case Temperature − °C
G006
TAS5142
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SLES126B – DECEMBER 2004 – REVISED MAY 2005
TYPICAL CHARACTERISTICS, SE CONFIGURATION
OUTPUT POWER
vs
SUPPLY VOLTAGE
50
10
TC = 75°C
Digital Gain = 3 dB
TC = 75°C
THD+N @ 10%
45
PO − Output Power − W
40
1
3Ω
0.1
35
30
3Ω
25
20
15
4Ω
10
4Ω
5
0.01
1
10
0
50
PO − Output Power − W
0
4
8
12
16
20
24
28
32
PVDD − Supply Voltage − V
G008
G009
Figure 8.
Figure 9.
OUTPUT POWER
vs
CASE TEMPERATURE
60
55
50
3Ω
45
PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise − %
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
40
35
30
25
4Ω
20
15
10
5
THD+N @ 10%
0
10
20
30
40
50
60
70
80
90 100 110 120
TC − Case Temperature − °C
G010
Figure 10.
13
TAS5142
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SLES126B – DECEMBER 2004 – REVISED MAY 2005
TYPICAL CHARACTERISTICS, PBTL CONFIGURATION
OUTPUT POWER
vs
SUPPLY VOLTAGE
220
TC = 75°C
Digital Gain = 3 dB
10
TC = 75°C
THD+N @ 10%
200
180
PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise − %
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
1
2Ω
0.1
3Ω
160
2Ω
140
120
100
80
60
3Ω
40
20
0.01
1
10
100
0
200
0
PO − Output Power − W
4
8
12
16
Figure 12.
SYSTEM OUTPUT POWER
vs
CASE TEMPERATURE
250
THD+N @ 10%
240
PO − Output Power − W
230
2Ω
220
210
200
190
180
3Ω
170
160
150
10
20
30
40
50
24
28
32
G012
Figure 11.
60
70
80
90 100 110 120
TC − Case Temperature − °C
Figure 13.
14
20
PVDD − Supply Voltage − V
G011
G013
TAS5142
www.ti.com
SLES126B – DECEMBER 2004 – REVISED MAY 2005
PVDD
10 Ω
GVDD
10 µF
3.3 Ω
100 nF
47 µF
50 V
10 Ω
1000 µF
50 V
10 nF
50 V
10 nF
50 V
TAS5142DKD
100 nF
1
Microcontroller
2
0Ω
Optional
3
Shutdown
GVDD_A
35
OTW
SD
5
VALID
22 kΩ
7
PWM2_P
OUT_A
RESET_AB
GND_A
PWM_B
GND_B
OC_ADJ
AGND
OUT_B
28
13
BST_C
26
M3
PVDD_C
M2
OUT_C
M1
GND_C
PWM_C
GND_D
RESET_CD
OUT_D
10 Ω
100 nF
47 µF
50 V
10 nF
50 V
100 nF
50 V
PWM_D
470 nF
100 V
10 µ[email protected] A
21
PVDD_D
100 nF
50 V
20
BST_D
18
19
GVDD_C
3.3 Ω
10 µ[email protected] A
22
VDD
10 µF
47 µF
50 V
23
17
GVDD
100 nF
50 V
24
15
16
33 nF
100 nF
50 V
25
14
1Ω
33 nF
BST_B
27
VREG
12
10 nF
50 V
PVDD_B
10
11
3.3 Ω
30
9
100 nF
100 nF
50 V
31
29
GND
TAS5508
470 nF
100 V
10 µ[email protected] A
32
3.3 Ω
10 µ[email protected] A
33
PWM_A
8
PWM2_M
100 nF
50 V
34
PVDD_A
6
PWM1_M
33 nF
BST_A
4
PWM1_P
100 nF
50 V
36
GVDD_B
47 µF
50 V
100 nF
50 V
3.3 Ω
10 nF
50 V
33 nF
GVDD_D
PVDD
100 nF
100 nF
10 Ω
3.3 Ω
10 nF
50 V
1000 µF
50 V
S0070-01
Figure 14. Typical Differential (2N) BTL Application With AD Modulation Filters
15
TAS5142
www.ti.com
SLES126B – DECEMBER 2004 – REVISED MAY 2005
PVDD
10 Ω
GVDD
10 µF
3.3 Ω
100 nF
47 µF
50 V
10 Ω
1000 µF
50 V
10 nF
50 V
10 nF
50 V
TAS5142DKD
100 nF
1
Microcontroller
2
0Ω
Optional
3
Shutdown
GVDD_A
35
OTW
SD
5
VALID
7
OUT_A
RESET_AB
GND_A
PWM_B
GND_B
OC_ADJ
AGND
OUT_B
28
13
BST_C
26
M3
PVDD_C
M2
OUT_C
M1
GND_C
PWM_C
GND_D
RESET_CD
OUT_D
16
10 Ω
100 nF
47 µF
50 V
10 nF
50 V
100 nF
50 V
PWM_D
470 nF
100 V
10 µ[email protected] A
21
PVDD_D
100 nF
50 V
20
BST_D
18
19
GVDD_C
3.3 Ω
10 µ[email protected] A
22
VDD
10 µF
47 µF
50 V
23
17
GVDD
100 nF
50 V
24
15
No connect
33 nF
100 nF
50 V
25
14
1Ω
33 nF
BST_B
27
VREG
12
10 nF
50 V
PVDD_B
10
11
3.3 Ω
30
9
TAS5508
100 nF
50 V
31
29
GND
100 nF
470 nF
100 V
10 µ[email protected] A
32
3.3 Ω
10 µ[email protected] A
33
PWM_A
8
PWM2
100 nF
50 V
34
PVDD_A
6
No connect
22 kΩ
33 nF
BST_A
4
PWM1
100 nF
50 V
36
GVDD_B
47 µF
50 V
50 nF
100 V
3.3 Ω
10 nF
50 V
33 nF
GVDD_D
PVDD
100 nF
100 nF
10 Ω
3.3 Ω
10 nF
50 V
1000 µF
50 V
S0070-02
Figure 15. Typical Non-Differential (1N) BTL Application With AD Modulation Filters
16
TAS5142
www.ti.com
SLES126B – DECEMBER 2004 – REVISED MAY 2005
10 Ω
100 nF
GVDD
10 µF
PVDD
47 µF
50 V
10 Ω
3.3 Ω
TAS5142DKD
100 nF
1
Microcontroller
2
0Ω
Optional
3
Shutdown
36
GVDD_B
GVDD_A
35
OTW
PWM1_P1
5
VALID
SD
PVDD_A
39 kΩ
PWM3_P
7
33
PWM_A
OUT_A
RESET_AB
GND_A
PWM_B
GND_B
OC_ADJ
OUT_B
30
PVDD_B
9
BST_B
10
27
VREG
TAS5508
12
13
BST_C
M3
PVDD_C
M2
OUT_C
M1
GND_C
PWM_C
GND_D
RESET_CD
OUT_D
10 µ[email protected] A
22
D
21
PWM_D
PVDD_D
100 nF
50 V
20
VDD
BST_D
18
GVDD_D
PVDD
100 nF
100 nF
3.3 Ω
100 nF
100 V
PVDD
PVDD/2
220 µF
50 V
1 µF
50 V
100 nF
100 V
2.7 kΩ
PVDD/2
100 nF
100 V
3.3 Ω
C
10 nF @ 50 V
2.7 kΩ
PVDD
3.3 Ω
220 µF
50 V
B
PVDD
10 nF
50 V
PVDD/2
100 nF
100 V
220 µF
50 V
220 µF
50 V
1 µF
50 V
100 nF
100 V
1000 µF
50 V
10 nF
50 V
10 Ω
2.7 kΩ
47 µF
50 V
33 nF
19
GVDD_C
10 Ω
A
C
10 µ[email protected] A
23
17
100 nF
47 µF
50 V
100 nF
50 V
24
16
10 µF
47 µF
50 V
100 nF
50 V
25
15
1Ω
33 nF
26
14
GVDD
33 nF
28
AGND
11
B
31
29
GND
100 nF
10 µ[email protected] A
32
8
PWM4_P
A
10 µ[email protected] A
100 nF
50 V
34
6
PWM2_P
33 nF
BST_A
4
1000 µF
50 V
10 nF
50 V
220 µF
50 V
1 µF
50 V
100 nF
100 V
100 nF
100 V
3.3 Ω
D
10 nF @ 50 V
2.7 kΩ
PVDD
PVDD/2
3.3 Ω
10 nF @ 50 V
3.3 Ω
220 µF
50 V
10 nF
50 V
3.3 Ω
10 nF
50 V
220 µF
50 V
1 µF
50 V
100 nF
100 V
10 nF
50 V
3.3 Ω
10 nF @ 50 V
3.3 Ω
220 µF
50 V
S0071-01
Figure 16. Typical SE Application
17
TAS5142
www.ti.com
SLES126B – DECEMBER 2004 – REVISED MAY 2005
PVDD
10 Ω
GVDD
10 µF
3.3 Ω
100 nF
47 µF
50 V
10 Ω
1000 µF
50 V
10 nF
50 V
10 nF
50 V
TAS5142DKD
100 nF
1
Microcontroller
2
0Ω
Optional
3
Shutdown
GVDD_A
35
OTW
SD
5
VALID
30 kΩ
7
OUT_A
RESET_AB
GND_A
PWM_B
GND_B
OC_ADJ
AGND
OUT_B
28
BST_C
26
M3
PVDD_C
M2
OUT_C
M1
GND_C
PWM_C
GND_D
RESET_CD
OUT_D
10 Ω
100 nF
100 nF
50 V
47 µF
50 V
47 µF
50 V
10 µ[email protected] A
24
23
10 µ[email protected] A
22
PWM_D
21
PVDD_D
100 nF
50 V
20
VDD
10 µF
33 nF
100 nF
50 V
25
17
GVDD
33 nF
BST_B
15
16
3.3 Ω
10 nF
50 V
PVDD_B
14
1Ω
100 nF
100 V
27
VREG
13
470 nF
63 V
30
10
12
10 µ[email protected] A
32
31
9
TAS5508
10 µ[email protected] A
29
GND
11
3.3 Ω
33
PWM_A
8
100 nF
100 nF
50 V
34
PVDD_A
6
PWM1_M
33 nF
BST_A
4
PWM1_P
100 nF
100 V
36
GVDD_B
BST_D
18
19
GVDD_C
47 µF
50 V
33 nF
GVDD_D
PVDD
100 nF
100 nF
10 Ω
3.3 Ω
10 nF
50 V
1000 µF
50 V
S0070-03
Figure 17. Typical Differential (2N) PBTL Application With AD Modulation Filters
18
TAS5142
www.ti.com
SLES126B – DECEMBER 2004 – REVISED MAY 2005
PVDD
10 Ω
GVDD
10 µF
3.3 Ω
100 nF
47 µF
50 V
10 Ω
1000 µF
50 V
10 nF
50 V
TAS5142DKD
100 nF
1
Microcontroller
2
0Ω
Optional
3
Shutdown
36
GVDD_B
GVDD_A
35
OTW
SD
5
VALID
7
OUT_A
RESET_AB
GND_A
PWM_B
GND_B
OC_ADJ
OUT_B
PVDD_B
28
AGND
BST_B
VREG
BST_C
10
12
13
M3
26
No connect
16
M2
OUT_C
M1
GND_C
PWM_C
GND_D
10 Ω
100 nF
100 nF
50 V
470 nF
63 V
47 µF
50 V
47 µF
50 V
100 nF
100 V
3.3 Ω
RESET_CD
OUT_D
10 nF
50 V
10 µ[email protected] A
24
23
10 µ[email protected] A
22
PWM_D
21
PVDD_D
100 nF
50 V
20
VDD
10 µF
3.3 Ω
25
17
GVDD
33 nF
100 nF
50 V
PVDD_C
15
1Ω
33 nF
27
14
No connect
100 nF
100 V
30
9
TAS5508
10 nF
50 V
29
GND
11
10 µ[email protected] A
32
31
8
100 nF
10 µ[email protected] A
33
PWM_A
6
No connect
30 kΩ
100 nF
50 V
34
PVDD_A
4
PWM1
33 nF
BST_A
BST_D
18
19
GVDD_C
47 µF
50 V
33 nF
GVDD_D
PVDD
100 nF
100 nF
10 Ω
3.3 Ω
10 nF
50 V
1000 µF
50 V
S0070-04
Figure 18. Typical Non-Differential (1N) PBTL Application
19
TAS5142
www.ti.com
SLES126B – DECEMBER 2004 – REVISED MAY 2005
THEORY OF OPERATION
POWER SUPPLIES
To facilitate system design, the TAS5142 needs only
a 12-V supply in addition to the (typical) 32-V
power-stage supply. An internal voltage regulator
provides suitable voltage levels for the digital and
low-voltage analog circuitry. Additionally, all circuitry
requiring a floating voltage supply, e.g., the high-side
gate drive, is accommodated by built-in bootstrap
circuitry requiring only a few external capacitors.
In order to provide outstanding electrical and
acoustical characteristics, the PWM signal path
including gate drive and output stage is designed as
identical, independent half-bridges. For this reason,
each half-bridge has separate gate drive supply
(GVDD_X), bootstrap pins (BST_X), and power-stage
supply pins (PVDD_X). Furthermore, an additional pin
(VDD) is provided as supply for all common circuits.
Although supplied from the same 12-V source, it is
highly recommended to separate GVDD_A,
GVDD_B, GVDD_C, GVDD_D, and VDD on the
printed-circuit board (PCB) by RC filters (see
application diagram for details). These RC filters
provide the recommended high-frequency isolation.
Special attention should be paid to placing all
decoupling capacitors as close to their associated
pins as possible. In general, inductance between the
power supply pins and decoupling capacitors must be
avoided. (See reference board documentation for
additional information.)
For a properly functioning bootstrap circuit, a small
ceramic capacitor must be connected from each
bootstrap pin (BST_X) to the power-stage output pin
(OUT_X). When the power-stage output is low, the
bootstrap capacitor is charged through an internal
diode connected between the gate-drive power-supply pin (GVDD_X) and the bootstrap pin. When
the power-stage output is high, the bootstrap
capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply
for the high-side gate driver. In an application with
PWM switching frequencies in the range from 352
kHz to 384 kHz, it is recommended to use 33-nF
ceramic capacitors, size 0603 or 0805, for the
bootstrap supply. These 33-nF capacitors ensure
sufficient energy storage, even during minimal PWM
duty cycles, to keep the high-side power stage FET
(LDMOS) fully turned on during the remaining part of
the PWM cycle. In an application running at a
reduced switching frequency, generally 192 kHz, the
bootstrap capacitor might need to be increased in
value.
20
Special attention should be paid to the power-stage
power supply; this includes component selection,
PCB placement, and routing. As indicated, each
half-bridge has independent power-stage supply pins
(PVDD_X). For optimal electrical performance, EMI
compliance, and system reliability, it is important that
each PVDD_X pin is decoupled with a 100-nF
ceramic capacitor placed as close as possible to
each supply pin. It is recommended to follow the PCB
layout of the TAS5142 reference design. For
additional information on recommended power supply
and required components, see the application
diagrams given previously in this data sheet.
The 12-V supply should be from a low-noise,
low-output-impedance voltage regulator. Likewise, the
32-V power-stage supply is assumed to have low
output impedance and low noise. The power-supply
sequence is not critical as facilitated by the internal
power-on-reset circuit. Moreover, the TAS5142 is fully
protected against erroneous power-stage turnon due
to parasitic gate charging. Thus, voltage-supply ramp
rates (dV/dt) are non-critical within the specified
range (see the Recommended Operating Conditions
section of this data sheet).
SYSTEM POWER-UP/POWER-DOWN
SEQUENCE
Powering Up
The TAS5142 does not require a power-up sequence.
The outputs of the H-bridges remain in a high-impedance state until the gate-drive supply voltage
(GVDD_X) and VDD voltage are above the
undervoltage protection (UVP) voltage threshold (see
the Electrical Characteristics section of this data
sheet). Although not specifically required, it is
recommended to hold RESET_AB and RESET_CD in
a low state while powering up the device. This allows
an internal circuit to charge the external bootstrap
capacitors by enabling a weak pulldown of the
half-bridge output.
When the TAS5142 is being used with TI PWM
modulators such as the TAS5508, no special
attention to the state of RESET_AB and RESET_CD
is required, provided that the chipset is configured as
recommended.
Powering Down
The TAS5142 does not require a power-down
sequence. The device remains fully operational as
long as the gate-drive supply (GVDD_X) voltage and
VDD voltage are above the undervoltage protection
(UVP) voltage threshold (see the Electrical
TAS5142
www.ti.com
SLES126B – DECEMBER 2004 – REVISED MAY 2005
Characteristics section of this data sheet). Although
not specifically required, it is a good practice to hold
RESET_AB and RESET_CD low during power down,
thus preventing audible artifacts including pops or
clicks.
temperature has dropped or the supply voltage has
increased. For highest possible reliability, recovering
from an overload fault requires external reset of the
device (see the Device Reset section of this data
sheet) no sooner than 1 second after the shutdown.
When the TAS5142 is being used with TI PWM
modulators such as the TAS5508, no special
attention to the state of RESET_AB and RESET_CD
is required, provided that the chipset is configured as
recommended.
Use of TAS5142
Capable Systems
ERROR REPORTING
The SD and OTW pins are both active-low,
open-drain
outputs.
Their
function
is
for
protection-mode signaling to a PWM controller or
other system-control device.
Any fault resulting in device shutdown is signaled by
the SD pin going low. Likewise, OTW goes low when
the device junction temperature exceeds 125°C (see
the following table).
SD
OTW
DESCRIPTION
0
0
Overtemperature (OTE) or overload (OLP) or
undervoltage (UVP)
0
1
Overload (OLP) or undervoltage (UVP)
1
0
Junction temperature higher than 125°C
(overtemperature warning)
1
1
Junction temperature lower than 125°C and no
OLP or UVP faults (normal operation)
Note that asserting either RESET_AB or RESET_CD
low forces the SD signal high, independent of faults
being present. TI recommends monitoring the OTW
signal using the system microcontroller and
responding to an overtemperature warning signal by,
e.g., turning down the volume to prevent further
heating of the device resulting in device shutdown
(OTE).
To reduce external component count, an internal
pullup resistor to 3.3 V is provided on both SD and
OTW outputs. Level compliance for 5-V logic can be
obtained by adding external pullup resistors to 5 V
(see the Electrical Characteristics section of this data
sheet for further specifications).
DEVICE PROTECTION SYSTEM
The TAS5142 contains advanced protection circuitry
carefully designed to facilitate system integration and
ease of use, as well as to safeguard the device from
permanent failure due to a wide range of fault
conditions such as short circuits, overload,
overtemperature, and undervoltage. The TAS5142
responds to a fault by immediately setting the power
stage in a high-impedance (Hi-Z) state and asserting
the SD pin low. In situations other than overload, the
device automatically recovers when the fault
condition has been removed, i.e., the junction
in
High-Modulation-Index
This device requires at least 50 ns of low time on the
output per 384-kHz PWM frame rate in order to keep
the bootstrap capacitors charged. As an example, if
the modulation index is set to 99.2% in the TAS5508,
this setting allows PWM pulse durations down to 20
ns. This signal, which does not meet the 50-ns
requirement, is sent to the PWM_X pin and this
low-state pulse time does not allow the bootstrap
capacitor to stay charged. In this situation, the low
voltage across the bootstrap capacitor can cause a
failure of the high-side MOSFET transistor, especially
when driving a low-impedance load. The TAS5142
device requires limiting the TAS5508 modulation
index to 96.1% to keep the bootstrap capacitor
charged under all signals and loads.
Therefore, TI strongly recommends using a TI PWM
processor, such as TAS5508 or TAS5086, with the
modulation index set at 96.1% to interface with
TAS5142.
Overcurrent (OC) Protection
Limiting and Overload Detection
With
Current
The device has independent, fast-reacting current
detectors with programmable trip threshold (OC
threshold) on all high-side and low-side power-stage
FETs. See the following table for OC-adjust resistor
values. The detector outputs are closely monitored by
two protection systems. The first protection system
controls the power stage in order to prevent the
output current from further increasing, i.e., it performs
a current-limiting function rather than prematurely
shutting down during combinations of high-level
music transients and extreme speaker load
impedance drops. If the high-current situation
persists, i.e., the power stage is being overloaded, a
second protection system triggers a latching
shutdown, resulting in the power stage being set in
the high-impedance (Hi-Z) state. Current limiting and
overload protection are independent for half-bridges
A and B and, respectively, C and D. That is, if the
bridge-tied load between half-bridges A and B causes
an overload fault, only half-bridges A and B are shut
down.
• For the lowest-cost bill of materials in terms of
component selection, the OC threshold measure
should be limited, considering the power output
requirement and minimum load impedance.
Higher-impedance loads require a lower OC
threshold.
21
TAS5142
www.ti.com
SLES126B – DECEMBER 2004 – REVISED MAY 2005
•
The demodulation-filter inductor must retain at
least 5 µH of inductance at twice the OC
threshold setting.
Unfortunately, most inductors have decreasing
inductance with increasing temperature and
increasing current (saturation). To some degree, an
increase in temperature naturally occurs when
operating at high output currents, due to core losses
and the dc resistance of the inductor's copper
winding. A thorough analysis of inductor saturation
and thermal properties is strongly recommended.
Setting the OC threshold too low might cause issues
such as lack of enough output power and/or
unexpected shutdowns due to too-sensitive overload
detection.
In general, it is recommended to follow closely the
external component selection and PCB layout as
given in the Application section.
For added flexibility, the OC threshold is
programmable within a limited range using a single
external resistor connected between the OC_ADJ pin
and AGND. (See the Electrical Characteristics section
of this data sheet for information on the correlation
between programming-resistor value and the OC
threshold.) It should be noted that a properly
functioning overcurrent detector assumes the
presence of a properly designed demodulation filter at
the power-stage output. Short-circuit protection is not
provided directly at the output pins of the power stage
but only on the speaker terminals (after the
demodulation filter). It is required to follow certain
guidelines when selecting the OC threshold and an
appropriate demodulation inductor:
OC-Adjust Resistor Values
(kΩ)
Max. Current Before OC Occurs
(A)
22
9.4
27
8.6
39
6.4
47
6
69
4.7
Overtemperature Protection
The TAS5142 has a two-level temperature-protection
system that asserts an active-low warning signal
(OTW) when the device junction temperature
exceeds 125°C (nominal) and, if the device junction
temperature exceeds 155°C (nominal), the device is
22
put into thermal shutdown, resulting in all half-bridge
outputs being set in the high-impedance (Hi-Z) state
and SD being asserted low. OTE is latched in this
case. To clear the OTE latch, both RESET_AB and
RESET_CD must be asserted. Thereafter, the device
resumes normal operation.
Undervoltage Protection (UVP) and Power-On
Reset (POR)
The UVP and POR circuits of the TAS5142 fully
protect the device in any power-up/down and
brownout situation. While powering up, the POR
circuit resets the overload circuit (OLP) and ensures
that all circuits are fully operational when the
GVDD_X and VDD supply voltages reach 9.8 V
(typical). Although GVDD_X and VDD are
independently monitored, a supply voltage drop
below the UVP threshold on any VDD or GVDD_X
pin results in all half-bridge outputs immediately being
set in the high-impedance (Hi-Z) state and SD being
asserted low. The device automatically resumes
operation when all supply voltages have increased
above the UVP threshold.
DEVICE RESET
Two reset pins are provided for independent control
of half-bridges A/B and C/D. When RESET_AB is
asserted low, all four power-stage FETs in half-bridges A and B are forced into a high-impedance
(Hi-Z) state. Likewise, asserting RESET_CD low
forces all four power-stage FETs in half-bridges C
and D into a high-impedance state. Thus, both reset
pins are well suited for hard-muting the power stage if
needed.
In BTL modes, to accommodate bootstrap charging
prior to switching start, asserting the reset inputs low
enables weak pulldown of the half-bridge outputs. In
the SE mode, the weak pulldowns are not enabled,
and it is therefore recommended to ensure bootstrap
capacitor charging by providing a low pulse on the
PWM inputs when reset is asserted high.
Asserting either reset input low removes any fault
information to be signalled on the SD output, i.e., SD
is forced high.
A rising-edge transition on either reset input allows
the device to resume operation after an overload
fault.
PACKAGE OPTION ADDENDUM
www.ti.com
11-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TAS5142DDV
ACTIVE
HTSSOP
DDV
44
35
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
TAS5142DDVG4
ACTIVE
HTSSOP
DDV
44
35
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
TAS5142DDVR
ACTIVE
HTSSOP
DDV
44
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
TAS5142DDVRG4
ACTIVE
HTSSOP
DDV
44
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
TAS5142DKD
ACTIVE
SSOP
DKD
36
29
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
TAS5142DKDG4
ACTIVE
SSOP
DKD
36
29
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
TAS5142DKDR
ACTIVE
SSOP
DKD
36
500
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
TAS5142DKDRG4
ACTIVE
SSOP
DKD
36
500
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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