FREESCALE MC34923DWR2

Freescale Semiconductor, Inc.
MOTOROLA
Order this document from Analog Marketing: MC34923/D
Rev 0, 05/2003
SEMICONDUCTOR TECHNICAL DATA
Preliminary Information
34923
Full-Bridge PWM Motor Driver
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Designed with Motorola’s advanced SMARTMOS, the 34923 is designed for
pulse-width modulated (PWM) current control of DC motors. It is capable of
continuous output currents up to 2.0 A and operating voltages of up to 45 V.
Internal fixed off-time PWM current-control timing circuitry can be programmed
via a serial interface to operate in slow, fast, and mixed current-decay modes.
FULL-BRIDGE PWM MOTOR
DRIVER
DIR and PWM/ENABLE input pins are provided for use in controlling the
speed and direction of a DC motor with externally applied PWM-control
signals. The PWM/ENABLE input can be programmed via the serial port to
PWM the bridge in fast or slow current decay. Internal synchronous
rectification control circuitry is provided to reduce power dissipation during
PWM operation.
Internal circuit protection includes thermal shutdown with hysteresis and
crossover-current protection. A special power-up sequencing is not required.
Features
• ±2.0 A, 45 V Continuous Output Rating
• Low RDS(ON) Outputs (270 mΩ, typical)
• Programmable Mixed, Fast, and Slow Current-Decay Modes
• Serial Interface Controls Chip Functions
• Synchronous Rectification for Low Power Dissipation
• Internal Undervoltage Lockout Thermal Shutdown Circuitry
• Crossover-Current Protection
DW SUFFIX
24-LEAD SOICW
CASE 751E-04
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
MC34923DW/R2
-40 to 125°C
24 SOICW
34923 Simplified Application Diagram
≤ 5.0 V
5.0 V
34923
PWMMODE
DIR
DCMA
PWM/ENABLE
MCU
Serial
Port
DC
Motor
CLOCK
DATA
STROBE
DCMB
OSC
GND
This document contains information on a product under development.
Motorola reserves the right to change or discontinue this product without notice.
© Motorola, Inc. 2003
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≤ 45 V
Bandgap
VDD
Thermal Shutdown
Undervoltage
and
Fault Detect
OSC
(160 kHz)
VB
VDD
CP2
CP1
5.0 V
VBB
Bandgap
Regulator
Charge
Pump
VREG
Control Logic
DIR
PWM/ENABLE
OSC
CLOCK
DATA
STROBE
DCMA
Direction
Enable
Sync. Rect.Control
Internal PWM Mode
External PWM Mode
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PWMMODE
Programmable
PWM Timer
Gate
Drive
Motor
DCMB
SENSE
Current
Sense
Serial Port
CS
Zero
Current
Detect
Fixed-Off
Blank
Decay
Sleep Mode
RS
Reference
Buffer and
Divider
VREF
Load Current
Reference
SPAN
Figure 1. 34923 Simplified Block Diagram
34923
2
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.
VB
CP2
CP1
DIR
OSC
GND
GND
VDD
PWM/ENABLE
DATA
CLOCK
STROBE
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VREG
SPAN
NC
DCMB
VBB
GND
GND
SENSE
DCMA
NC
PWMMODE
VREF
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PIN FUNCTION DESCRIPTION
Pin
Pin Name
Formal Name
Definition
1
VB
Boost Voltage
2
CP2
Switching Capacitor 2
Charge pump capacitor connection 2.
3
CP1
Switching Capacitor 1
Charge pump capacitor connection 1.
4
DIR
Direction
Logic-level input for direction control.
5
OSC
Oscillator
Logic-level oscillator (square wave) input.
6, 7, 18, 19
GND
Ground
8
VDD
Logic Voltage
9
PWM/ENABLE
H-Bridge Enable
10
DATA
Serial Data
11
CLOCK
Serial Data Clock
12
STROBE
Serial Data Latch Strobe
Logic-level input for serial port (active on rising edge).
13
VREF
Current Limit Reference
Voltage
Load current reference input voltage.
Boost voltage storage node.
Ground.
Low voltage (typically 5.0 V) logic supply.
Logic-level input for enabling the H-bridge driver.
Logic-level input for serial interface.
Logic-level input for serial port (data is entered on rising edge).
14
PWMMODE
PWM Mode Control
15, 22
NC
No Connect
16
DCMA
H-Bridge Output A
17
SENSE
Current Sense
20
VBB
H-Bridge Voltage Supply
High-current (20 V to 45 V) load supply.
21
DCMB
H-Bridge Output B
One of two bridge outputs to the motor.
23
SPAN
Current Limit Reference Range
Logic-level input for VREF range control.
24
VREG
Bandgap Voltage
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Logic-level input for PWM mode control when in internal PWM mode.
No internal connection to this pin.
One of two bridge outputs to the motor.
Sense resistor.
Bandgap decoupling capacitor.
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MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
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Rating
Symbol
Value
Unit
Load Supply Voltage
VBB
48
V
Logic Supply Voltage
VDD
7.0
V
Input Voltage
VIN
-0.3 to VDD + 0.3
V
Sense Voltage
VS
0.5
V
Reference Voltage
VREF
2.7
V
Output Current (Note 1)
IOUT
±2.0
A
Storage Temperature
TS
-55 to 150
°C
Ambient Temperature
TA
-20 to 85
°C
Operating Junction Temperature
TJ
-40 to 150
°C
Power Dissipation (TA = 25°C) (Note 2)
PD
1.6 (Note 3)
W
VESD1
±2000
VESD2
±200
TSOLDER
260
°C
RθJA
56
°C/W
V
ESD Voltage
Human Body Model (Note 4)
Machine Model (Note 5)
Lead Soldering Temperature (Note 6)
Thermal Resistance Junction-to-Ambient (Note 2)
Notes
1. Output current rating may be limited by duty cycle, ambient temperature, and heatsinking. Under any set of conditions, do not exceed the
specified current rating or a junction temperature of 150°C.
2. Maximum power dissipation at indicated ambient temperature in free air with no heatsink used.
3. Per SEMI G42-88 specification.
4. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).
5.
ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
6.
Lead soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
34923
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STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions TA = 25°C, VBB = 45 V, VDD = 5.0 V, VSENSE = 0.5 V, and fPWM < 50 kHz unless otherwise
noted.
Characteristic
Symbol
Min
Typ
Max
Operating
20
–
45
During Sleep Mode
0
–
45
VOUT = VBB
–
<1.0
20
VOUT = 0 V
–
<-1.0
-20
Source Driver, IOUT = -2.0 A @ 25°C
–
300
450
Source Driver, IOUT = -2.0 A @ 150°C
–
–
700
Sink Driver, IOUT = 2.0 A @ 25°C
–
300
450
Sink Driver, IOUT = 2.0 A @ 150°C
–
–
700
Unit
OUTPUT DRIVERS
VBB
Load Supply Voltage Range
µA
IDSS
Output Leakage Current
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V
mΩ
RDS(ON)
Output On Resistance
V
VF
Body Diode Forward Voltage
Source Diode, IF = -2.0 A
–
1.2
1.6
Sink Diode, IF = 2.0 A
–
1.2
1.6
fPWM < 50 kHz
–
4.0
7.0
mA
Charge Pump On, Outputs Disabled
–
2.0
5.0
mA
Sleep Mode
–
–
20
µA
VDD
4.5
5.0
5.5
V
VIN(1)
2.0
–
–
VIN(0)
–
–
0.8
IBB
Load Supply Current
CONTROL LOGIC
Logic Supply Voltage Range (Operating)
V
Logic Input Voltage
µA
Input Current
All Logic Inputs Except PWM/ENABLE
VIN = 2.0 V
IIN(1)
–
<1.0
20
VIN = 0.8 V
IIN(0)
–
<-2.0
-20
VIN = 2.0 V
IIN(1)
–
40
100
VIN = 0.8 V
IIN(0)
–
16
40
∆VIN(LOGIC)
50
–
100
∆VIN(OSC)
200
–
400
Reference Input Voltage Range (Operating)
VREF
0
–
2.6
Reference Input Current
IREF
–
–
±0.5
Comparator VREF = 0 V
–
0
±5.0
Buffer
–
0
±15
PWM/ENABLE Only
mV
Input Hysteresis
All Digital Inputs Except OSC
OSC (Operating)
VREF = 2.5 V
µA
mV
VIO
Input Offset Voltage
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V
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions TA = 25°C, VBB = 45 V, VDD = 5.0 V, VSENSE = 0.5 V, and fPWM < 50 kHz unless otherwise
noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Bit D14 = High
9.9
10
10.2
Bit D14 = Low
4.95
5.0
5.05
TJ
–
165
–
°C
∆TJ
–
15
–
°C
3.90
4.2
4.45
0.05
0.10
–
fPMW < 50 kHz
–
6.0
10
Sleep Mode, Inputs <0.5 V
–
–
2.0
CONTROL LOGIC (continued)
Reference Divider Ratio
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
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Undervoltage Lockout Enable Threshold
–
UVLO
Increasing VDD
Undervoltage Lockout Hysteresis
Logic Supply Current
34923
6
–
∆UVLO
V
V
mA
IDD
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DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions TA = 25°C, VBB = 45 V, VDD = 5.0 V, VSENSE = 0.5 V, and fPWM < 50 kHz unless otherwise
noted.
Characteristic
Symbol
Min
Typ
Max
Unit
OSC Input Frequency (Operating)
f OSC
2.9
–
6.1
MHz
OSC Input Duty Cycle (Operating)
dc OSC
40
–
60
%
PWM Change to Source ON
–
600
–
PWM Change to Source OFF
–
100
–
PWM Change to Sink ON
–
600
–
PWM Change to Sink OFF
–
100
–
Direction Change to Sink ON
–
600
–
Direction Change to Sink OFF
–
100
–
Direction Change to Source ON
–
600
–
Direction Change to Source OFF
–
100
–
CONTROL LOGIC
t pd
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Propagation Delay Times
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ns
34923
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Timing Diagram
STROBE
C
D
E
F
G
CLOCK
A
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DATA
B
D19
D18
D0
Legend
ID
Description
Value (ns)
ID
Description
Value (ns)
A
B
C
D
DATA Setup Time
DATA Hold Time
Setup STROBE-to-CLOCK Rising Edge
CLOCK High Pulse Width
15
10
50
50
E
F
G
CLOCK Low Pulse Width
Setup CLOCK Rising Edge-to-STROBE
STROBE Pulse Width
50
50
50
Figure 2. Serial Port Write Timing
34923
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 34923 is designed for pulse-width modulated (PWM)
current control of DC motors. It is capable of continuous output
currents up to 2.0 A and operating voltages of up to 45 V.
Internal fixed off-time PWM current-control timing circuitry can
be programmed via a serial interface to operate in slow, fast,
and mixed current decay modes.
DIR and PWM/ENABLE input pins are provided for use in
controlling the speed and direction of a DC motor with externally
applied PWM-control signals. The PWM/ENABLE input can be
programmed via the serial port to PWM the bridge in fast or slow
current decay. Internal synchronous rectification control
circuitry is provided to reduce power dissipation during PWM
operation.
Internal circuit protection includes thermal shutdown with
hysteresis and crossover-current protection. Special power-up
sequencing is not required.
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FUNCTIONAL PIN DESCRIPTION
VB
DATA
This logic input is the serial data used by the serial interface.
This pin provides a node for charge storage at the boost
voltage. Internal circuitry will draw VB current from this node,
and the charge pump will deliver charge to this node.
CLOCK
CP1 and CP2
This logic input is the clock for the serial interface. Data is
shifted in synchronously with this clock.
These pins are the connections to the switching capacitor in
the charge pump. These pins swing between ground and VB,
drawing charge from VBB and delivering it to the VB node.
STROBE
This logic input is used to latch data from the serial interface
into the internal logic.
DIR
This is the direction input for the H-bridge driver.
VREF
This input provides a reference voltage for the current limit
comparator threshold.
PWM/ENABLE
This pin is the enable input for the H-bridge driver. When
asserted this will bring the H-bridge out of tri-state mode so that
it can drive a load.
DCMA and DCMB
These are the high-current, high-voltage drive signals for the
motor.
PWMMODE
This logic input controls the H-bridge output mode when the
PWM is deasserted. The H-bridge can have an active or
passive output state when the PWM input is deasserted.
VBB
This is the motor drive voltage input. The H-bridge will deliver
this voltage to the motor.
OSC
SPAN
This logic input is the clock for the on-board decay time
generator used only when in internal PWM mode. The decay
time can be slow or mixed fast and slow.
This logic-level input controls the current limit comparator
threshold that is generated from VREF.
VREG
VDD
This is the power supply input for the internal logic and
several other functions.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
This output is a decoupling node for the internal bandgap
reference voltage generator.
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FUNCTIONAL DESCRIPTION
Serial Interface
D2–D6, Fixed Off-Time
The 34923 is controlled via a 3-wire (clock, data, strobe)
serial port. The programmable functions allow maximum
flexibility in configuring the PWM to the motor drive
requirements. The serial data is clocked in starting with bit D19.
A five-bit word sets the fixed off-time for internal PWM
current control. The off time is defined as follows:
Bit
Function
D0
Blank Time LSB
where N = 0 to 31.
For example, with an oscillator frequency of 4.0 MHz, the offtime is adjusted from 1.75 µs to 63.75 µs in increments of
2.0 µs.
D1
Blank Time MSB
D2
Fixed Off-Time LSB
D3
Fixed Off-Time Bit 1
D7–D10, Fast Decay Time
D4
Fixed Off-Time Bit 2
D5
Fixed Off-Time Bit 3
D6
Fixed Off-Time MSB
D7
Fast Decay Time LSB
D8
Fast Decay Time Bit 1
A four-bit word sets the fast decay portion of the fixed off-time
for the internal PWM control circuitry. This will only have impact
if the mixed current decay mode is selected (via bit D17 and the
PWMMODE input pin). For t fd > t off, the device will effectively
operate in the fast decay mode. The fast decay portion is
defined as follows:
D9
Fast Decay Time Bit 2
t fd = (8[1 + N]/f osc) - 1/fosc
D10
Fast Decay Time MSB
D11
Synchronous Rectification Mode
D12
Synchronous Rectification Enable
D13
External PWM Decay Mode
D14
Enable Logic
D15
Direction Logic
D16
Divisor SPAN Select
D17
Internal PWM Mode
D18
Test Mode
D19
Sleep Mode
D0–D1, Blank Time
The current-sense comparator is blanked when any output
driver is switched on in accordance with the table below. fosc is
the oscillator input frequency.
34923
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t off = (8[1 + N] /fosc) - 1/f osc
where N = 0 to 15.
For example, with an oscillator frequency of 4.0 MHz, the fast
decay time is adjusted from 1.75 µs to 31.75 µs in increments
of 2.0 µs.
D11–D12, Synchronous Rectification Control
The active mode prevents reversal of load current by turning
off synchronous rectification when a zero current level is
detected. The passive mode will allow reversal of current but
will turn off the synchronous rectifier circuit if the load current
inversion ramps up to the current limit set by VREF /RS.
D11
D12
Synchronous
Rect. Control
0
0
Disabled
0
1
Active
1
0
Disabled
1
1
Passive
D0
D1
Blank Time
0
0
4/f osc
1
0
6/f osc
D13, External PWM Decay Mode
0
1
12/f osc
1
1
24/f osc
Bit D13 determines the current decay mode when using
PWM/ENABLE chopping for external PWM current control.
D13
Current
Decay Mode
0
Fast
1
Slow
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D14, Enable Logic
D19, Sleep Mode
Bit D14, in conjunction with the PWM/ENABLE pin,
determines if the output drivers are in the chopped (OFF) or ON
state.
Bit D19 selects a Sleep mode to minimize power
consumption when not in use. This disables much of the
internal circuitry, including the regulator and charge pump. On
power-up the serial port is initialized to all zeros. Bit D19 should
be programmed high for 1.0 ms before attempting to enable any
output driver.
PWM/
ENABLE
D14
0
0
1
1
1
0
0
1
Operating
Mode
Chopped
D19
Sleep Mode
0
Sleep
1
Normal
ON
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Serial Port Write Timing Operations
D15, Direction Logic
Bit D15, in conjunction with the DIR pin, determines if the
device is operating in the forward or reverse state.
State
DIR
D15
0
0
1
1
1
0
0
1
Reverse
Forward
DCMA
DCMB
Low
High
High
Low
Data is clocked into the shift register on the rising edge of the
CLOCK signal. Normally STROBE will be held high, only
brought low to initiate a write cycle. Refer to Figure 2, Serial Port
Write Timing, page 8, for the minimum timing requirements.
VREG
This internally generated voltage is used to operate the sinkside outputs. The VREG pin should be decoupled with a 0.22 µF
capacitor to ground. VREG is internally monitored and, in the
case of a fault condition, the outputs of the device are disabled.
D16, Divisor SPAN Select
Charge Pump
Bit D16, in conjunction with the SPAN pin, determines if VREF
is divided by 5 or 10.
Divisor
SPAN
D16
1
0
0
1
0
0
The charge pump is used to generate a gate supply voltage
greater than VBB to drive the source-side gates. A 0.22 µF
ceramic capacitor should be connected between CP1 and CP2
for pumping purposes. A 0.22 µF ceramic capacitor should be
connected between VB and VBB to act as a reservoir to operate
the high-side devices. The VB voltage is internally monitored
and, in the case of a fault condition, the source outputs of the
device are disabled.
1
1
Shutdown
÷5
÷10
D17, Internal PWM Mode
Bit D17, in conjunction with the PWMMODE pin, selects
mixed or slow current decay.
PWMMODE
D17
0
0
1
1
1
0
0
1
Current
Decay Mode
Mixed
Slow
D18, Test Mode
Bit D18 low (default) operates the device in normal mode.
D18 is only used for testing purposes. The user should never
change this bit.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
In the event of a fault (excessive junction temperature or low
voltage on VB or VREG), the outputs of the device are disabled
until the fault condition is removed. At power-up, and in the
event of low VDD, the Undervoltage Lockout circuit disables the
drivers and resets the data in the serial port to all zeros.
PWM Timer Function
The PWM timer is programmable via the serial port (bits D2–
D10) to provide off-time PWM signals to the control circuitry. In
the mixed current-decay mode, the first portion of the off time
operates in fast decay, until the fast decay time count (serial bits
D7–D10) is reached, followed by slow decay for the rest of the
off-time period (bits D2–D6). If the fast decay time is set longer
than the off time, the device effectively operates in fast decay
mode. Bit D17, in conjunction with PWMMODE, selects mixed
or slow decay.
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PWM Blank Timer
Current Regulation
When a source driver turns on, a current spike occurs owing
to the reverse recovery currents of the clamp diodes and/or
switching transients related to distributed capacitance in the
load. To prevent this current spike from erroneously resetting
the source-enable latch, the sense comparator is blanked. The
blank timer runs after the off-time counter (see bits D2–D6) to
provide the programmable blanking function. The blank timer is
reset when PWM/ENABLE is chopped or DIR is changed. For
external PWM control, a DIR change or PWM/ENABLE on will
trigger the blanking function.
Load current is regulated by an internal fixed off-time PWM
control circuit. When the outputs of the H-bridge are turned on,
the current increases in the motor winding until it reaches a trip
value determined by the external sense resistor (RS), the
applied analog reference voltage (VREF), the SPAN logic level,
and serial data bit D16:
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Synchronous Rectification
When a PWM off cycle is triggered, either by an PWM/
ENABLE chop command or internal fixed off-time cycle, load
current will recirculate according to the decay mode selected by
the control logic. The 34923 synchronous rectification feature
will turn on the opposite pair of outputs during the current decay
and effectively short out the body diodes with the low RDS(ON)
driver. This will reduce power dissipation significantly and can
eliminate the need for external Schottky diodes.
Synchronous rectification can be configured in active mode,
passive mode, or disabled via the serial port (bits D11 and
D12).
When SPAN = D16, ITRIP = VREF /10RS
When SPAN ≠ D16, ITRIP = VREF /5RS
At the trip point, the sense comparator resets the sourceenable latch, turning off the source driver. The load inductance
then causes the current to recirculate for the serial-portprogrammed fixed off-time period. The current path during
recirculation is determined by the configuration of slow/mixed
current-decay mode (D17) and the synchronous rectification
control bits (D11 and D12).
Internal PWM (Current Mode) PWM Frequency
The internal PWM opeating frequency is set by the sum of
“Off Time”, as determined by bits D2 through D6, “Blank Time”,
as determined by bits D0 and D1, and the time constant of the
motor.
The active or passive mode selection has no impact in slowdecay mode. With synchronous rectification enabled, the slowdecay mode serves as an effective brake mode.
34923
12
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APPLICATIONS
Current Sensing
Layout
To minimize inaccuracies in sensing the ITRIP current level,
which may be caused by ground trace IR drops, the sense
resistor should have an independent ground return to the
ground pin of the device. For low-value sense resistors, the IR
drops in the PCB sense resistor’s traces can be significant and
should be taken into account. The use of sockets should be
avoided because they can introduce variation in RS owing to
their contact resistance.
The printed wiring board should use a heavy ground plane.
For optimum electrical and thermal performance (see following
Note), the driver should be soldered directly onto the board. The
ground side of RS should have an individual path to the ground
pins of the device. This path should be as short as is possible
physically and should not have any other components
connected to it. It is recommended that a 0.1 µF capacitor be
placed between SENSE and ground as close to the device as
possible; the load supply pin, VBB, should be decoupled with an
electrolytic capacitor (>47 µF is recommended) placed as close
to the device as is possible.
Braking
The braking function is implemented by driving the device in
slow-decay mode via serial port bit D13, enabling synchronous
rectification via bit D12, and chopping with the combination of
D14 and the PWM/ENABLE input pin. Because it is possible to
drive current in either direction through the drivers, this
configuration effectively shorts out the motor-generated back
EMF (BEMF) as long as the PWM/ENABLE chop mode is
asserted. It is important to note that the internal PWM currentcontrol circuit will not limit the current when braking, because
the current does not flow through the sense resistor. The
maximum brake current can be approximated by VBEMF/RL.
Care should be taken to ensure that the maximum ratings of the
device are not exceeded in worst-case braking situations of
high-speed and high-inertial loads.
Thermal Protection
Circuitry turns off all drivers when the junction temperature
reaches 165°C typically. It is intended only to protect the device
from failures owing to excessive junction temperatures and
should not imply that output short circuits are permitted.
Thermal shutdown has a hysteresis of approximately 15°C.
Note The thermal resistance and absolute maximum
allowable package power dissipation specified in the
MAXIMUM RATINGS table, page 4, is measured on typical
two-sided PCB with minimal copper ground area. For the
34923, RθJA can be reduced to 56°C/W with 3.57-in2 copper
ground area, as shown in Figure 3.
ALLOWABLE PACKAGE POWER DISSIPATION WATTS
Freescale Semiconductor, Inc...
The maximum value of RS is given as RS ≤ 0.5/ITRIP.
5
4
3
2
RθJA = 56°C/W
1
0
25
50
75
100
125
150
TEMPERATURE (°C)
Figure 3. Package Dissipation Temperature Derating
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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34923
13
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PACKAGE DIMENSIONS
DW SUFFIX
24-LEAD SOIC WIDE BODY
PLASTIC PACKAGE
CASE 751E-04
ISSUE E
-A24
-B-
12X
P
0.010 (0.25)
1
Freescale Semiconductor, Inc...
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM MATERIAL
CONDITION.
13
M
B
M
12
24X
D
J
0.010 (0.25)
M
T A
S
B
S
F
R
C
-TSEATING
PLANE
34923
14
M
22X
G
K
X 45 °
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
15.25
15.54
7.40
7.60
2.35
2.65
0.35
0.49
0.41
0.90
1.27 BSC
0.23
0.32
0.13
0.29
0°
8°
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.601
0.612
0.292
0.299
0.093
0.104
0.014
0.019
0.016
0.035
0.050 BSC
0.009
0.013
0.005
0.011
0°
8°
0.395
0.415
0.010
0.029
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
NOTES
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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34923
15
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
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MC34923/D