FUJITSU SEMICONDUCTOR DATA SHEET DS06-20211-1E Semicustom CMOS Standard Cell CS201 Series ■ DESCRIPTION The CS201 series of 65 nm standard cells is a line of CMOS ASICs that satisfy demands for lower power consumption and higher integration. These cells offer the minimum level of leakage current in the semiconductor industry, and are able to implement a mixture of core transistors with three different threshold voltages, as appropriate for the applications ranging from handheld terminals to digital audiovisual equipment. The integration level in this series is twice the previous series with lower power consumption. ■ FEATURES • Technology • • • • • • • • • • • • • • • • : 65 nm Si gate CMOS : 6 to 12 layers of metal wiring. Ultra Low-K (low permittivity) material is used for dielectric inter-layers. Three different types of core transistors (low leak, standard and high speed) can be used on the same chip. Power supply voltage : Supports a wide range from + 0.9 V to + 1.3 V Operation junction temperature : − 40 °C to + 125 °C (standard) Gate delay time : 11 ps (1.2 V, Inverter, F/O = 1) Gate power consumption : 1.77 nW/gate (operating condition: 1.2 V, operating rate 0.5, 1 MHz) Reduced chip size achieved by creating the wire bonding pads within the I/O macro regions. Support various cell sets (from low power versions to high speed versions) Compiled cell (RAM, ROM, others) Support large capacity memory “1T-SRAM-Q ®”*1 “1T-SRAM-Q ®” is the embedded memory which enable maximum 128Mbit. Support low-consumption technology “ CoolAdjustTM ”*2 Support ultra high speed (up to 10 Gbps) interface macros Special interfaces (LVDS, SSTL, others) Short-term development using a physical prototyping tool One pass design using a physical synthesis tool Hierarchical design environment for supporting large-scale circuits Support Signal Integrity, EMI noise reduction Support static timing sign-off (Continued) Copyright©2007 FUJITSU LIMITED All rights reserved CS201 Series (Continued) • Improve timing convergence by using Statistical Static Timing Analysis (SSTA) • Design For Manufacturing (DFM) enables stable product-supply and reduced variation • Optimum package range : FBGA, PBGA, TEBGA, FC-BGA *1: To realize this memory, the “1T-SRAM-Q ®” technology by MoSys Inc. was used *2: “CoolAdjust TM” is low power solution presented by Fujitsu. Note : Some of the features are not available yet. ■ MACRO LIBRARIES (including macros currently being prepared) 1. Logic cells (about 400 types) Library sets having three different threshold voltages of core transistors. • Adder • AND • AND-OR • AND-OR Inverter • Buffer • Clock Buffer • Decoder • Delay Buffer • ENOR • EOR • Inverter • Latch • NAND • NOR • OR • OR-AND • OR-AND Inverter • SCAN Flip flop • Non-SCAN Flip Flop • Multiplexer • Others 2. IP macros The following macros will be made available for the CS201 series. CPU/DSP ARM™* cores(ARM7/ARM9/ARM11),Peripherals IP Mixed signal macro ADC, DAC, OPAMP, others Compiled macro SRAM (1 Port, 2 Port), 1 ROM, product sum calculators Large capacity memory 1T-SRAM-Q ® PLL Analog PLL * : ARM is the trademark of ARM Limited. 3. Special I/O interface macro 2 Interface macro (PHY) LVDS, SSTL2, SSTL18, PCI, I2C, others Interface macro (controller) USB2.0 Device/host, Serial ATA, PCI-Express, DDR2, HDMI, others CS201 Series ■ COMPILED CELL Compiled cells are macro cells that can be automatically generated by specifying the bit/word configuration. The following compiled cells are available for the CS201 series (Note that the bit/word ranges for each macro vary depending on the column type). 1. Clock synchronous single-port RAM (1 address : 1 read/write) Column type Memory capacity (bit) Word range (word) Bit range (bit) 2 16 to 160 K 16 to 1 K 1 to 160 4 32 to 640 K 32 to 8 K 1 to 80 8 64 to 640 K 64 to 16 K 1 to 40 2. Clock synchronous dual port RAM (2 address: 2 read/write) Column type Memory capacity (bit) Word range (word) Bit range (bit) 4 64 to 72 K 32 to 1K 2 to 72 Column type Memory capacity (bit) Word range (word) Bit range (bit) 16 256 to 1M 128 to 8 K 2 to 128 64 1K to 1M 512 to 32 K 2 to 32 3. Clock synchronous ROM 4. Clock synchronous register file (2 address : 1 read, 1 write) Column type Memory capacity (bit) Word range (word) Bit range (bit) 1 16 to 1152 8 2 to 144 1 32 to 18 K 16 to 128 2 to 144 3 CS201 Series ■ ABSOLUTE MAXIMUM RATINGS Parameter Power supply voltage*1 Input voltage* 1 Output voltage*1 Symbol VDD VI VO Rating Unit Remarks Min Max − 0.5 + 1.8 − 0.5 + 2.5 (TBD) − 0.5 + 3.6 (TBD) − 0.5 + 4.6 *5 − 0.5 VDD + 0.5 ( ≤ 2.5 V) *3 − 0.5 VDD + 0.5 ( ≤ 3.6 V) − 0.5 VDD + 0.5 ( ≤ 4.6 V) *5 − 0.5 VDD + 0.5 ( ≤ 2.5 V) *3 − 0.5 VDD + 0.5 ( ≤ 3.6 V) − 0.5 VDD + 0.5 ( ≤ 4.6 V) *2 V V V *3 *4 *4 *4 *5 Storage temperature TST − 55 + 125 °C Operation junction temperature Tj − 40 + 125 °C Output current*6 IO ⎯ 15 mA Power supply pin current ID ⎯ 40 mA *1 : VSS = 0 V *2 : Internal gates *3 : 1.8 V interface on dual-power supply system *4 : 2.5 V interface on dual-power supply system *5 : 3.3 V interface on dual-power supply system *6 : The output current varies depending on the number of wiring layers in the chip and the wiring configuration of the I/O cells. Contact your Fujitsu representative for details. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 4 CS201 Series ■ RECOMMENDED OPERATING CONDITIONS • Dual power supply (under planning) (VDDE = 1.8 V ± 0.15 V, VDDI = 1.0 V ± 0.1 V/VDDI = 1.2 V ± 0.1 V) Parameter Symbol VDDE Power supply voltage H level input voltage L level input voltage 1.8 V CMOS Normal 1.8 V CMOS Schmitt 1.8 V CMOS Normal 1.8 V CMOS Schmitt VDDI VIH VIL (VSS = 0 V) Value Unit Min Typ Max 1.65 1.8 1.95 V 0.9 1.0 1.1 V 1.1 1.2 1.3 V VDDE × 0.65 ⎯ VDDE + 0.3 V VDDE × 0.70 ⎯ VDDE + 0.3 V − 0.3 ⎯ VDDE × 0.35 V − 0.3 ⎯ VDDE × 0.30 V Schmitt hysteresis voltage VH VDDE × 0.10 ⎯ VDDE × 0.40 V Operation junction temperature Tj − 40 ⎯ + 125 °C • Dual power supply (under planning) (VDDE = 2.5 V ± 0.2 V, VDDI = 1.0 V ± 0.1 V/VDDI = 1.2 V ± 0.1 V) Parameter Symbol VDDE Power supply voltage H level input voltage 2.5 V CMOS Normal L level input voltage 2.5 V CMOS Normal 2.5 V CMOS Schmitt 2.5 V CMOS Schmitt VDDI VIH VIL (VSS = 0 V) Value Unit Min Typ Max 2.3 2.5 2.7 V 0.9 1.0 1.1 V 1.1 1.2 1.3 V 1.7 ⎯ VDDE + 0.3 V 1.7 ⎯ VDDE + 0.3 V − 0.3 ⎯ + 0.7 V − 0.3 ⎯ + 0.7 V Schmitt hysteresis voltage VH 0.2 ⎯ 1.0 V Operation junction temperature Tj − 40 ⎯ + 125 °C 5 CS201 Series • Dual power supply (VDDE = 3.3 V ± 0.3 V, VDDI = 1.0 V ± 0.1 V/VDDI = 1.2 V ± 0.1 V) Parameter Symbol VDDE Power supply voltage H level input voltage L level input voltage 3.3 V CMOS Normal 3.3 V CMOS Schmitt 3.3 V CMOS Normal 3.3 V CMOS Schmitt VDDI VIH VIL (VSS = 0 V) Value Unit Min Typ Max 3.0 3.3 3.6 V 0.9 1.0 1.1 V 1.1 1.2 1.3 V 2.0 ⎯ VDDE + 0.3 V 2.1 ⎯ VDDE + 0.3 V − 0.3 ⎯ + 0.8 V − 0.3 ⎯ + 0.7 V Schmitt hysteresis voltage VH 0.2 ⎯ 1.4 V Operation junction temperature Tj − 40 ⎯ + 125 °C WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 6 CS201 Series ■ ELECTRICAL CHARACTERISTICS • Dual power supply (under planning) (VDDE = 1.8 V ± 0.15 V, VDDI = 1.0 V ± 0.1 V/VDDI = 1.2 V ± 0.1 V) (VDDE = 1.8 V ± 0.15 V, VDDI = 1.0 V ± 0.1 V/VDDI = 1.2 V ± 0.1 V, VSS = 0 V, Tj = − 40 °C to + 125 °C) Value Parameter Symbol Conditions Min Typ Max H level output voltage VOH 1.8 V output IOH = − 100 µA L level output voltage VOL 1.8 V output IOL = 100 µA Input leakage current IL Pull-up/Pull-down resistor Rp ⎯ Pull-up VIL = 0 V Pull-down VIH = VDDE Unit VDDE − 0.2 ⎯ VDDE V 0 ⎯ 0.2 V ⎯ ⎯ ⎯ µA ⎯ 18 ⎯ kΩ • Dual power supply (under planning) (VDDE = 2.5 V ± 0.2 V, VDDI = 1.0 V ± 0.1 V/VDDI = 1.2 V ± 0.1 V) (VDDE = 2.5 V ± 0.2 V, VDDI = 1.0 V ± 0.1 V/VDDI = 1.2 V ± 0.1 V, VSS = 0 V, Tj = − 40 °C to + 125 °C) Value Parameter Symbol Conditions Min Typ Max H level output voltage VOH 2.5 V output IOH = − 100 µA L level output voltage VOL 2.5 V output IOL = 100 µA Input leakage current IL Pull-up/Pull-down resistor Rp ⎯ Pull-up VIL = 0 V/ Pull-down VIH = VDDE Unit VDDE − 0.2 ⎯ VDDE V 0 ⎯ 0.2 V ⎯ ⎯ ⎯ µA ⎯ 25 ⎯ kΩ • Dual power supply (VDDE = 3.3 V ± 0.3 V, VDDI = 1.0 V ± 0.1 V/VDDI = 1.2 V ± 0.1 V) (VDDE = 3.3 V ± 0.3 V, VDDI = 1.0 V ± 0.1 V/VDDI = 1.2 V ± 0.1 V, VSS = 0 V, Tj = − 40 °C to + 125 °C) Value Parameter Symbol Conditions Min Typ Max H level output voltage VOH 3.3 V output IOH = − 100 µA L level output voltage VOL 3.3 V output IOL = 100 µA Input leakage current IL Pull-up/Pull-down resistor Rp ⎯ Pull-up VIL = 0 V/ Pull-down VIH = VDDE Unit VDDE − 0.2 ⎯ VDDE V 0 ⎯ 0.2 V − 10 ⎯ + 10 µA 15 33 70 kΩ 7 CS201 Series ■ DESIGN METHODS Fujitsu’s Reference Design Flow provides the following functions that help reduce the development time of large scale, high quality LSIs. • Statistical Static Timing Analysis (SSTA) improves timing convergence. • Physical Prototyping enables more accurate estimation of highly reliable designs. • Layout synthesis with optimized timing is realized by Physical Synthesis Tool. • High accuracy design environment considers drop in power supply voltage, signal noise, delay penalty and crosstalk. • I/O design environment (power line design, assignment and selection of I/Os, package selection) considers noise. ■ PACKAGES The CS201 series can use the same packages that were available for the previous series, allowing a smooth transition from previously developed models. For details of delivery time, contact Fujitsu. • • • • 8 FBGA packages PBGA packages TEBGA packages FC-BGA packages CS201 Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. 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