FUJITSU SEMICONDUCTOR DATA SHEET DS07-12507-3E 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89810A Series MB89816A/P817A ■ DESCRIPTION The MB89810A series is a line of single-chip microcontrollers based on the F2MC*-8L CPU core which can operate at low voltage but at high speed. The microcontrollers contain peripheral function such as timer, serial interface, a UART, and an external interrupt. The MB89810A series is applicable to a wide range of applications from welfare products to industrial equipment, including portable devices. *: F2MC stands for FUJITSU Flexible Microcontroller. ■ FEATURES High speed processing at low voltage Minimum execution time: 0.8 µs/3.0 V, 1.33 µs/2.2 V • F2MC-8L family CPU core Instruction set optimized for controllers : Multiplication and division instructions 16-bit arithmetic operations Test and branch instructions Bit manipulation instructions, etc. • Four types of timers 8-bit PWM timer: 2 channels (also serve as reload timers) 16-bit timer/counter 21-bit time-base timer (Continued) ■ PACKAGE 64-pin Plastic QFP (FPT-64P-M06) MB89810A Series (Continued) • Two serial interface 8-bit synchronous serial (Switchable transfer direction allows communication with various equipment.) UART (5-, 7-, or 8-bit transfer capable) • External interrupt: 8 channels Eight channels are independent and capable of wake-up from low-power consumption modes (with an edge detection function). • Low-power consumption modes Stop mode (Oscillation stops to minimize the current consumption) Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal) 2 MB89810A Series ■ PRODUCT LINEUP Part number Parameter Classification ROM size MB89816A MB89P817A Mass-production product (mask ROM products) One-time PROM product (for evaluation and development) 24 K × 8 bits (internal mask ROM) 32 K × 8 bits (internal PROM, programming with general-purpose EPROM programmer) 2048 × 8 bits RAM size CPU functions Number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Interrupt processing time: 136 8 bits 1 to 3 bytes 1, 8, 16 bits 0.8 µs/5 MHz 7.2 µs/5 MHz Ports Input ports: Output ports: I/O ports (N-ch open-drain): I/O ports (CMOS): Total: 8 (All also serve as peripherals.) 8 5 (for LED driving) 32 (14 ports also serve as peripherals.) 53 8-bit PWM timer Two internal channels 8-bit reload timer operation (toggled output capable, operating clock cycle: 3 different cycles) 8-bit resolution PWM operation (conversion cycle: 3 different cycles) 8-bit timer/counter UART 8-bit Serial I/O External interrupt 16-bit timer operation 16-bit event counter operation 5-, 7-, or 8-bit transfer capable Built-in baud rate generator Clock synchronous/asynchronous data transfer capable 8-bits LSB-first/MSB first selectability One clock selectable from four transfer clocks (one external shift clock, three internal shift clocks) 8 independent channels (edge selection, interrupt vector, source flag) 4 channels: Level detection (level selectable) 4 channels: Edge detection (edge selectable) Used also for wake-up from the stop/sleep mode. (Edge detection is also permitted in stop mode.) (Continued) 3 MB89810A Series (Continued) Part number Parameter Watch interrupt Watchdog timer reset MB89816A MB89P817A Interrupt cycles: 4 different cycles (subclock) Reset occurrence cycle: 839 ms/5 MHz Standby mode Sleep mode, stop mode Process CMOS Package FPT-64P-M06 Operating voltage 2.2 V to 6.0 V* 2.7 V to 6.0 V* *: Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”) ■ DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the OTPROM (one-time PROM) products, verify its differences from the product that will actually be used. 2. Current Consumption When operated at low speed, the product with an OTPROM will consume more current than the product with a mask ROM. However, the same is current consumption in sleep/stop modes (For more information, see “■ ELECTRICAL CHARACTERISTICS”) . 3. Mask Options Functions that can be selected as options and how to designate these options vary with product. Before using options, check “■ MASK OPTIONS”. Take particular care on the following point: For MB89816A, pull-up resistor option can be set for P50 to P54. 4 MB89810A Series ■ PIN ASSIGNMENT 64 63 62 61 60 59 58 57 56 55 54 53 52 P47/SCL2 P46/RXD2 P45/TXD2 P44/SCL1 P43/RXD1 P42/TXD1 P41/EC VCC P40 P54 P53 P52 P51 (Top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 P50 VSS P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 20 21 22 23 24 25 26 27 28 29 30 31 32 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RST MOD0 MOD1 X0 X1 VSS P27 P26 P25 P24 P23 P22 P21 P30/PWE P31/SCK P32/SO P33/SI P34/PWO P35/PWI P36/PTO1 P37/PTO2 P60/INT0 P61/INT1 P62/INT2 VCC P63/INT3 P64/INT4 P65/INT5 P66/INT6 P67/INT7 X0A X1A (FPT-64P-M06) 5 MB89810A Series ■ PIN DESCRIPTION Pin no. Pin name 23 X0 24 X1 18 X0A 19 X1A 21 MOD0 22 MOD1 20 Circuit type Function A Main clock oscillator pins I Subclock crystal oscillator pins B Operating mode selection pins Connect directly these pins directly to VSS. RST C Reset I/O pin This pin is an N-ch open-drain output type with a pull-up resistor and a hysteresis input type. “L” is output from this pin by an internal reset source. The internal circuit is initialized by the input of “L”. 49 to 42 P00 to P07 D General-purpose I/O ports A pull-up resistor option is provided. These ports have the port output inverting function. 41 to 34 P10 to P17 D General-purpose I/O ports A pull-up resistor option is provided. These ports have the port output inverting function. 33 to 30 P20 to P23 F General-purpose output ports These ports have the port output inverting function. 29 to 26 P24 to P27 F General-purpose output ports 1 P30 /PWE E General-purpose I/O port A pull-up resistor option is provided. Also serves as a pulse width detection enable input (PWE). PWE input is hysteresis input. 2 P31/SCK E General-purpose I/O port A pull-up resistor option is provided. Also serves as the clock I/O for the 8-bit serial I/O (SCK). SCK input is hysteresis input. 3 P32/SO D General-purpose I/O port A pull-up resistor option is provided. Also serves as the data output for the 8-bit serial I/O (SO). 4 P33/SI E General-purpose I/O port A pull-up resistor option is provided. Also serves as the data input for the 8-bit serial I/O (SI). SI input is hysteresis input. 5 P34/PWO D General-purpose I/O port A pull-up resistor option is provided. Also serves as a pulse width detection output (PWO). 6 P35/PWI E General-purpose I/O port A pull-up resistor option is provided. Also serves as a pulse width detection input (PWI). PWI input is hysteresis input. 7 P36/PTO1 D General-purpose I/O port A pull-up resistor option is provided. Also serves as the toggle output for the 8-bit PWM timer 1 (PTO1). (Continued) 6 MB89810A Series (Continued) Pin no. Pin name Circuit type Function 8 P37/PTO2 D General-purpose I/O port A pull-up resistor option is provided. Also serves as the toggle output for the 8-bit PWM timer 2 (PTO2). 56 P40 D General-purpose I/O port A pull-up resistor option is provided. 58 P41/EC E General-purpose I/O port A pull-up resistor option is provided. Also serves as a 16-bit timer/counter input (EC). EC input is hysteresis input. 59 P42/TXD1 D General-purpose I/O port A pull-up resistor option is provided. Also serves as the data output 1 for the UART (TXD1). 60 P43/RXD1 E General-purpose I/O port A pull-up resistor option is provided. Also serves as the data input 1 for the UART (RXD1). RXD1 input is hysteresis input. 61 P44/SCL1 E General-purpose I/O port A pull-up resistor option is provided. Also serves as the clock I/O 1 for the UART (SCL1). SCL1 input is hysteresis input. 62 P45/TXD2 D General-purpose I/O port A pull-up resistor option is provided. Also serves as the data output 2 for the UART (TXD2). 63 P46/RXD2 E General-purpose I/O port A pull-up resistor option is provided. Also serves as the data input 2 for the UART (RXD2). RXD2 input is hysteresis input. 64 P47/SCL2 E General-purpose I/O port A pull-up resistor option is provided. Also serves as the clock I/O 2 for the UART (SCL2). SCL2 input is hysteresis input. 51 to 55 P50 to P54 G N-channel open-drain I/O ports A pull-up resistor option is provided only for the MB89816A. 9 to 11 P60/INT0 to P62/INT2 H General-purpose I/O ports A pull-up resistor option is provided. Also serve as an external interrupt input (INT0 to INT2). These ports are a hysteresis input type. 13 to 17 P63/INT3 to P67/INT7 H General-purpose I/O ports A pull-up resistor option is provided. Also serve as an external interrupt input (INT3 to INT7). These ports are a hysteresis input type. 12, 57 VCC – Power supply pin 25, 50 VSS – Power supply (GND) pin 7 MB89810A Series ■ I/O CIRCUIT TYPE Type A Circuit Remarks • Main clock • At an oscillation feedback resistor of approximately 1 MΩ (1 to 5 MHz) • CR oscillator circuit selectability X1 X0 Standby control signal B C R P-ch • At an output pull-up resistor (P-ch) of approximately 50 kΩ/5.0 V • Hysteresis input N-ch D • CMOS output • CMOS input R P-ch P-ch N-ch • Pull-up resistor optional E • CMOS output • CMOS input • Hysteresis input (resource input) R P-ch P-ch N-ch • Pull-up resistor optional (Continued) 8 MB89810A Series (Continued) Type Circuit Remarks F • CMOS output P-ch N-ch G • N-ch open-drain output • CMOS input R P-ch N-ch • Pull-up resistor optional (only for the MB89816A) H • Hysteresis input • Pull-up resistor optional I X1A • Subclock (30 to 40 kHz) • At an oscillation feedback resistor of approximately 10 MΩ X0A 9 MB89810A Series ■ HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. 3. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 4. Precautions when Using an External Clock Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode. 10 MB89810A Series ■ PROGRAMMING TO THE EPROM ON THE MB89P817A In EPROM mode, the MB89P817A functions equivalent to the MBM27C256A. This allows the OTPROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. • Writing Procedure (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0007H to 7FFFH (note that addresses 8007H to FFFFH while operating as operating mode assign to 0007H to 7FFFH in EPROM mode). Load option data into addresses 0000H to 0006H of the EPROM programmer. (For information about each corresponding option, see “• OTPROM Option Bit Map.”) (3) Program with the EPROM programmer. • Memory Space Memory space is diagrammed below. Normal operating mode 0000H EPROM mode (Corresponding address on the EPROM programmer) I/O 0080H 0100H 0200H Register RAM 0880H External area 8000H 0000H Option area 8007H Option area 0007H Program area ROM FFFFH (PROM) 7FFFH 11 MB89810A Series • Recommended Screening Conditions High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM (one-time PROM) microcomputer program. Program, verify Aging +150 °C, 48 h Data verification Assembly • Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. • EPROM Programmer Socket Adapter Package FPT-64P-M06 Compatible socket adapter ROM-64QF-28DP-8L Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760 Note: Connect the jumper pin to VSS when using. Depending on the EPROM programmer, inserting a capacitor of approx. 0.1 µF between VPP and VSS or VCC and VSS can stabilize programming operations. 12 MB89810A Series • OTPROM Option Bit Map Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Vacancy Vacancy Vacancy 000 Readable 0H and writable Readable and writable Readable and writable P07 000 Pull-up 1H 1: No 0: Yes P06 Pull-up 1: No 0: Yes P17 000 Pull-up 2H 1: No 0: Yes Single-clock setting 1: Dualclock 0: Singleclock Reset pin output 1: Enabled 0: Disabled Power-on Oscillation stabilization time reset 4 14 1: Enabled 00 217/FCH 01 218/FCH 0: Disabled 10 2 /FCH 11 2 /FCH P05 Pull-up 1: No 0: Yes P04 Pull-up 1: No 0: Yes P03 Pull-up 1: No 0: Yes P02 Pull-up 1: No 0: Yes P01 Pull-up 1: No 0: Yes P00 Pull-up 1: No 0: Yes P16 Pull-up 1: No 0: Yes P15 Pull-up 1: No 0: Yes P14 Pull-up 1: No 0: Yes P13 Pull-up 1: No 0: Yes P12 Pull-up 1: No 0: Yes P11 Pull-up 1: No 0: Yes P10 Pull-up 1: No 0: Yes P37 000 Pull-up 3H 1: No 0: Yes P36 Pull-up 1: No 0: Yes P35 Pull-up 1: No 0: Yes P34 Pull-up 1: No 0: Yes P33 Pull-up 1: No 0: Yes P32 Pull-up 1: No 0: Yes P31 Pull-up 1: No 0: Yes P30 Pull-up 1: No 0: Yes P47 000 Pull-up 4H 1: No 0: Yes P46 Pull-up 1: No 0: Yes P45 Pull-up 1: No 0: Yes P44 Pull-up 1: No 0: Yes P43 Pull-up 1: No 0: Yes P42 Pull-up 1: No 0: Yes P41 Pull-up 1: No 0: Yes P40 Pull-up 1: No 0: Yes Vacancy Vacancy Readable and writable Readable and writable P64 Pull-up 1: No 0: Yes P63 Pull-up 1: No 0: Yes P62 Pull-up 1: No 0: Yes P61 Pull-up 1: No 0: Yes P60 Pull-up 1: No 0: Yes Vacancy Vacancy Vacancy Oscillator type Readable and writable Readable and writable Readable and writable P67 Pull-up 1: No 0: Yes P66 Pull-up 1: No 0: Yes P65 Pull-up 1: No 0: Yes Vacancy 000 Readable 5H and writable Vacancy 000 Readable 6H and writable 1: Crystal 0: CR Bit 2 Bit 1 Bit 0 Note: • Each bit is set to ’1‘ as the initialized value. • Do not write ’0‘ to the vacant bit. 13 MB89810A Series ■ BLOCK DIAGRAM Time-base timer Main clock oscillator Clock controlletr X0A X1A 8-bit PWM timer 1 P36/PTO1 Port 0 and port 1 CMOS I/O port 8 P1 0 t o P17 8 Port 2 CMOS output port 8-bit serial I/O 1 P31/SCK P33/SI P32/SO Pulse width detection P 3 0 / P WE P 3 5 / P WI P 3 4 / P WO CMOS I/O port UART RAM (2048 × 8 bits) F2MC-8L CPU ROM (24 K × 8 bits) Other pins 16-bit timer/counter P41/EC CMOS I/O port P40 Port 5 N-ch open-drain I/O port External interrupt VCC × 2, VSS × 2 MOD0, MOD1 Input port 14 P44/SCL1 P47/SCL2 P43/RXD1 P46/RXD2 P42/TXD1 P45/TXD2 Port 4 8 P0 0 t o P07 Internal bus Reset circuit (WDT) RST P2 0 t o P27 P37/PTO2 Port 3 Subclock oscillator 8-bit PWM timer 2 5 P50 to P54 8 8 Port 6 X0 X1 P60/INT0 to P67/INT7 MB89810A Series ■ CPU CORE 1. Memory Space The microcontrollers of the MB89810A series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89810A series is structured as illustrated below. Memory Space MB89816A 0000H MB89P817A 0000H I/O I/O 0080H 0080H 0100H 0100H Register 0200H Register 0200H RAM 2 KB RAM 2 KB 0880H 0880H Not available Not available 8000H Optional PROM 8007H A000H PROM 32 KB ROM 24 KB FFFFH FFFFH 15 MB89810A Series 2. Registers The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided: Program counter (PC): A 16-bit register for indicating instruction storage positions Accumulator (A): A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX): A 16-bit register for index modification Extra pointer (EP): A 16-bit pointer for indicating a memory address Stack pointer (SP): A 16-bit register for indicating a stack area Program status (PS): A 16-bit register for storing a register pointer, a condition code 16 bits Initial value FFFDH : Program counter PC A : Accumulator Undefined T : Temporary accumulator Undefined IX : Index register Undefined EP : Extra pointer Undefined SP : Stack pointer Undefined PS : Program status I-flag = 0, IL1, 0 = 11 Other bits are undefined. The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) Structure of the Program Status Register 15 PS 14 13 12 RP 10 9 8 Vacancy Vacancy Vacancy RP 16 11 7 6 H I 5 4 IL1, 0 3 2 1 0 N Z V C CCR MB89810A Series The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. Rule for Conversion of Actual Addresses of the General-purpose Register Area Lower OP codes RP “0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ b1 b0 ↓ ↓ Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag:Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared otherwise. This flag is for decimal adjustment instructions. I-flag:Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0 when reset. IL1, 0:Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 IL0 Interrupt level 0 0 0 1 1 0 2 1 1 3 1 High-low High Low = no interrupt N-flag:Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0. Z-flag:Set when an arithmetic operation results in 0. Cleared otherwise. V-flag:Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does not occur. C-flag:Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise. Set to the shift-out value in the case of a shift instruction. 17 MB89810A Series The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 32 banks can be used on the MB89816A. The bank currently in use is indicated by the register bank pointer (RP). Register Bank Configuration This address = 0100H + 8 × (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area 18 MB89810A Series ■ I/O MAP Address Read/write Register name Register description 00H (R/W) PDR0 Port 0 data register 01H (W) DDR0 Port 0 data direction register 02H (R/W) PDR1 Port 1 data register 03H (W) DDR1 Port 1 data direction register 04H (R/W) PDR2 Port 2 data register 05H Vacancy 06H Vacancy 07H (R/W) SYCC System clock control register 08H (R/W) STBC Standby control register 09H (R/W) WDTC Watchdog timer control register 0AH (R/W) TBCR Time-base timer control register 0BH (R/W) WPCR Watch prescaler control register 0CH (R/W) PDR3 Port 3 data register 0DH (W) DDR3 Port 3 data direction register 0EH (R/W) PDR4 Port 4 data register 0FH (W) DDR4 Port 4 data direction register 10H (R/W) PDR5 Port 5 data register 11H (R) PDR6 Port 6 data register 12H Vacancy 13H Vacancy 14H Vacancy 15H Vacancy 16H Vacancy 17H (R/W) PIVE 18H (R/W) TMCR 16-bit timer count register 19H (R/W) TCHR 16-bit timer count register (H) 1AH (R/W) TCLR 16-bit timer count register (L) 1BH Port inverting operation enable register Vacancy 1CH (R/W) SMR Serial I/O mode register 1DH (R/W) SDR Serial I/O data register 1EH Vacancy 1FH Vacancy (Continued) 19 MB89810A Series (Continued) Address Read/write Register name 20H (R/W) SMC1 21H (R/W) SRC UART serial I/O rate control register 22H (R/W) SSD UART serial I/O status/data control register 23H (R/W) SIDR/SODR 24H (R/W) SMC2 UART serial I/O mode control register 1 UART serial I/O data control register UART serial I/O mode control register 2 25H Vacancy 26H Vacancy 27H Vacancy 28H (R/W) CNTR1 PWM timer control register 1 29H (R/W) CNTR2 PWM timer control register 2 2AH (R/W) CNTR3 PWM timer control register 3 2BH (W) COMR2 PWM timer compare register 2 2CH (W) COMR1 PWM timer compare register 1 2DH Vacancy 2EH Vacancy 2FH (R/W) PWCR Pulse width detection control register 30H (R/W) EIC1 External interrupt 1 control register 1 31H (R/W) EIC2 External interrupt 1 control register 2 32H (R/W) EI2E External interrupt 2 enable register 33H (R/W) EI2F External interrupt 2 flag register 34H Vacancy 35H to 7AH Vacancy 7BH Vacancy 7CH (W) ILR1 Interrupt level register 1 7DH (W) ILR2 Interrupt level register 2 7EH (W) ILR3 Interrupt level register 3 7FH Not available ITR Interrupt test register Note: Do not use vacancies. 20 Register description MB89810A Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (VSS = 0.0 V) Parameter Symbol Value Unit Remarks Min. Max. VCC VSS – 0.3 VSS + 7.0 V VI1 VSS – 0.3 VCC + 0.3 V Except P50 to P54 VI2 VSS – 0.3 VSS + 7.0 V P50 to P54 VO1 VSS – 0.3 VCC + 0.3 V Except P50 to P54 VO2 VSS – 0.3 VSS + 7.0 V P50 to P54 IOL — 20 mA Peak value IOLAV1 — 4 mA Average value except pins other than P50 to P54 IOLAV2 — 10 mA Average value for P50 to P54 “L” level total maximum output current ∑IOL — 100 mA Peak value “L” level total average output current ∑IOLAV — 40 mA Average value “H” level maximum output current IOH — –20 mA Peak value “H” level average output current IOHAV — –4 mA Average value “H” level total maximum output current ∑IOH — –50 mA Peak value “H” level total average output current ∑IOHAV — –20 mA Average value Power consumption PD — 300 mW Operating temperature TA –40 +85 °C Storage temperature Tstg –55 +150 °C Power supply voltage Input voltage Output voltage “L” level maximum output current “L” level average output current WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 21 MB89810A Series 2. Recommended Operating Conditions (VSS = 0.0 V) Symbol Parameter Power supply voltage VCC Value Unit Remarks Min. Max. 2.2* 6.0 V Normal operation assurance range MB89816A 2.7* 6.0 V Normal operation assurance range MB89P817A 1.5 6.0 V Retains the RAM state in stop mode P50 to P54 (without pull-up resistor) Open-drain output pin application voltage VD VSS – 0.3 VSS + 6.0 V Operating temperature TA –40 +85 °C *: These values vary with the operating frequency. See Figure 1. Operating voltage (V) 6 5 Operating assurance range 4 3 2 1 2.0 5.0 1.0 3.0 4.0 Main clock operating frequency (MHz) (at an instruction cycle of 4/FCH) Note: The shaded area is assured only for the MB89816A Figure 1 Operating Voltage vs. Main Clock Operating Frequency (for MB89816A) WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 22 MB89810A Series 3. DC Characteristics (VCC = +5.0 V, VSS = 0.0 V, TA = –40 °C to +85 °C) Parameter Pull-up resistance Unit Min. Typ. Max. Remarks 0.7 VCC — VCC + 0.3 V RST, MOD0, MOD1, P60 to P67, Peripheral input for port 3 and port 4 — 0.8 VCC — VCC + 0.3 V VIHS2 P50 to P54 (without pull-up resistor) — 0.8 VCC — VSS + 6.0 V VIL P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P54 — VSS – 0.3 — 0.3 VCC V VILS RST, MOD0, MOD1, P60 to P67, Peripheral input for port 3 and port4 — VSS – 0.3 — 0.2 VCC V VOH P00 to P07, P10 to P17, P20 to P27, P30 to P37, IOH = –2.0 mA P40 to P47 2.4 — — V VOL1 P00 to P07, P10 to P17, P20 to P27, P30 to P37, IOL = 1.8 mA P40 to P47, P50 to P54 P60 to P67 — — 0.4 V VOL2 P50 to P54 IOL = 6 mA VCC = 3 V — — 0.5 V VOL3 RST IOL = 4.0 mA — — 0.4 V ILI1 P00 to P07, P10 to P17, P20 to P27, P30 to P37, 0.45 V < VI < P40 to P47, P50 to P54, VCC P60 to P67, MOD0, MOD1 — — ±5 µA Without pullup resistor RPULL P00 to P07, P10 to P17, P30 to P37, P40 to P47, VI = 0.0 V P50 to P54, P60 to P67, RST 25 50 100 kΩ With pull-up resistor “L” level input voltage Input leakage current (Hi-z output leakage current) Condition — “H” level input voltage VIHS “L” level output voltage Pin P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P54 (with pull-up resistor) VIH “H” level output voltage Value Symbol (Continued) 23 MB89810A Series (Continued) (VCC = +5.0 V, VSS = 0.0 V, TA = –40 °C to +85 °C) Value Parameter Symbol Pin Unit Remarks Min. Typ. Max. FCH = 5 MHz VCC = 5.0 V tinst = 0.8 µs — 4 6 mA MB89816A — 4.8 7.5 mA MB89P817A FCH = 5 MHz VCC = 3.0 V tinst = 6.4 µs — 0.4 0.6 mA MB89816A — 1.0 1.5 mA MB89P817A FCH = 5 MHz VCC = 5.0 V tinst = 0.8 µs — 1.2 1.8 mA Sleep mode ICCS2 FCH = 5 MHz VCC = 3.0 V tinst = 12.8 µs — 0.3 0.5 mA — 50 100 µA ICCL FCL = 32.768 kHz VCC = 3.0 V Subclock mode — 500 700 µA MB89P817A — 15 50 µA Subclock sleep mode µA Watch mode Main clock stop mode at dual-clock system Subclock stop mode Main clock stop mode at single-clock system ICC1 ICC2 ICCS1 Power supply current* Condition VCC FCL = 32.768 kHz VCC = 3.0 V ICCLS FCL = 32.768 kHz VCC = 3.0 V ICCT — — 15 VCC ICCH Input capacitance CIN Other than VCC and VSS FCL = 32.768 kHz VCC = 3.0 V — — 10 µA f = 1 MHz — 10 — pF *: The measurement conditions of power supply current are as follows: the external clock and TA = +25 °C. 24 MB89810A Series 4. AC Characteristics (1) Reset Timing (VCC = +5.0 V±10 %, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C) Symbol Parameter RST “L” pulse width Value Condition tZLZH — Min. Max. 48 tCH — Unit Remarks ns Note: tCH is the cycle time of the main clock. tZLZH RST 0.2 VCC 0.2 VCC (2) Power-on Reset (AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C) Parameter Symbol Power supply rising time tR Power supply cut-off time tOFF Condition — Value Unit Remarks Min. Max. — 50 ms Power-on reset function only 1 — ms Due to repeated operations Note: Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. tR tOFF 2.0 V VCC 0.2 V 0.2 V 0.2 V Note that a sudden increase in supply voltage may result in a power-on reset. When increasing the supply voltage during operation, voltage variation should be within twice the intended increment so that the voltage rises as smoothly as possible. 25 MB89810A Series (3) Clock Timing (AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C) Symbol Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rising/ falling time Pin Condition Value Min. Typ. Max. FCH X0, X1 1 — 5 MHz FCL X0A, X1A — 32.768 — kHz tCH X0, X1 200 — 1000 ns tCL X0A, X1A — 30.5 — µs PWH PWL X0 20 — — ns PWHL PWLL X0A — 15.2 — µs tCR tCF X0 — — 10 ns — X0 and X1 Timing and Conditions tCH PWH PWL tCR 0.8 VCC tCF 0.8 VCC X0 0.2 VCC 0.2 VCC 0.2 VCC Main Clock Conditions When a crystal or ceramic resonator is used X0 X1 when an external clock is used X0 X1 Open When a CR oscillator is used X0 26 Unit X1 Remarks External clock External clock MB89810A Series X0A and X1A Timings and Conditions tCL PWHL PWLL tCF tCR 0.8 VCC 0.8 VCC X0A 0.2 VCC 0.2 VCC Subclock Conditions 0.2 VCC When a crystal or ceramic resonator is used X0A when an external clock is used X1A X0A X1A Open (4) Instruction Cycle Parameter Instruction cycle (Minimum execution time) Symbol Value (typ) Unit Remarks 4/FC, 8/FC, 16/FC, 64/FC µs tinst = 0.8 µs when operating at FC = 5 MHz (4/FC) 2/FCL µs tinst = 61.036 µs when operating at FCL = 32.768 kHz tinst Note: When operating at 5 MHz, the cycle varies with the set execution time. (5) Serial I/O Timings (VCC = +5.0 V±10 %, AVSS = VSS= 0.0 V, TA = –40 °C to +85 °C) Parameter Symbol Pin Serial clock cycle time tSCYC1 SCK SCK ↓ → SO time tSLOV1 SCK, SO Valid SI → SCK ↑ tIVSH1 SI, SCK SCK ↑ → valid SI hold time tSHIX1 SCK, SI Serial clock “H” pulse width tSHSL Serial clock “L” pulse width tSLSH Condition Internal shift clock mode SCK External shift clock mode Value Unit Remarks Min. Max. 2 tinst — ns –200 200 ns 1/2 tinst — ns 1/2 tinst — ns 1 tinst — ns 1 tinst — ns 0 200 ns SCK ↓ → SO time tSLOV2 SCK, SO Valid SI → SCK ↑ tIVSH2 SI, SCK 1/2 tinst — ns SCK ↑ → valid SI hold time tSHIX2 SCK, SI 1/2 tinst — ns Note: For information on tinst, see “ (4) Instruction Cycle”. 27 MB89810A Series (6) UART Timings (VCC = +5.0 V±10 %, AVSS = VSS= 0.0 V, TA = –40 °C to +85 °C) Parameter Symbol Pin Serial clock cycle time tSCYC SCL1, SCL2 SCL ↓ → TXDx time tSLOV1 SCLx, TXDx Valid RXDx → SCLx ↑ tIVSH1 RXDx, SCLx SCLx ↑ → valid RXDx hold time tSHIX1 SCL1, RXD2 Serial clock “H” pulse width tSHSL Serial clock “L” pulse width tSLSH SCLx ↓ → TXDx time tSLOV2 SCLx, TXDx Valid RXDx → SCLx ↑ tIVSH2 RXDx, SCLx SCLx ↑ → valid RXDx hold time tSHIX2 SCL1, RXD2 Notes: • • Condition Value Max. 2 tinst — ns –200 200 ns 1/2 tinst — ns 1/2 tinst — ns 1 tinst — ns 1 tinst — ns 0 200 ns 1/2 tinst — ns 1/2 tinst — ns Remarks Internal shift clock mode SCL1, SCL2 External shift clock mode For information on tinst, see “ (4) Instruction Cycle”. The edge polarity for the SLCx input is assumed when LSEL bit = 0 for SMC2. The polarity is inverted when LSEL = 1. Internal Shift Clock Mode tSCYC SCK/SCLx 2.4 V 0.8 V 0.8 V t SLOV1 2.4 V SO/TXDx 0.8 V tIVSH1 SI/RXDx tSHIX1 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC External Shift Clock Mode tSLSH SCK/SCLx tSHSL 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tSLOV2 SO/TXDx 2.4 V 0.8 V tIVSH2 SI/RXDx 28 Unit Min. tSHIX2 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC MB89810A Series (7) Peripheral Input Timings (VCC = +5.0 V±10 %, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C) Pin Condition Peripheral input “H” pulse tILIH width EC, INT0 to INT7 Peripheral input “L” pulse width EC, INT0 to INT7 Parameter “H” input pulse width of pulse width detection enable signal Symbol tIHIL tPWEH Notes: • • • tPWEL Unit Remarks Min. Max. — 2 tinst — ns — 2 tinst — ns — 512 tCL + 200 or 480 tCL + 200 — ns — 512 tCL + 200 or 480 tCL + 200 — ns PWE “L” input pulse width of pulse width detection enable signal Value For information on tinst, see “ (4) Instruction Cycle”. tCL represents the subclock cycle time. The PWE pulse width value varies with the first divider selection bit of the watch prescaler. The pulse width is “512 tCL + 200” when divide by 16 is selected; or “480 tCL + 200” when divide by 15 is selected. tIHIL EC, INT0 to INT7 tILIH 0.8 VCC 0.2 VCC 0.2 VCC tPWEH tPWEL 0.8 VCC PWE 0.2 VCC 0.8 VCC 0.8 VCC 0.2 VCC 29 MB89810A Series ■ MASK OPTIONS No. Part number MB89816A MB89P817A Specifying procedure Specify when ordering masking Set with EPROM programmer 1 Pull-up resistors •P00 to P07, P10 to P17, •P30 to P37, P40 to P47, •P50 to P54, P60 to P67 Specify by pin 2 Power-on reset selection •With power-on reset •Without power-on reset Selectable Setting possible 3 Main clock oscillation (5 MHz) stabilization time selection* •approx. 218/FCH (approx. 52.4 ms) •approx. 217/FCH (approx. 26.2 ms) •approx. 214/FCH (approx. 3.2 ms) •approx. 24/FCH (approx. 0 ms) Selectable Setting possible 4 Reset pin output selection •With reset output •Without reset output Selectable Setting possible 5 Selection either single- or dual-clock system •Single clock •Dual clock Selectable Setting possible 6 Main clock oscillator type selection •Crystal or ceramic oscillator •CR Selectable Setting possible Can be set per pin. (P50 to P54 are available only for without a pull-up resistor.) FCH: Main clock frequency *: The main clock oscillation setting time is generated by dividing the main clock frequency. Note that the oscillation cycle is not stable immediately after oscillation is started. The settling time value in this data sheet should be used as a reference. ■ ORDERING INFORMATION Part number MB89816APF MB89P817APF 30 Package 64-pin Plastic QFP (FPT-64P-M06) Remarks MB89810A Series ■ PACKAGE DIMENSION 64-pin Plastic QFP (FPT-64P-M06) 24.70±0.40(.972±.016) 20.00±0.20(.787±.008) 51 0.17±0.06 (.007±.002) 33 52 32 18.70±0.40 (.736±.016) 14.00±0.20 (.551±.008) INDEX Details of "A" part +0.35 3.00 –0.20 +.014 .118 –.008 64 (Mounting height) 20 0~8° 1 19 1.00(.039) 0.42±0.08 (.017±.003) 0.20(.008) +0.15 M 0.25 –0.20 1.20±0.20 (.047±.008) +.006 .010 –.008 (Stand off) "A" 0.10(.004) C 2001 FUJITSU LIMITED F64013S-c-4-4 Dimensions in mm (inches) 31 MB89810A Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0105 FUJITSU LIMITED Printed in Japan