ESDA14V2-4BF2 Quad bidirectional Transil™ array for ESD protection Features ■ 4 Bidirectional Transil functions ■ ESD Protection: IEC 61000-4-2 level 4 ■ Stand off voltage: 12 V Min. ■ Low leakage current < 1 µA ■ 50 W Peak pulse power (8/20 µs) Flip Chip (5 bumps) Benefits ■ High ESD protection level ■ High integration ■ Suitable for high density boards Figure 1. Device configuration A3 A1 C1 C3 Complies with the following standards ■ ■ IEC 61000-4-2 – 15 kV (air discharge) – 8 kV (contact discharge) MIL STD 883F- Method 3015-7: class3 – 25 kV (human body model) GND Figure 2. Pin configuration (bump side) 3 Applications 2 1 A Where transient overvoltage protection in ESD sensitive equipment is required, such as : B ■ Computers C ■ Printers ■ Communication systems and cellular phones ■ Video equipment Description The ESDA14V2-4BF2 is a monolithic array designed to protect up to 4 lines (bidirectional) against ESD transients. This device is particularly adapted to the protection of symmetrical signals. The device is ideal for situations where board space saving is requested. April 2008 TM: Transil is a trademark of STMicroelectronics. Rev 4 1/8 www.st.com 8 Characteristics 1 ESDA14V2-4BF2 Characteristics Table 1. Absolute ratings (limiting values) Symbol Parameter MIL STD 883E - Method 3015-7 IEC61000-4-2 air discharge IEC61000-4-2 contact discharge Unit ± 25 ± 15 ±8 kV VPP ESD discharge PPP Peak pulse power (8/20 µs) 50 W Junction temperature 125 °C -55 to +150 °C 260 °C -40 to +125 °C Tj Tstg Storage temperature range TL Lead solder temperature (10 seconds duration) Top Operating temperature range Table 2. Electrical characteristics (Tamb = 25 °C) Symbol Parameter VRM Stand-off voltage VBR Breakdown voltage VCL Clamping voltage IRM Leakage current @ VRM IPP Peak pulse current C Capacitance Rd Dynamic resistance I VCL VBR VRM Types ESDA6V1SC5 V Slope: 1 / Rd VBR @ IR IPP IRM @ VRM αT C typ.(1) max.(2) typ. 0 V bias max. V V mA µA V Ω 10-4/C pF 14.2 18 1 1 0.1 12 3 3.2 10 15 2. Δ VBR = αT* (Tamb -25 °C) * VBR (25 °C) max. Rd min. 1. Square pulse, Ipp = 3 A, tp = 2.5 µs. 2/8 Value ESDA14V2-4BF2 Figure 3. Characteristics Clamping voltage versus peak Figure 4. pulse current (Tj initial = 25 °C) (Rectangular waveform, tp = 2.5 µs) Capacitance versus reverse applied voltage (typical values) C(pF) IPP(A) 10.0 14 tp = 2.5µs F=1MHz VOSC=30mVRMS Tj=25°C 12 10 8 1.0 6 4 2 VCL(V) VR(V) 0.1 0 0 Figure 5. 10 20 30 40 50 60 Relative variation of leakage current versus junction temperature (typical values) 0 2 Figure 6. 4 6 8 10 12 14 ESD response to IEC 61000-4-2 (+15 kV air discharge) IR[Tj] / IR[Tj=25°C] 1000 100 V(i/o) 10 Tj(°C) 1 25 Figure 7. 50 75 100 ESD response to IEC 61000-4-2 (-15 kV air discharge) 125 Figure 8. Analog crosstalk Typical crosstalk response of ESDA14V2-4BF1 (A1/A3 line) 0.00 -10.00 -20.00 -30.00 V(i/o) -40.00 -50.00 -60.00 -70.00 -80.00 -90.00 -100.0 100.0k 1.0M 10.0M f/Hz 100.0M 1.0G 3/8 Application information Figure 9. ESDA14V2-4BF2 Digital crosstalk rise time: t10-90% = 3ns VG1 VIN = A1 V = 0-3V F = 5MHz β21VG1 VOUT = C3 2 Application information Figure 10. Application example A1 Connector A3 IC to be protected C1 C3 B2 Figure 11. Aplac model 1.2pF 1.2pF 100m 100m D02_r BV = 16 IBV = 1m CJO = 200p M = 0.3333 RS = 1 VJ = 0.6 TT = 100n 4/8 1.2pF 100m D02_r D02_f BV = 16 IBV = 1m CJO = 10.4p M = 0.3333 RS = 2 VJ = 0.6 TT = 100n B2 B2 50pH 50m C3 C1 A3 A1 160pH 1.8 1.2pF 100m ESDA14V2-4BF2 3 Ordering information scheme Ordering information scheme Figure 12. Ordering information scheme ESDA 14V2 - 4 B Fx ESD Array Breakdown Voltage 14V2 = 14.2 Volts min. Number of line 4 = 4 lines Type B = Bidirectional Package F = Flip Chip x = 2: Lead-free, pitch = 500 µm, bump = 315 µm Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Figure 13. Flip Chip package mechanical data 700µm ± 50 650µm ± 65 µm ± 40 1.12 mm ± 50µm 315µm ± 50 210 µm 1.12 mm ± 50µm 210 µm 49 5 4 5/8 Package information ESDA14V2-4BF2 Figure 14. Foot print recommendations Figure 15. Marking Dot, ST logo xx = marking z = manufacturing location yww = datecode (y = year ww = week) Copper pad Diameter: 250 µm recommended, 300 µm max E Solder stencil opening: 330 µm x x z y ww Solder mask opening recommendation: 340 µm min for 315 µm copper pad diameter Figure 16. Flip Chip tape and reel specification Dot identifying Pin A1 location 3.5 ± 0.1 1.22 ST E xxz yww 1.22 ST E xxz yww 6/8 ST E All dimensions in mm xxz yww 8 ± 0.3 0.73 ± 0.05 1.75 ± 0.1 Ø 1.5 ± 0.1 4 ± 0.1 4 ± 0.1 User direction of unreeling ESDA14V2-4BF2 5 Ordering information Ordering information Table 3. Ordering information Order code Marking Package Weight Base qty Delivery mode ESDA14V2-4BF2 EA Flip Chip 2.1 mg 5000 Tape and reel 7” Note: More information is available in the application notes: AN1235:"Flip Chip: Package description and recommendations for use" AN1751: “EMI filters: Recommendations and measurements” 6 Revision history Table 4. Document revision history Date Revision Description of changes 14-Mar-2005 1 First issue. 18-Oct-2005 2 Dimension from center bump to corner bump changed in Figure 16. to indicate diagonal instead of perpendicular measurement. No values changed. ECOPACK statement added. 04-Jun-2007 3 Reformatted to current standard. 16-Apr-2008 4 Updated ECOPACK statement. Updated Figure 12, Figure 13 and Figure 16. Reformatted to current standards. 7/8 ESDA14V2-4BF2 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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