EMIF10-COM01F2 10-line IPAD™, EMI filter including ESD protection Features ■ EMI symmetrical (I/O) low-pass filter ■ Lead free package ■ Very low PCB space consuming: < 6 mm2 ■ Very thin package: 0.65 mm ■ High efficiency in ESD suppression on both input & output pins ■ High reliability offered by monolithic integration Complies with the following standard: ■ Flip Chip (25 bumps) Figure 1. IEC 61000-4-2 level 4 – 15 kV (air discharge) – 8 kV (contact discharge) Applications EMI filtering and ESD protection for: ■ Computers and printers ■ Communication systems ■ Mobile phones Description Figure 2. The EMIF10-COM01F2 is a highly integrated device designed to suppress EMI / RFI noise in all systems subjected to electromagnetic interferences. The EMIF10 Flip-Chip packaging means the package size is equal to the die size. Pin configuration (bump side) 5 4 3 2 1 I5 I4 I3 I2 I1 A I10 I9 I8 I7 I6 B GND GND GND GND GND C 010 09 08 07 06 D 05 04 03 02 01 E Basic cell configuration Low-pass Filter Input Additionally, this filter includes an ESD protection circuitry which prevents damage to the application when subjected to ESD surges up to 15 kV. Output RI/O = 200Ω Cline = 45 pF TM: IPAD is a trademark of STMicroelectronics. April 2008 Rev 5 1/7 www.st.com 7 Characteristics 1 EMIF10-COM01F2 Characteristics Table 1. Absolute ratings (Tamb = 25 °C) Symbol VPP Tj Parameter and test conditions Value Unit ESD discharge IEC61000-4-2, air discharge ESD discharge IEC61000-4-2, contact discharge 15 8 kV Junction temperature 125 °C Top Operating temperature range - 40 to + 85 °C Tstg Storage temperature range - 55 to + 150 °C Table 2. Electrical characteristics (Tamb = 25 °C) Symbol Parameter I VBR Breakdown voltage IRM Leakage current @ VRM VRM Stand-off voltage VCL Clamping voltage Rd Dynamic impedance IPP Peak pulse current RI/O Resistance between Input and Output Cline Input capacitance per line Symbol VCL VBR VRM slope : 1 / R d Test conditions VBR IR = 1 mA IRM VRM = 3 V per line Rd IPP = 10 A, tp = 2.5 µs tLH Figure 3. Min. Typ. Max. Unit 6 8 10 V 500 nA 180 At 0 V bias Vinput = 2.8 V IPP Ω 1 RI/O Cline 200 220 Ω 45 50 pF 25 ns Rload = 100 kΩ S21(db) attenuation measurement(1) V IRM IR Figure 4. Analog crosstalk 0.00 0.00 dB dB -10.00 -10.00 -20.00 -30.00 -20.00 -40.00 -50.00 -30.00 -60.00 -70.00 -40.00 -80.00 -90.00 -50.00 100.0k 1.0M 10.0M 100.0M f/Hz 1.0G 1. Spikes at high frequencies are induced by the PCB layout 2/7 -100.00 100.0k 1.0M Xtalk 1/2 10.0M f/Hz 100.0M 1.0G EMIF10-COM01F2 Figure 5. Characteristics Figure 6. ESD response to IEC 61000-4-2 (+15 kV air discharge) on one input (Vin) and on one output (Vout) ESD response to IEC 61000-4-2 (-15 kV air discharge) on one input (Vin) and on one output (Vout) V(in1) V(in1) V(out1) V(out1) Figure 7. Rise time measurement EMIF10-COM01F2 In Square signal Generator Vc = 2.8V Figure 8. Vin Out 100k Vout Capacitance versus reverse applied voltage C(pF) 50 F=1MHz Vosc=30mV 40 30 20 10 0 1 2 3 4 5 VR(V) 3/7 Application information 2 EMIF10-COM01F2 Application information Figure 9. Aplac model 200R out in MODEL = demif10 MODEL = demif10 Demif10 model BV = 7 IBV = 1m CJO = 25p M = 0.3333 RS = 1 VJ = 0.6 TT = 100n sub 2.1 PCB grounding recommendations In order to ensure a good efficiency in terms of ESD protection and filtering behavior, we recommend to implement microvias (100 µm dia.) between the GND bumps and the GND layer. GND bumps can be connected together in PCB layer 1, and in addition, if possible, use through hole vias (200 µm dia.) in both sides of filter to improve contact to GND (layer). This layout will minimize the distance to the ground and thus parasitic inductances. In addition, we recommend to have GND plane wherever possible. 3 Ordering information scheme Figure 10. Ordering information scheme EMIF EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10(pF) or 3 letters = application 2 digits = version Package F = Flip Chip x = 2: Lead-free, pitch = 500 µm, bump = 315 µm 4/7 yy - xxx zz Fx EMIF10-COM01F2 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Figure 11. Flip Chip package dimensions 500 µm ± 50 650 µm ± 65 315 µm ± 50 2.39 mm ± 30 µm 500 µm ± 50 4 Package information 2.39 mm ± 30 µm Figure 12. Footprint recommendations Copper pad Diameter: 250 µm recommended, 300 µm max Figure 13. Marking Dot, ST logo xx = marking z = manufacturing location yww = datecode (y = year ww = week) E Solder stencil opening: 330 µm Solder mask opening recommendation: 340 µm min for 300 µm copper pad diameter x x z y ww 5/7 Ordering information EMIF10-COM01F2 Figure 14. Flip Chip tape and reel specification Dot identifying Pin A1 location 3.5 ± 0.1 2.6 ST E User direction of unreeling Ordering information Table 3. Note: 2.6 4 ± 0.1 All dimensions in mm 5 xxz yww xxz yww ST E xxz yww ST E 8 ± 0.3 0.73 ± 0.05 1.75 ± 0.1 Ø 1.5 ± 0.1 4 ± 0.1 Ordering information Order code Marking Package Weight Base qty Delivery mode EMIF10-COM01F2 FE Flip Chip 8.3 mg 5000 Tape and reel More information is available in the application notes: AN1235: “Flip Chip: Package description and recommendations for use” AN1751: "EMI Filters: Recommendations and measurements" 6 Revision history Table 4. 6/7 Document revision history Date Revision Description of changes 14-Dec-2004 1 First issue. 08-Apr-2005 2 Die shrink. 19-Oct-2005 3 Replaced Figures 3 and 13. Added ECOPACK statement. 03-Apr-2006 4 Reformatted to current standard. Pin identification in Figure 1 updated. 17-Apr-2008 5 Updated ECOPACK statement. Updated Figure 10, Figure 11 and Figure 14. Reformatted to current standards. EMIF10-COM01F2 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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