STMICROELECTRONICS VND5012AKTR-E

VND5012AK-E
DOUBLE CHANNEL HIGH SIDE DRIVER WITH ANALOG
CURRENT SENSE FOR AUTOMOTIVE APPLICATIONS
ADVANCE DATA
Table 1. General Features
Figure 1. Package
TYPE
VCC
RDS(on)
ID
VND5012AK-E
41V
12mΩ (*)
40A
(*) Per channel
OUTPUT CURRENT: 40A
3.0V CMOS COMPATIBLE INPUT
■ CURRENT SENSE DISABLE
■ PROPORTIONAL LOAD CURRENT SENSE
■ UNDERVOLTAGE SHUT-DOWN
■ OVERVOLTAGE CLAMP
■ THERMAL SHUT DOWN
■ CURRENT AND POWER LIMITATION
■
■
PowerSSO-24
VERY LOW STAND-BY CURRENT
■ PROTECTION AGAINST LOSS OF GROUND
AND LOSS OF VCC
■ VERY LOW ELECTROMAGNETIC
SUSCEPTIBILITY
■ OPTIMIZED ELECTROMAGNETIC EMISSION
■ REVERSE BATTERY PROTECTION (**)
■ IN COMPLIANCE WITH THE 2002/95/EC
EUROPEAN DIRECTIVE
■
This device integrates an analog current sense
which delivers a current proportional to the load
current (according to a known ratio) when CS_DIS
is driven low or left open.
When CS_DIS is driven high, the CURRENT
SENSE pin is in a high impedance condition.
Output current limitation protects the device in
overload condition. In case of long overload
duration, the device limits the dissipated power to
safe level up to thermal shut-down intervention.
Thermal shut-down with automatic restart allows
the device to recover normal operation as soon as
fault condition disappears.
DESCRIPTION
The VND5012AK-E is a monolithic device made
using STMicroelectronics VIPower technology. It
is intended for driving resistive or inductive loads
with one side connected to ground. Active V CC pin
voltage clamp protects the device against low
energy
spikes
(see
ISO7637
transient
compatibility table).
Table 2. Order Codes
Package
Tube
Tape and Reel
PowerSSO-24
VND5012AK-E
VND5012AKTR-E
Note: (**) See application schematic at page 8
Rev. 3
January 2005
This is preliminary information on a new product now in development. Details are subject to change without notice.
1/13
VND5012AK-E
Figure 2. Block Diagram
VCC
UNDERVOLTAGE
VCC
CLAMP
OUTPUT1
PwCLAMP 1
GND
CURRENT
SENSE1
DRIVER 1
ILIM 1
INPUT1
LOGIC
PwCLAMP 2
DRIVER 2
VDSLIM 1
PwrLIM 1
OUTPUT2
ILIM 2
OVERTEMP. 1
INPUT2
VDSLIM 2
IOUT1
K1
CURRENT
SENSE2
OVERTEMP. 2
IOUT2
K2
PwrLIM 2
CS_DIS
Table 3. Pin Function
Name
VCC
OUTPUT1,2
Function
Battery connection
Power output
GND
Ground connection. Must be reverse battery protected by an external diode/resistor network
INPUT1,2
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state
CURRENT SENSE1,2 Analog current sense pin, delivers a current proportional to the load current
CS_DIS
Active high CMOS compatible pin, to disable the current sense pin
Figure 3. Current and Voltage Conventions
IS
VCC
IOUT1
ICSD
OUTPUT1
CS_DIS
VCSD
CURRENT
SENSE1
IIN1
INPUT1
VIN1
VSENSE1
OUTPUT2
VOUT2
INPUT2
GND
CURRENT
SENSE2
IGND
(*) VFn = VCC - VOUTn during reverse battery condition
2/13
VOUT1
ISENSE1
IOUT2
IIN2
VIN2
VF (*)
ISENSE2
VSENSE2
VCC
VND5012AK-E
Figure 4. Configuration Diagram (Top View) & Suggested Connections For Unused and n.c. Pins
VCC
GND
N.C.
INPUT2
N.C.
INPUT1
N.C.
CURRENT SENSE1
N.C.
CURRENT SENSE2
CS_DIS
VCC
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
TAB = VCC
Connection / Pin
Current Sense
N.C.
Output
Input
X
X
X
X
Through 10KΩ
resistor
Through 10KΩ
resistor
Floating
To Ground
Through 1KΩ
resistor
X
CS_DIS
Table 4. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
41
V
VCC
DC supply voltage
-VCC
Reverse DC supply voltage
-0.3
V
- IGND
DC reverse ground pin current
-200
mA
Internally limited
A
IOUT
- IOUT
IIN
ICSD
VCSENSE
VESD
Tj
Tstg
DC output current
Reverse DC output current
-30
A
DC input current
-1 to 10
mA
DC current sense disable input current
-1 to 10
mA
VCC-41
V
+VCC
V
2000
V
Junction operating temperature
-40 to 150
°C
Storage temperature
-55 to 150
°C
Current sense maximum voltage
Electrostatic discharge (R=1.5kΩ; C=100pF)
Table 5. Thermal Data
Symbol
Parameter
Rthj-case
Thermal resistance junction-case
Rthj-amb
Thermal resistance junction-ambient
Note: 1. When mounted on a standard single-sided FR4 board with
1cm 2
Max Value
Unit
1.7
°C/W
52 (see note 1)
°C/W
of Cu (at least 35µm thick) connected to TAB.
3/13
VND5012AK-E
ELECTRICAL CHARACTERISTICS (8V<VCC<36V; -40°C<Tj<150°C, unless otherwise specified)
Table 6. Power Section
Symbol
Parameter
VCC
Operating supply voltage
VUSD
VUSDhyst
RON
Min.
Typ.
Max.
Unit
4.5
13
36
V
Undervoltage shutdown
3
4.5
V
Undervoltage shut-down
hysteresis
0.5
On state resistance
Test Conditions
IOUT=5A; Tj=25°C
12
mΩ
IOUT=5A; Tj=150°C
24
mΩ
IOUT=5A; VCC=5V; Tj=25°C
16
mΩ
46
52
V
2(**)
5(**)
µA
3
6
mA
Vclamp
Clamp Voltage
IS=20 mA
IS
Supply current
Off State; VCC=13V; Tj=25°C;
VIN=VOUT=VSENSE=VCSD=0V
41
On State; VCC=13V; VIN=5V; IOUT=0A
IL(off)
Off state output current
V
VIN=VOUT=0V; VCC=13V; Tj=25°C
0
3
VIN=VOUT=0V; VCC=13V; Tj=125°C
0
5
µA
Note: (**) PowerMOS leakage included
Table 7. Switching (VCC=13V)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
td(on)
Turn-on delay time
RL=2.6Ω
15
µs
td(off)
Turn-off delay time
RL=2.6Ω
40
µs
(dVOUT/dt)on
Turn-on voltage slope
RL=2.6Ω
0.3
V/µs
(dVOUT/dt)off
Turn-off voltage slope
RL=2.6Ω
0.35
V/µs
WON
Switching energy losses at
turn-on
RL=2.6Ω
TBD
mJ
WOFF
Switching energy losses at
turn-off
RL=2.6Ω
TBD
mJ
4/13
VND5012AK-E
ELECTRICAL CHARACTERISTICS (continued)
Table 8. Logic Input
Symbol
Parameter
VIL
Input low level voltage
IIL
Low level input current
VIH
Input high level voltage
IIH
High level input current
VI(hyst)
Input hysteresis voltage
VICL
Input clamp voltage
VCSDL
CS_DIS low level voltage
ICSDL
Low level CS_DIS current
VCSDH
CS_DIS high level voltage
ICSDH
High level CS_DIS current
VCSD(hyst)
CS_DIS hysteresis voltage
VCSCL
CS_DIS clamp voltage
Test Conditions
VIN=0.9 V
Min.
Typ.
Max.
Unit
0.9
V
1
µA
2.1
V
VIN= 2.1 V
10
0.25
IIN=1mA
V
5.5
IIN=-1mA
TBD
-0.7
V
1
µA
2.1
V
VCSD= 2.1 V
10
0.25
ICSD=1mA
V
V
0.9
VCSD= 0.9V
µA
V
5.5
ICSD=-1mA
µA
TBD
-0.7
V
V
Table 9. Protections and Diagnostics (see note 2)
Symbol
Parameter
IlimH
DC Short circuit current
IlimL
Short circuit current
during thermal cycling
TTSD
Shutdown temperature
TR
Reset temperature
TRS
Thermal reset of STATUS
THYST
VDEMAG
VON
Test Conditions
VCC=13V
Min.
Typ.
Max.
Unit
40
60
80
A
80
A
5V<VCC<36V
VCC=13V; TR<Tj<TTSD
24
150
175
A
200
TRS + 1 TRS + 5
135
Thermal hysteresis
(TTSD-TR)
Turn-off output voltage
clamp
IOUT=2A; VIN=0; L=6mH
Output voltage drop
IOUT=0.4A
limitation
Tj= -40°C...+150°C (see fig. 9)
°C
°C
°C
7
°C
VCC-41 VCC-46 VCC-52
V
25
mV
Note: 2. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be
used together with a proper software strategy. If the device operates under abnormal conditions this software must limit the duration
and number of activation cycles.
5/13
VND5012AK-E
ELECTRICAL CHARACTERISTICS (continued)
Table 10. Current Sense (8V<VCC<16V)
Symbol
Parameter
K1
IOUT/ISENSE
K2
IOUT/ISENSE
Test Conditions
Min.
Typ.
Max.
TBD
5000
TBD
Tj=-40°C
TBD
5000
TBD
Tj=25°C...150°C
TBD
5000
TBD
Tj=-40°C
TBD
5000
TBD
Tj=25°C...150°C
TBD
5000
TBD
IOUT=1.5A; VSENSE=0.5V; VCSD=0V;
Tj= -40°C...150°C
Unit
IOUT=10A; VSENSE=4V; VCSD=0V;
IOUT=25A; VSENSE=4V; VCSD=0V;
K3
IOUT/ISENSE
IOUT=0A; VSENSE=0V;
ISENSE0
VSENSE
Analog sense current
Max analog sense
output voltage
VCSD=5V; VIN=0V; Tj=-40°C...150°C
0
5
µA
VCSD=0V; VIN=5V; Tj=-40°C...150°C
0
10
µA
IOUT=15A; VCSD=0V; RSENSE=3.9KΩ
5
V
VSENSEH
Analog sense output
voltage in
overtemperature condition
VCC=13V; RSENSE=3.9KΩ
9
V
ISENSEH
Analog sense output
current in
overtemperature condition
VCC=13V
8
mA
tDSENSE1H
Delay Response time from
falling edge of CS_DIS pin
VSENSE<4V,
tDSENSE1L
Delay Response time from
rising edge of CS_DIS pin
VSENSE<4V,
tDSENSE2H
Delay Response time from
rising edge of INPUT pin
VSENSE<4V,
tDSENSE2L
Delay Response time from
falling edge of INPUT pin
VSENSE<4V,
1.5A<Iout<25A
ISENSE=90% of ISENSE max (see fig 5)
1.5A<Iout<25A
ISENSE=10% of ISENSE max (see fig 5)
1.5A<Iout<25A
ISENSE=90% of ISENSE max (see fig 5)
1.5A<Iout<25A
ISENSE=10% of ISENSE max (see fig 5)
50
100
µs
5
20
µs
270
600
µs
100
250
µs
Table 11. Truth Table
CONDITIONS
Normal operation
Overtemperature
Undervoltage
Short circuit to GND
Short circuit to VCC
Negative output voltage
clamp
INPUT
OUTPUT
SENSE (VCSD=0V)
(see note 3)
L
H
L
L
H
L
0
Nominal
0
H
L
L
L
VSENSEH
0
H
L
L
L
0
0
H
L
L
H
0
0
H
H
< Nominal
L
L
0
Note: 3. If the VCSD is high, the SENSE output is at a high impedance.
6/13
VND5012AK-E
Figure 5.
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
tDSENSE2H
tDSENSE1L
tDSENSE1H
tDSENSE2L
Figure 6.
VOUT
90%
80%
dVOUT/dt(off)
dVOUT/dt(on)
10%
tr
tf
t
INPUT
td(on)
td(off)
t
Table 12. Electrical Transient Requirements
ISO T/R 7637/1
Test Pulse
1
2
3a
3b
4
5
ISO T/R 7637/1
Test Pulse
1
2
3a
3b
4
5
CLASS
C
E
I
II
TEST LEVELS
III
IV
-25 V
+25 V
-25 V
+25 V
-4 V
+26.5 V
-50 V
+50 V
-50 V
+50 V
-5 V
+46.5 V
-75 V
+75 V
-100 V
+75 V
-6 V
+66.5 V
-100 V
+100 V
-150 V
+100 V
-7 V
+86.5 V
I
C
C
C
C
C
C
TEST LEVELS RESULTS
II
III
C
C
C
C
C
C
C
C
C
C
E
E
Delays and
Impedance
2 ms 10 Ω
0.2 ms 10 Ω
0.1 µs 50 Ω
0.1 µs 50 Ω
100 ms, 0.01 Ω
400 ms, 2 Ω
IV
C
C
C
C
C
E
CONTENTS
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure to disturbance
and cannot be returned to proper operation without replacing the device.
7/13
VND5012AK-E
Figure 7. Application Schematic
+5V
VCC
Rprot
CS_DIS
Dld
µC
Rprot
INPUT
OUTPUT
Rprot
CURRENT SENSE
GND
RSENSE
RGND
VGND
DGND
Note: Channel 2 has the same internal circuit as channel 1.
GND PROTECTION
REVERSE BATTERY
NETWORK
AGAINST
Solution 1: Resistor in the ground line (RGND only). This
can be used with any type of load.
The following is an indication on how to dimension the
RGND resistor.
1) RGND ≤ 600mV / (IS(on)max).
2) RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can
be found in the absolute maximum rating section of the
device datasheet.
Power Dissipation in RGND (when VCC<0: during reverse
battery situations) is:
PD= (-VCC)2/RGND
This resistor can be shared amongst several different
HSDs. Please note that the value of this resistor should
be calculated with formula (1) where IS(on)max becomes
the sum of the maximum on-state currents of the different
devices.
Please note that if the microprocessor ground is not
shared by the device ground then the RGND will produce a
shift (IS(on)max * RGND) in the input thresholds and the
status output values. This shift will vary depending on
how many devices are ON in the case of several high side
drivers sharing the same RGND.
If the calculated power dissipation leads to a large
resistor or several devices have to share the same
resistor then ST suggests to utilize Solution 2 (see
below).
Solution 2: A diode (DGND) in the ground line.
8/13
A resistor (RGND=1kΩ) should be inserted in parallel to
DGND if the device drives an inductive load.
This small signal diode can be safely shared amongst
several different HSDs. Also in this case, the presence of
the ground network will produce a shift (j600mV) in the
input threshold and in the status output values if the
microprocessor ground is not common to the device
ground. This shift will not vary if more than one HSD
shares the same diode/resistor network.
LOAD DUMP PROTECTION
Dld is necessary (Voltage Transient Suppressor) if the
load dump peak voltage exceeds the VCC max DC rating.
The same applies if the device is subject to transients on
the VCC line that are greater than the ones shown in the
ISO T/R 7637/1 table.
µC I/Os PROTECTION:
If a ground protection network is used and negative
transient are present on the VCC line, the control pins will
be pulled negative. ST suggests to insert a resistor (Rprot)
in line to prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the
leakage current of µC and the current required by the
HSD I/Os (Input levels compatibility) with the latch-up
limit of µC I/Os.
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
5kΩ ≤ Rprot ≤ 65kΩ.
Recommended Rprot value is 10kΩ.
VND5012AK-E
Figure 8. Waveforms
NORMAL OPERATION
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
UNDERVOLTAGE
VUSDhyst
VCC
VUSD
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
SHORT TO VCC
INPUT
CS_DIS
LOAD VOLTAGE
LOAD CURRENT
SENSE CURRENT
<Nominal
<Nominal
OVERLOAD OPERATION
Tj
TTSD
TR
TRS
INPUT
CS_DIS
ILIMH
ILIML
LOAD CURRENT
VSENSEH
SENSE CURRENT
current power
limitation limitation
thermal cycling
SHORTED LOAD
NORMAL LOAD
9/13
VND5012AK-E
Figure 9.
Vcc-Vout
Tj=150oC
Tj=25oC
Tj=-40oC
Von
Von/Ron(T)
10/13
Iout
VND5012AK-E
PACKAGE MECHANICAL
Table 13. PowerSSO-24™ Mechanical Data
Symbol
millimeters
Min
Typ
Max
A
1.9
2.22
A2
1.9
2.15
a1
0
0.07
b
0.34
c
0.23
0.32
D
10.2
10.4
E
7.4
7.6
0.4
e
0.8
e3
8.8
0.46
G
0.1
G1
0.06
H
10.1
h
L
10.5
0.4
0.55
N
0.85
10º
X
3.9
4.3
Y
6.1
6.5
Figure 10. PowerSSO-24™ Package Dimensions
11/13
VND5012AK-E
REVISION HISTORY
Table 14. Revision History
12/13
Date
Revision
Description of Changes
Sep. 2004
1
- First issue.
Oct. 2004
2
- Minor text changes.
Jan. 2005
3
- Minor text changes.
VND5012AK-E
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of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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 2004 STMicroelectronics - All rights reserved
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13/13