HCF40193B PRESETTABLE UP/DOWN COUNTERS (DUAL CLOCK WITH RESET) BINARY TYPE ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ INDIVIDUAL CLOCK LINES FOR COUNTING UP OR COUNTING DOWN SYNCHRONOUS HIGH-SPEED CARRY AND BORROW PROPAGATION DELAYS FOR CASCADING ASYNCHRONOUS RESET AND PRESET CAPABILITY MEDIUM-SPEED OPERATION - fCL = 8MHz (typ.) AT 10 V STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIF. UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DESCRIPTION HCF40193B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF40193B Presettable Binary Up/Down Counter consists of 4 synchronously clocked, GATED "D" type flip-flops connected as a counter. The inputs consist of four individual jam lines, a PRESET ENABLE control, individual CLOCK UP and CLOCK DOWN signals and a master RESET. Four buffered Q signal outputs as well as CARRY DIP SOP ORDER CODES PACKAGE TUBE T&R DIP SOP HCF40193BEY HCF40193BM1 HCF40193M013TR and BORROW outputs for multiple-stage counting schemes are provided. The counter is cleared so that all outputs are in a low state by a high on the RESET line. A RESET is accomplished asynchronously with the clock. Each output is individually programmable asynchronously with the clock to the level on the corresponding jam input when the PRESET ENABLE control is low. The counter counts up one count on the positive clock edge of the CLOCK UP signal provided the CLOCK DOWN line is high. The counter counts down one count on the positive clock edge of the CLOCK DOWN signal provided the CLOCK UP line is high. The CARRY and BORROW signals are high when the counter counts up or down. The CARRY signal goes low one-half clock cycle after the counter reaches its maximum count in the count-up mode. The BORROW signal goes low PIN CONNECTION September 2002 1/12 HCF40193B one-half clock cycle after the counter reaches its minimum count in the count-down mode. The cascading of multiple packages is easily accomplished without the need for additional external circuitry by tying the BORROW and CARRY outputs to the CLOCK DOWN and CLOCK UP inputs, respectively, of the following package. IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 3, 2, 6, 7 8 Q1 to Q4 CLOCK DOWN CLOCK UP PRESET ENABLE CARRY BORROW RESET J1 to J4 VSS 16 VDD 4 5 11 12 13 14 15, 1, 10, 9 FUNCTIONAL DIAGRAM 2/12 NAME AND FUNCTION Flip-Flop Outputs Clock Down Input Clock Up Input Preset Enable Input Count Up (Carry) Count Down (Borrow) Reset Input Data Input Negative Supply Voltage Positive Supply Voltage HCF40193B LOGIC DIAGRAM TRUTH TABLE CLOCK UP CLOCK DOWN PRESET ENABLE RESET ACTION H H L COUNT UP H H L NO COUNT H H L COUNT DOWN H H L NO COUNT L X L H PRESET RESET X X X X (X) : Don’t Care 3/12 HCF40193B TIMING DIAGRAM INTERNAL LOGIG OF FLIP-FLOP 4/12 HCF40193B ABSOLUTE MAXIMUM RATINGS Symbol VDD Parameter Supply Voltage VI DC Input Voltage II DC Input Current PD Value Unit -0.5 to +22 V -0.5 to VDD + 0.5 ± 10 V mA 200 100 mW mW Top Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature -55 to +125 °C Tstg Storage Temperature -65 to +150 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage. RECOMMENDED OPERATING CONDITIONS Symbol VDD Parameter Supply Voltage VI Input Voltage Top Operating Temperature Value Unit 3 to 20 V 0 to VDD V -55 to 125 °C 5/12 HCF40193B DC SPECIFICATIONS Test Condition Symbol IL VOH VOL VIH VIL IOH IOL II CI Parameter Quiescent Current High Level Output Voltage Low Level Output Voltage VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 High Level Input Voltage Low Level Input Voltage Output Drive Current Output Sink Current Input Leakage Current Input Capacitance VO (V) 0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 Value |IO| VDD (µA) (V) <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 Any Input Any Input 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 TA = 25°C Min. Typ. Max. 0.04 0.04 0.04 0.08 5 10 20 100 4.95 9.95 14.95 -40 to 85°C -55 to 125°C Min. Min. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 4.95 9.95 14.95 3.5 7 11 1.5 3 4 -3.2 -1 -2.6 -6.8 1 2.6 6.8 ±0.1 5 7.5 0.05 0.05 0.05 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V 6/12 V V 1.5 3 4 ±1 µA V 3.5 7 11 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 ±10-5 Max. 150 300 600 3000 0.05 0.05 0.05 3.5 7 11 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 Max. Unit V mA mA ±1 µA pF HCF40193B DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns) Test Condition Symbol Parameter tPLH tPHL Propagation Delay Time Clock Up or Clock Down to Q Reset to Q PE to Q Clock Up to Carry Clock Down to Borrow Reset or PR to Borrow or Carry tTHL tTLH Transition Time trem* Removal Time Reset or PE tW Clock Input Pulse Width Reset PE Clock tr tf fCL Clock Input Rise or Fall Time Maximum Clock Input Frequency VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Value (*) Min. 80 40 30 480 300 260 2 5 5.5 Unit Typ. Max. 250 120 90 200 100 70 160 80 60 300 150 110 100 50 40 40 20 15 240 150 130 120 85 70 90 45 30 500 240 180 400 200 140 320 160 120 600 300 220 200 100 80 4 8 11 ns ns ns ns ns ns ns 240 170 140 180 90 60 15 15 5 ns ns µs MHz (*) The time required for Reset or Preset Enable control to be removed before clocking (see timing diagram). 7/12 HCF40193B TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200KΩ RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1 : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle) 8/12 HCF40193B WAVEFORM 2 : MINIMUM PULSE WIDTH AND REMOVAL TIME (f=1MHz; 50% duty cycle) TYPICAL APPLICATION: CASCADED COUNTER PACKAGES 9/12 HCF40193B Plastic DIP-16 (0.25) MECHANICAL DATA mm. inch DIM. MIN. a1 0.51 B 0.77 TYP MAX. MIN. TYP. MAX. 0.020 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L Z 3.3 0.130 1.27 0.050 P001C 10/12 HCF40193B SO-16 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45˚ (typ.) D 9.8 E 5.8 10 0.385 6.2 0.228 0.393 0.244 e 1.27 0.050 e3 8.89 0.350 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.62 0.024 8 ˚ (max.) PO13H 11/12 HCF40193B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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