L9903 MOTOR BRIDGE CONTROLLER 1 ■ ■ ■ ■ ■ ■ ■ ■ ■ FEATURES Figure 1. Package OPERATING SUPPLY VOLTAGE 8V TO 20V, OVERVOLTAGE MAX. 40V OPERATING SUPPLY VOLTAGE 6V WITH IMPLEMENTED STEPUP CONVERTER QUIESCENT CURRENT IN STANDBY MODE LESS THAN 50µA ISO 9141 COMPATIBLE INTERFACE CHARGE PUMP FOR DRIVING A POWER MOS AS REVERSE BATTERY PROTECTION PWM OPERATION FREQUENCY UP TO 30KHZ PROGRAMMABLE CROSS CONDUCTION PROTECTION TIME OVERVOLTAGE, UNDERVOLTAGE, SHORT CIRCUIT AND THERMAL PROTECTION REAL TIME DIAGNOSTIC SO20 Table 1. Order Codes Part Number Package L9903 SO20 L9903TR Tape & Reel 2 DESCRIPTION Control circuit for power MOS bridge driver in automotive applications with ISO 9141bus interface. Figure 2. Block Diagram VS 10 ST 1 R CP Reference BIAS + VCC Charge pump = V STH f ST VCC EN 2 4 REN DIR CB1 12 GH1 14 S1 Thermal shutdown Control Logic DG CP 13 Overvoltage Undervoltage RDG 11 5 R DIR R S1 V S1TH = 19 GL1 R GL1 18 GL2 R GL2 VCC 17 R PWM PWM R S2 V S2TH = PR 6 Timer ISO-Interface RX 8 15 GH2 16 CB2 9 7 R RX VCC TX K = 0.5 • V VS R TX I KH 20 October 2005 S2 3 GND REV. 4 1/17 L9903 Table 2. Pin Function N° Pin 1 ST 2 DG 3 PWM Description Open Drain Switch for Stepup converter Open drain diagnostic output PWM input for H-bridge control 4 EN Enable input 5 DIR Direction select input for H-bridge control 6 PR Programmable cross conduction protection time 7 RX ISO 9141 interface, receiver output 8 TX ISO 9141 interface, transmitter input 9 K 10 VS ISO 9141 Interface, bidirectional communication K-line Supply voltage 11 CP Charge pump for driving a power MOS as reverse battery protection 12 GH1 Gate driver for power MOS highside switch in halfbridge 1 13 CB1 External bootstrap capacitor 14 S1 Source/drain of halfbridge 1 15 GH2 16 CB2 External bootstrap capacitor 17 S2 Source/drain of halfbridge 2 18 GL2 Gate driver for power MOS lowside switch in halfbridge 2 19 GL1 Gate driver for power MOS lowside switch in halfbridge 1 20 GND Ground Gate driver for power MOS highside switch in halfbridge 2 Figure 3. Pin Connection (Top view) ST 1 20 GND DG 2 19 GL1 PWM 3 18 GL2 EN 4 17 S2 DIR 5 16 CB2 PR 6 15 GH2 RX 7 14 S1 TX 8 13 CB1 K 9 12 GH1 10 11 CP VS SO20 2/17 L9903 Table 3. Absolute Maximum Ratings Symbol Parameter Value VCB1 , VCB2 Bootstrap voltage ICB1 , ICB2 Bootstrap current VCP Charge pump voltage ICP Charge pump current VDIR ,VEN Logic input voltage ,VPWM ,VTX Unit -0.3 to 40 V -100 mA -0.3 to 40 V -1 mA -0.3 to 7 V ±1 mA IDIR ,IEN ,IPWM ,ITX Logic input current VDG ,VRX Logic output voltage -0.3 to 7 V IDG ,IRX Logic output current -1 mA -0.3 to VSX + 10 V VGH1, VGH2 Gate driver voltage IGH1 , IGH2 Gate driver current VGL1 , VGL2 Gate driver voltage IGL1 , IGL2 Gate driver current -1 mA -0.3 to 10 V -10 mA VK K-line voltage -20 to VS V VPR Programming input voltage -0.3 to 7 V IPR Programming input current -1 mA VS1 , VS2 Source/drain voltage -2 to VVS + 2 V IS1 , IS2 Source/drain current -10 mA VST Output voltage IST Step up output current VVSDC VVSP IVS DC supply voltage Pulse supply voltage (T < 500ms) DC supply current -0.3 to 40 V -1 mA -0.3 to 27 V 40 V -100 mA For externally applied voltages or currents exceeding these limits damage of the device may occur! All pins of the IC are protected against ESD. The verification is performed according to MIL883C, human body model with R=1.5kΩ, C=100pF and discharge voltage ±2kV, corresponding to a maximum discharge energy of 0.2mJ. Table 4. Thermal Data Symbol TJ Parameter Operating junction temperature TJSD Junction temperature thermal shutdown threshold TJSDH Junction thermal shutdown hysteresis Rth j-amb Thermal resistance junction to ambient 1) Value Unit -40 to 150 °C min 150 °C typ 15 °C 85 °C/W 1. see application note 110 for SO packages. . 3/17 L9903 Table 5. Electrical Characteristcs (8V < VVS < 20V, VEN = HIGH, -40°C ≤ TJ ≤ 150°C, unless otherwise specified. The voltages are refered to GND and currents are assumed positive, when current flows into the pin Symbol Parameter Test Condition Min. Typ. Max. Unit 20 22 24 V Supply (VS) VVS OVH Overvoltage disable HIGH threshold VVS OVh Overvoltage threshold hysteresis 2) VVS UVH Undervoltage disable HIGH threshold VVS UVh Undervoltage threshold hysteresis 2) 1.6 6 V 7 0.66 IVSL Supply current VEN = 0 ; VVS = 13.5V; TJ< 85°C IVSH Supply current, pwm-mode VVS= 13.5V; VEN= HIGH; VDIR= LOW; S1 = S2 = GND V V 50 µA 8.1 13 mA 5.8 10 mA fPWM = 20kHz; CCBX = 0.1µF; CGLX = 4.7nF; CGHX = 4.7nF; RPR = 10kΩ; CPR = 150pF IVSD Supply current, dc-mode VVS= 13.5V; VEN= HIGH; VDIR= LOW; S1 = S2 = GND VPWM = LOW; CGHX = 4.7nF RPR = 10kΩ; CPR = 150pF Enable input (EN) VENL Low level VENH High level VENh Hysteresis threshold 2) REN Input pull down resistance 1.5 3.5 1 VEN = 5V 16 V V 50 V 100 kΩ 1.5 V H-bridge control inputs (DIR, PWM) VDIRL VPWML Input low level VDIRH VPWMH Input high level VDIRh VPWMh Input threshold hysteresis 2) RDIR RPWM Internal pull up resistance to internal VCC 3) 3.5 V 1 VDIR = 0; VPWM = 0 16 50 V 100 kΩ 0.6 V kΩ DIAGNOSTIC output (DG) VDG Output drop IDG = 1mA RDG Internal pull up resistance to internal VCC 3) VDG = 0V 10 20 40 2 2.2 Programmable cross conduction protection 4) NPR Threshold voltage ratio VPRH/ VPRL RPR = 10kΩ 1.8 IPR Current capability VPR = 2V -0.5 mA ISO interface, transmission input (TX) VTXL 4/17 Input low level 1.5 V L9903 Table 5. Electrical Characteristcs (continued) (8V < VVS < 20V, VEN = HIGH, -40°C ≤ TJ ≤ 150°C, unless otherwise specified. The voltages are refered to GND and currents are assumed positive, when current flows into the pin Symbol Parameter VTXH Input high level VTXh Input hysteresis voltage 2) RTX Internal pull up resistance to internal VCC 3) Test Condition Min. Typ. Max. 3.5 V 1 VTX = 0 10 4.5 Unit 20 V 40 kΩ 5.5 V 10 20 kΩ 90 Ω ISO interface, receiver output (RX) VRXL Output voltage high stage TX = HIGH; IRX = 0; VK = VVS RRX Internal pull up resistance to internal VCC 3) TX = HIGH; VRX = 0V RRXON ON resistance to ground TX = LOW; IRX = 1mA 40 tRXH Output high delay time Fig. 1 0.5 µs tRXL Output low delay time 0.5 µs 5 ISO interface, K-line (K) VKL Input low level -20V 0.45 · VVS VKH Input high level 0.55 · VVS VVS VKh Input hysteresis voltage 2) IKH Input current VTX = HIGH RKON ON resistance to ground VTX = LOW; IK=10mA IKSC Short circuit current VTX = LOW 0.025· VVS Transmission frequency fK -5 10 40 60 0.8V 25 µA 30 Ω 130 100 mA kHz 2. not tested in production: guaranteed by design and verified in characterization 3. Internal VVCC is 4.5V ... 5.5V 4. see page 18 for calculation of programmable cross conduction protection time tKr Rise time 2 VVS = 13.5V; Fig. 1 External loads at K-line: RK = 510Ω pull up to VVS 6 µs CK = 2.2nF to GND tKf Fall time 2 6 µs tKH Switch high delay time 4 17 µs tKL Switch low delay time 4 17 µs tSH Short circuit detection time 10 40 µs VVS +7V VVS +10V VVS +10V VVS +14V VVS +14V VVS +14V VVS = 13.5V; TX = LOW VK > 0.55 · VVS Charge pump VCP Charge pump voltage VVS = 8V VVS = 13.5V VVS = 20V 5/17 L9903 Table 5. Electrical Characteristcs (continued) (8V < VVS < 20V, VEN = HIGH, -40°C ≤ TJ ≤ 150°C, unless otherwise specified. The voltages are refered to GND and currents are assumed positive, when current flows into the pin Symbol Parameter Test Condition Min. Typ. -50 -75 ICP Charging current VCP= VVS + 8V VVS = 13.5V tCP Charging time 2) VCP= VVS + 8V VVS = 13.5V CCP = 10nF fCP Charge pump frequency VVS = 13.5V 250 7.5 10 10 Max. Unit µA 1.2 4 ms 500 750 kHz 14 14 14 V V V 10 Ω 20 Ω 10 20 Ω Ω Drivers for external highside power MOS VCB1 VCB2 Bootstrap voltage VVS = 8V; ICBX = 0; VSX = 0 VVS =13.5V; ICBX = 0; VSX = 0 VVS = 20V; ICBX = 0; VSX = 0 RGH1L RGH2L ON-resistance of SINK stage VCBX = 8V; VSX = 0 IGHX = 50mA; TJ = 25°C VCBX = 8V; VSX = 0 IGHX = 50mA; TJ = 125°C RGH1H RGH2H ON-resistance of SOURCE stage IGHX = -50mA; TJ = 25°C IGHX = -50mA; TJ = 125°C VGH1H VGH2H Gate ON voltage (SOURCE) VVS= VSX = 8V; IGHX = 0; CCBX = 0.1µF VVS +6.5V VVS +14V VVS = VSX = 13.5V; IGHX = 0; CCBX = 0.1µF VVS +10V VVS +14V VVS = VSX = 20V; IGHX = 0; CCBX = 0.1µF VVS +10V VVS +14V RGH1 RGH2 RS1 RS2 Gate discharge resistance EN = LOW Sink resistance 10 100 kΩ 10 100 kΩ Drivers for external lowside power MOS RGL1L RGL2L ON-resistance of SINK stage IGLX = 50mA; TJ = 25°C IGLX = 50mA; TJ = 125°C 10 20 Ω Ω RGL1H, RGL2H ON-resistance of SOURCE stage IGLX = -50mA; TJ = 25°C IGLX = -50mA; TJ = 125°C 10 20 Ω Ω VGL1H, VGL2H Gate ON voltage (SOURCE) VVS = 8V; IGLX = 0 VVS = 13.5V; IGLX = 0 VVS = 20V; IGLX = 0 Gate discharge resistance EN = LOW RGL1 RGL2 7V 10V 10V 10 VVS VVS 14V 100 kΩ 2. not tested in production: guaranteed by design and verified in characterization Timing of the drivers tGH1LH tGH2LH Propagation delay time Fig. 2 VVS = 13.5V VS1 = VS2 =0 CCBX = 0.1µF RPR= 10kW 6/17 500 ns L9903 Table 5. Electrical Characteristcs (continued) (8V < VVS < 20V, VEN = HIGH, -40°C ≤ TJ ≤ 150°C, unless otherwise specified. The voltages are refered to GND and currents are assumed positive, when current flows into the pin Symbol Parameter tGH1LH tGH2LH Propagation delay time including cross conduction protection time tCCP tGH1HL tGH2HL Propagation delay time tGL1LH tGL2LH Propagation delay time tGL1LH tGL2LH Propagation delay time including cross conduction protection time tCCP tGL1HL tGL2HL Propagation delay time Test Condition Fig. 2 VVS = 13.5V VS1 = VS2 =0 CCBX = 0.1µF Min. Typ. Max. Unit 0.7 1 1.3 µs 500 ns 500 ns 1.3 µs 500 ns 1 µs 1 µs 1 µs 1 µs CPR= 150pF; RPR= 10kΩ; 5) Fig. 2 VVS = 13.5V VS1 = VS2 =0 CCBX = 0.1µF RPR= 10kΩ Fig. 2 VVS = 13.5V VS1 = VS2 =0 CCBX = 0.1µF 0.7 1 CPR= 150pF; RPR= 10kΩ; 5) tGH1r tGH2r Rise time tGH1f tGH2f Fall time tGL1r tGL2r Rise time tGL1f tGL2f Fall time Fig. 2 VVS = 13.5V VS1 = VS2 =0 CCBX = 0.1µF CGHX = 4.7nF CGLX = 4.7nF RPR= 10kΩ; Short Circuit Detection VS1TH VS2TH tSCd Threshold voltage 4 Detection time Step up converter (ST) 5 15 µs 10 V 2 V 20 Ω 149 kHz (5.2V ≤ VVS < 10V) VSTH ST disable HIGH threshold VSTh ST disable threshold hysteresis voltage 2) RDSON 10 V Open drain ON resistance 1 VVS = 5.2V; IST = 50mA fST Clock frequency 50 100 2. not tested in production: guaranteed by design and verified in characterization 5. tested with differed values in production but guaranteed by design and verified in characterization 7/17 L9903 Figure 4. Timing of the ISO-interface V TX 0.7 • V V C C 0.3 • V V C C 0.3 • V V C C t V K t KL t KH tKf t Kr 80 % I K > I K SC 0.55 • V V S 0.45 • V V S 20% t VR X t RXL t RXH 0.7 • V VC C 0.3 • V V C C t op e n d r ain tr ansis tor at K-pin t SH ON O FF Figure 5. Timing of the drivers for the external MOS regarding the inputs DIR and PWM PWM or DIR 50% tGHXLH tGHXr t tGHXHL tGHXf 80% GHX 20% tGLXHL tGLXf tGLXLH tGLXr t 80% GLX 20% t 8/17 L9903 Figure 6. I(V) characteristics of the K-Line for TX = HIGH and VVS=13.5V IK [mA] 0.2 ~5 0 k Ω 0.1 0.0 -0.1 ~5 0k Ω -0.2 -0.3 -0.4 -0.5 -20 -10 0 10 20 VK [V] Figure 7. Driving sequence EN D IR PWM braking G H1 G L1 G H2 Note: Before standby mode (EN = low) a braking phase is mandatory to discharge the stored energy of the motor. G L2 9/17 L9903 Figure 8. Charging time of an external capacitor of 10nF connected to CP pin at VVS=8V and VVS=13.5V voltage [V] Charging time of a 10nF load at CP 30 CP for VS=13.5V 25 CP for VS=8V 20 15 10 EN 5 0 0 1 2 3 4 time [ms] Figure 9. Application Circuit Diagram VBAT D1 VS Voltage Regulator CS1 10 R CP CS2 ST Reference BIAS + 1 VCC Charge pump = VSTH f ST VCC VCC DG 2 14 S1 4 5 R DIR C1 19 M R GL1 R GL1 18 R GL2 R GL2 VCC 17 R PWM PWM 3 PR CPR 6 Timer RPR ISO-Interface RX VCC CB2 15 GH2 16 CB2 9 7 R RX S2 R S2 V S2TH = K = 0.5 • VVS R TX TX GND 10/17 R R S1 Control Logic µC GH1 Thermal shutdown REN DIR CB1 12 CB1 V S1TH = EN CP 13 Overvoltage Undervoltage RDG 11 8 I KH 20 GND R K-Line L9903 3 FUNCTIONAL DESCRIPTION 3.1 General The L9903 integrated circuit (IC) is designed to control four external N-channel MOS transistors in H-Bridge configuration for DC-motor driving in automotive applications. It includes an ISO9141 compatible interface. A typical application is shown in fig.9. 3.2 Voltage supply The IC is supplied via an external reverse battery protection diode to the VVS pin. The typical operating voltage range is down to 8V. The supply current consumption of the IC composes of static and a dynamic part. The static current is typically 5.8mA. The dynamical current Idyn is depending of the PWM frequency fPWM and the required gate charge QGate of the external power mos transistor. The current can be estimated by the expression: Idyn = 2 · fPWM · QGate An external power transistor with a gate charge of QGate = 160nC and a PWM frequency of fPWM = 20kHz requires a dynamical supply current of Idyn = 6.4mA. The total supply current consumption is IVS = 5.8mA + 6.4mA = 12.2mA. 3.3 Extended supply voltage range (ST) The operating battery voltage range can be extended down to 6V using the additional components shown in fig.7. A small inductor of L~150µH (Ipeak~500mA) in series to the battery supply builts up a step up converter with the switching open drain output ST. The switching frequency is typical 100kHz with a fixed duty cycle of 50%. The step up converter starts below VVS < 8V, increases the supply voltage at the VS pin and switches off at VVS > 10V to avoid EME at nominal battery voltage. The diode D2 in series with the ST pin is necessary only for systems with negative battery voltage. No additional load can be driven by the step up converter. Figure 10. L9903 VBAT L1 D1 VS C1 C2 D2 ST + = VSTH f ST 11/17 L9903 3.4 Control inputs (EN, DIR, PWM) The cmos level inputs drive the device as shown in fig.7 and described in the truth table. The device is activated with enable input HIGH signal. For enable input floating (not connected) or VEN=0V the device is in standby mode. When activating the device a wake-up time of 50µs is recommended to stabilize the internal supplies. The DIR and PWM inputs control the driver of the external H-Bridge transistors. The motor direction can be choosen with the DIR input, the duty cycle and frequency with the PWM input. Unconnected inputs are defined by internal pull up resistors. During wake-up and braking and before disactivating the IC via enable both inputs should be driven HIGH. Table 6. Truth table: Status Control inputs Driver stage for external power MOS Device status Diagnostic Comment EN DIR PWM TS OV UV SC GH1 GL1 GH2 GL2 DG 1 0 x x x x x x R7) R R7) R T standby mode 2 1 x x 1 0 0 0 L L L L L thermal shutdown 3 1 x x 0 1 0 0 L L L L L overvoltage 4 1 x x 0 0 1 0 L L L L L undervoltage 5 1 x x 0 0 0 1 X6) X6) X6) X6 L short circuit 6) 6 1 0 0 0 0 0 0 L H H L H 7 1 x 1 0 0 0 0 H L H L H 8 1 1 0 0 0 0 0 H L L H H Symbols: x Don't care braking mode R:Resistive output TS:Thermal shutdown 0: Logic LOW or not active L: Output in sink condition OV:Overvoltage 1: Logic HIGH or active H: Output in source condition UV:Undervoltage T: Tristate SC:Short Circuit 6. Only those external MOS transistors of the H-Bridge which are in short circuit condition are switched off. All others remain driven by DIR and PWM. 7. See Application Note AN2229 3.5 Thermal shutdown When the junction temperature exceeds TJSD all driver are switched in sink condition (L), the K- output is off and the diagnostic DG is LOW until the junction temperature drops below TJSD - TJHYST. 3.6 Overvoltage Shutdown When the supply voltage VVS exceeds the overvoltage threshold VVSOVH all driver are switched in sink condition (L), the K- output is off and the diagnostic DG is LOW. 3.7 Undervoltage Shutdown For supply voltages below the undervoltage disable threshold the gate driver remains in sink condition (L) and the diagnostic DG is low. 12/17 L9903 3.8 Short Circuit Detection The output voltage at the S1 and S2 pin of the H-Bridge is monitored by comparators to detect shorts to ground or battery. The activated external highside MOS transistor will be switched off if the voltage drop remains below the comparator threshold voltage VS1TH and VS2TH for longer than the short current detection time tSCd. The transistor remains in off condition, the diagnostic output goes LOW until the DIR or PWM input status will be changed. The status doesn't change for the other MOS transistors. The external lowside MOS transistor will be switched off if the voltage drop passes over the comparator threshold voltage VS1TH and VS2TH for longer than the short current detection time tSCd. The transistor remains in off condition, the diagnostic output goes LOW until the DIR or PWM input status will be changed. The status doesn't change for the other MOS transistors. 3.9 Diagnostic Output (DG) The diagnostic output provides a real time error detection, if monitors the following error stacks: Thermal shutdown, overvoltage shutdown , undervoltage shutdown and short circuit shutdown. The open drain output with internal pull up resistor is LOW if an error is occuring. 3.10 Bootstrap capacitor (CB1,CB2) To ensure, that the external power MOS transistors reach the required RDSON, a minimum gate source voltage of 5V for logic level and 10V for standard power MOS transistors has to be guaranteed. The highside transistors require a gate voltage higher than the supply voltage. This is achieved with the internal chargepump circuit in combination with the bootstrap capacitor. The bootstrap capacitor is charged, when the highside MOS transistor is OFF and the lowside is ON. When the lowside is switched OFF, the charged bootstrap capacitor is able to supply the gate driver of the highside power MOS transistor. For effective charging the values of the bootstrap capacitors should be larger than the gate-source capacitance of the power MOS and respect the required PWM ratio. 3.11 Chargepump circuit (CP) The reverse battery protection can be obtained with an external N-channel MOS transistor as shown in fig.6. In this case its drain-bulk diode provides the protection. The output CP is intended to drive the gate of this transistor above the battery voltage to switch on the MOS and to bypass the drain-bulk diode with the RDSON. The CP has a connection to VS through an internal diode and a 20kΩ resistor. 3.12 Gate drivers for the external N-channel power MOS transistors (GH1, GH2, GL1, GL2) High level at EN activates the driver of the external MOS under control of the DIR and PWM inputs (see truth table and driving sequence fig.4). The external power MOS gates are connected via series resistors to the device to reduce electro magnetic emission (EME) of the system. The resistors influence the switching behaviour. They have to be choosen carefully. Too large resistors enlarge the charging and discharging time of the power MOS gate and can generate cross current in the halfbridges. The driver assures a longer switching delay time from source to sink stage in order to prevent the cross conduction. The gate source voltage is limited to 14V. The charge/discharge current is limited by the RDSON of the driver. The drivers are not protected against shorts. 3.13 Programmable cross conduction protection The external power MOS transistors in H-Bridge ( two half bridges) configuration are switched on with an additional delay time tCCP to prevent cross conduction in the halfbridge. The cross conduction protection time tCCP is determined by the external capacitor CPR and resistor RPR at the PR pin. The capacitor CPR is charged up to the voltage limit VPRH. A level change on the control inputs DIR and PWM switches off the concerned external MOS transistor and the charging source at the PR pin. The resistor RPR discharges the capacitor CPR. The concerned external power MOS transistor will be switched on again when the voltage at PR reaches the value of VPRL. After that the CPR will be charged again. The capacitor CPR should be choosen between 100pF and 1nF. The resistor RPR should be higher than 7kW. The delay time can be expressed as follows: 13/17 L9903 tCCP= RPR · CPR · ln NPR with NPR= VPRH / VPRL = 2 tCCP= 0.69 · RPR · CPR 3.14 ISO-Interface The ISO-Interface provides the communication between the micro controller and a serial bus with a baud rate up to 60kbit/s via a single wire which is VBAT and GND compatible. The logic level transmission input TX drives the open drain K-output. The K output can be connected to a serial bus with a pull up resistor to VBAT. The Kpin is protected against overvoltage, short to GND and VS and can be driven beyond VVS and GND. During lack of VVS or GND the output shows high impedance characteristic. The open drain output RX with an internal pull up resistor monitors the status at the K-pin to read the received data and control the transmitted data. Short circuit condition at K-pin is recognized if the internal open drain transistor isn't able to pull the voltage potential at K-pin below the threshold of 0.45·VVS. Then the RX stays in high condition. A timer starts and switches the open drain transistor after typ. 20µs off. A next low at the TX input resets the timer and the open drain transistor switches on again. Figure 11. Functional schematic of the ISO-interface RX K R RX = VCC 0.5 •V VS R TX TX I KH R Q S 14/17 R delay T SH L9903 Figure 12. SO20 Mechanical Data & Package Dimensions mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.10 0.30 0.004 0.012 B 0.33 0.51 0.013 0.200 C 0.23 0.32 0.009 0.013 D (1) 12.60 13.00 0.496 0.512 E 7.40 7.60 0.291 0.299 e 1.27 0.050 H 10.0 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.40 1.27 0.016 0.050 k ddd OUTLINE AND MECHANICAL DATA 0˚ (min.), 8˚ (max.) 0.10 0.004 (1) “D” dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side. SO20 0016022 D 15/17 L9903 Table 7. Revision History Date Revision January 2004 3 Migration from ST-Press to EDOCS DMS October 2005 4 Inserted on pag 12 AN2229 ref. 16/17 Description of Changes L9903 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 17/17