Data Sheet TLE 6281G H-Bridge Driver IC Features Product Summary • Compatible to very low ohmic normal Turn on current level input N-Channel MOSFETs Turn off current • PWM – DIR - Interface Supply voltage range • PWM frequency up to 50kHz Gate Voltage • Operates down to 7.5V Temperature range supply voltage • Low EMC sensitivity and emission • Adjustable dead time with shoot through protection • Deactivation of dead time and shoot through protection possible • Short circuit protection for each Mosfet • Driver undervoltage shut down • Reverse polarity protection for the driver IC • Fast disable function / Inhibit for low quiescent current • Input with TTL characteristics • 2 bit diagnosis • Thermal overload warning for driver IC • Shoot through protection • Integrated bootstrap diodes 850 580 7.5 … 60 10 -40...+150 IGxx(on) IGxx(off) VVs VGS TJ mA mA V V °C P-DSO-20 Application • Dedicated for DC-brush high current motor bridges in PWM control mode for 12, 24 and 42V powernet applications. • The input structure allows an easy control of a DC-brush motor General Description H-bridge driver IC for MOSFET power stages with multiple protection functions Block Diagram VS Charge Pump Linear Regulator BH1 BH2 GND INH INH HS1 PWM DIR Floating HS Driver 1 + VGS limitation HS1 + Short circuit SCD detect. + Undervoltage Input control LS1 HS2 DT/DIS Dead time Level LS2 Undervoltage OR Shift Undervoltage HSx Undervoltage LSx ER1 ER2 Short circuit Detect. Short Circuit Detection Floating LS Driver 1 + VGS limitation LS1 + Short circuit SCD detect. + Undervoltage Floating LS Driver 2 + VGS limitation LS2 + Short circuit SCD detect. + Undervoltage Overtemp. warning Tj > 170oC typ. Data Sheet Floating HS Driver 2 + VGS limitation HS2 + Short circuit SCD detect. + Undervoltage 1 DH1 GH1 SH1 DH2 GH2 SH2 GL1 SL1 GL2 SL2 Rev 2.3 2007-01-11 Data Sheet TLE 6281G Example Application Circuit Watchdog Reset Q TLE 4278G I VS=12V RVS 10 Ω D CQ 22µF CS 47µF CD 47nF CS 1µF RQ 47kΩ WD R RQ 47kΩ VCC VS BH1 CB 220nF DH1 ER1 GH1 ER2 SH1 CB 220nF BH2 INH DH2 68kΩ GH2 DT/ DIS BCR192W µC RDT 10kΩ RINH 220kΩ SH2 M TLE6281G GL1 PWM SL1 DIR GL2 SL2 GND RB1 12kΩ RB2 12kΩ This example application circuit shows one possibility to use this Driver IC. Data Sheet 2 Rev 2.3 2007-01-11 Data Sheet TLE 6281G Pin Symbol Function 1 DT / DIS a) Set adjustable dead time by external resistor b) Reset ERx register c) Disable output stages Data Sheet 2 ER1 Error flag for driver shut down 3 DIR Control input for spinning direction of the motor 4 PWM Control input for PWM frequency and duty cycle 5 SL2 Connection to source low side switch 2 6 SL1 Connection to source low side switch 1 7 GND Logic Ground 8 VS Voltage supply 9 ER2 Warning flag Temperature / distinguish if short circuit or undervoltage lock out occurred 10 INH Sets complete device to sleep mode to achieve low quiescent currents 11 GL1 Output to gate low side switch 1 12 SH1 Connection to source high side switch 1 13 GH1 Output to gate high side switch 1 14 BH1 Bootstrap supply high side switch 1 15 DH1 Sense contact for short circuit detection high side 1 16 DH2 Sense contact for short circuit detection high side 2 17 BH2 Bootstrap supply high side switch 2 18 GH2 Output to gate high side switch 2 19 SH2 Connection to source high side switch 2 20 GL2 Output to gate low side switch 2 3 Rev 2.3 2007-01-11 Data Sheet TLE 6281G Maximum Ratings at Tj=-40…+150°C unless specified otherwise Parameter Symbol Supply voltage 1 Operating temperature range Storage temperature range Max. voltage range at PWM, DIR, DT/DIS Max. voltage range at ERx Max. voltage range at INH Max. voltage range at BHx Max. voltage range at DHx2 Max. voltage range at GHx3 Max. voltage range at SHx3 Max. voltage range at GLx Max. voltage range at SLx Max. voltage difference BHx – SHx Max. voltage difference Gxx – Sxx Power dissipation (DC) @ TA=125°C / min.footprint Power dissipation (DC) @ TA=85°C / min.footprint Electrostatic discharge voltage (Human Body Model) according to MIL STD 883D, method 3015.7 and EOS/ESD assn. standard S5.1 – 1993 Thermal resistance junction - ambient (minimal footprint with thermal vias) Thermal resistance junction - ambient (6 cm2) VS Tj Tstg VINH VBHx VDHx VGHx VSHx VGLx VSLx VBHx-VSHx VGxx-VSxx Ptot Ptot VESD4 Limits Values min max -4 60 -40 150 -55 150 -1 6 -0.3 6 -0.6 60 -0.3 90 -4 75 -6.8 86 -6.8 75 -2 12 -2 7 -0.3 17 -0.3 11 -0.33 -0.85 -2 Unit V °C V V V V V V V V V V V W W kV RthJA -- 75 K/W RthJA -- 75 K/W Functional range Parameter and Conditions Symbol at Tj = -40…+150°C, unless otherwise specified Supply voltage Operating temperature range Max. voltage range at PWM, DIR, DT/DIS Max. voltage range at ERx Max. voltage range at INH Max. voltage range at BHx Max. voltage range at DHx2 Max. voltage range at GHx3 Max. voltage range at SHx3 VS Tj VINH VBHx VDHx VGHx VSHx Values min max 7.5 60 -40 150 -0.3 5.5 -0.3 5.5 -0.6 60 -0.3 90 -4 75 -7 86 -7 75 Unit V °C V V V V V V V 1 With external resistor (≥10 Ω ) and capacitor The min value -4V is reduced to –( VBHx - VSHx) in case of bootstrap voltages VBHx-VSHx <4V 3 The min value -7V is reduced to –(VBHx - VSHx - 1V) in case of bootstrap voltages VBHx-VSHx <8V 4 All test involving Gxx pins VESD=1 kV! 2 Data Sheet 4 Rev 2.3 2007-01-11 Data Sheet TLE 6281G Max. voltage range at GLx Max. voltage range at SLx Max. voltage difference BHx – SHx Max. voltage difference Gxx – Sxx PWM frequency Minimum on time external lowside switch – static condition @ 20 kHz; QGate = 200nC VGHx VSLx VBHx-VSHx VGxx-VSxx FPWM tp(min) -2 -2 -0.3 -0.3 0 -- 12 6 12 11 50 2 V V V V kHz µs Electrical Characteristics Parameter and Conditions Symbol at Tj = -40…150°C, unless otherwise specified and supply voltage range VS = 7.5 … 60V; fPWM = 20kHz Static Characteristics Low level output voltage (VGSxx) @ I=10mA High level output voltage (VGSxx) @ I=-10mA; Vs≥11.5V High level output voltage (VGSxx) @ I=-10mA; Vs<11.5V Supply current at VS (device disabled) @ Vbat= VS =14V RDT=400kΩ Supply current at VS (device disabled) @ Vbat= VS =42V RDT=400kΩ Quiescent current at VS (device inhibited) @ Vbat= VS =14V RDT=400kΩ RBx=12kΩ Quiescent current at VS (device inhibited) @ Vbat= VS =42V RDT=400kΩ RBx=12kΩ Supply current at VS @ Vbat= VS =14V, fPWM = 20kHz (Outputs open) Supply current at VS @ Vbat= VS =14V, fPWM = 50kHz (Outputs open) Supply current at VS @ Vbat= VS =42V, fPWM = 20kHz (Outputs open) Low level input voltage High level input voltage Input hysteresis Inhibit trip level Data Sheet 5 min Values typ Unit max ∆VLL ∆VHL -8 60 10 150 11 mV V ∆VHL -- Vs-1.5 -- V IVS(dis)14V -- 4 8 mA IVS(dis)42V -- 4 8 mA IVS(inh)14V -- 0.6 1.5 mA IVS(inh)42V -- 0.6 1.5 mA IVS(open)14V -- 7 15 mA IVS(open)14V -- 7 15 mA IVS(open)42V -- 7 15 mA -2.0 100 1.3 --170 2 1.0 -- V V mV V VIN(LL) VIN(HL) ∆VIN VINH 3 Rev 2.3 2007-01-11 Data Sheet TLE 6281G Dynamic characteristics (pls. see test circuit and timing diagram) Turn on current @ VGxx –VSxx = 0V; Tj=25°C @ VGxx –VSxx = 4V; Tj=125°C @ CLoad=22nF ; Rload= 0Ω Turn off current @ VGxx –VSxx = 10V; Tj=25°C @ VGxx –VSxx = 4V; Tj=125°C @ CLoad= 22nF ; Rload=0Ω Dead time (adjustable) @ RDT = 1 kΩ @ RDT = 10 kΩ @ RDT = 50 kΩ @ RDT = 200 kΩ @ CLoad=10nF ; Rload=1Ω Rise time @ CLoad=10nF; Rload=1Ω (20% to 80%) Fall time @ CLoad=10nF; Rload=1Ω (80% to 20%) Disable propagation time @ CLoad=10nF ; Rload=1Ω Reset time of diagnosis @ CLoad=10nF ; Rload=1Ω Input propagation time (low side turns on, 0% to 10%) Input propagation time (low side turns off, 100% to 90%) Input propagation time (high side turns on, 0% to 10%) Input propagation time (high side turns off, 100% to 90%) Input propagation time difference (all channels turn on) Input propagation time difference (all channels turn off) Input propagation time difference (one channel; low on – high off) Input propagation time difference (one channel; high on – low off) Input propagation time difference (all channels; low on – high off) Input propagation time difference (all channels; high on – low off) Data Sheet 6 IGxx(on) --- 850 700 --- mA IGxx(off) --- 580 300 --- mA -0.05 0.40 -- 0.01 0.20 1.0 3.1 -0.38 2.50 -- µs -- 100 300 ns tfall tP(DIS) -3.4 150 5 440 7 ns µs tP(CL) 1 2 3.1 µs tP(ILN) -- 250 500 ns tP(ILF) -- 110 500 ns tP(IHN) -- 200 500 ns tP(IHF) -- 130 500 ns tP(Diff) 20 50 70 ns tP(Diff) -- 25 50 ns tP(Diff) -- 120 180 ns tP(Diff) -- 100 180 ns tP(Diff) -- 120 180 ns tP(Diff) -- 100 180 ns tDT t rise Rev 2.3 2007-01-11 Data Sheet TLE 6281G Test Circuit and Timing Diagram x2 PWM GHx PWM Rload = 1 Ohm Cload = 10 nF 50% VGHX_C SHx tP(IHN) trise GLx t tP(IHF) tfall VGHX_C Rload = 1 Ohm 90% Cload = 10 nF 80% VGLX_C SLx 20% 10% t tP(ILF) Test Conditions : tfall tP(ILN) trise VGLX_C 90% 80% Junction temperature Tj = -40 … 150oC Supply voltage range Vs = 7.5 … 60V 20% 10% PWM frequency fPWM = 20 kHz t Diagnosis and Protection Functions Parameter and Conditions Symbol at Tj = -40…150°C, unless otherwise specified and supply voltage range VS = 7.5 … 60V; fPWM = 20kHz Overtemperature warning Hysteresis for overtemperature warning Short circuit protection filter time Short circuit criteria (VDS of Mosfets) For Low sides For High sides Disable input level Disable input hysteresis Error level @ 1.6mA IERR Under voltage lock out for highside output – bootstrap voltage Under voltage lock out for lowside output – supply voltage Data Sheet min TJ(OV) ∆TJ(OV) tSCP(off) VDS(SCP) VDIS ∆VDIS VERR VBHx (uvlo) VVs (uvlo) 7 Values typ Unit max 150 -6 170 20 9 190 -12 °C °C µs 0.5 0.45 3.3 ---- 0.75 0.75 3.7 180 -3.7 1.0 1.05 4.0 -1.0 4.6 V V mV V V -- 4.8 5.9 V Rev 2.3 2007-01-11 Data Sheet TLE 6281G Remarks: Default status of input pins: To assure a defined status of the logic input pins in case of disconnection, these pins are internally secured by pull up / pull down current sources with approx. 20µA. The high voltage proof input INH should be secured by an external pull down resistor close to the device. The following table shows the default status of the logic input pins. Input pin PWM and DIR DT/DIS (active high) Default status Low (= break in high side) High Definition: In this datasheet a duty cycle of 98% means that the GLx pin is 2% of the PWM period in high condition. Remark: Please consider the influence of the dead time and the propagation time differences for the input duty cycle Functional description Description of Dead Time Pin / Disable Pin / Reset This pin allows to adjust the internal generated dead time. The dead time protects the external high side and lowside Mosfets in the same halfbridge against a lowohmic connection between battery and GND and the resulting cross current through these Mosfets. The adjustable dead time allows to minimize the power dissipation caused by the current flowing through the body diode during switching the halfbridge. In addition this pin allows to reset the diagnosis registers without shut down of any output stage as well as the possibility to shut down all outputs simultaneously. Condition of DT/DIS pin 0 - 3.5V > 4V Function Adjust dead time between 10ns and 3.1µs a) Reset of diagnosis register if DT/DIS voltage is higher than 4V for a time between 3.1µs and 3.6µs b) Shut down of output stages if DT/DIS voltage is higher than 4V for a time above 7µs (Active pull down of gate voltage) Description of Inhibit functionality In automotive applications which are permanently connected to the battery line, it is very important to reduce the current consumption of the single devices. Therefore the TLE6281G offers an inhibit mode to put the device to sleep and assure low quiescent currents. To deactivate the inhibit mode the INH pin has to be set to high. This can be done by connecting this pin to voltages between 3.3 and 60V without external protection. An inhibit mode means a complete reinitialisation of the device. Description of Diagnosis The two ERx pins are open collector outputs and have to be pulled up with external pull up resistors to 5V. In normal conditions both ERx signals are high. In case of shutdown of any Data Sheet 8 Rev 2.3 2007-01-11 Data Sheet TLE 6281G output stage the ER1 is pulled down. This shut down can be caused by undervoltage or short circuit. In this condition ER2 indicates the reason for the shut down. Condition of ER1 pin 5V 5V 0V Condition of ER2 pin 5V 0V 5V Function no errors overtemperature warning of driver IC Shut down of any output stage caused by short circuit 0V 0V Shut down of any output stage caused by undervoltage Recommended Start-up procedure The following procedure is recommended whenever the Driver IC is powered up: • • • • Disable the Driver IC via DT/DIS pin Wait until the bootstrap capacitors CBx are charged (the waiting time depends on application conditions, e.g. CBx and RBx) Enable the Driver IC via DT/DIS pin Start the operation by applying the desired pulse patterns. Do not apply any pulse patterns to the PWM or DIR pin, before the CBx capacitors are charged up. Shut down of the driver A shut down can be caused by undervoltage or short circuit. A short circuit will shut down only the affected Mosfet until a reset of the error register by a disable of the driver occurs. A shut down due to short circuit will occur only when the Short Circuit criteria VDS(SCP) is met for a duration equal to or longer than the Short Circuit filter time tSCP(off). Yet, the exposure to or above VDS(SCP) is not counted or accumulated. Hence, repetitive Short Circuit conditions shorter than tscp(off) will not result in a shut down of the affected MOSFET. An undervoltage shut down shuts only the affected output down. The affected output will auto restart after the undervoltage situation is over. Operation at Vs<12V If Vs<11.5V the gate voltage will not reach 10V. It will reach approx Vs-1.5V, dependent on duty cyle, bootstrap capacitor, total gate charge of the external Mosfet and switching frequency. Operation at different voltages for Vs, DH1 and DH2 If DH1 and DH2 are used with a voltage higher than Vs, a duty cycle of 100% can not be guaranteed. In this case the driver is acting like a normal driver IC based on the bootstrap principle. This means that after a maximum “On” time of the highside switch of more than 1ms a refresh pulse to charge the bootstrap capacitor of about 1µs is needed to avoid undervoltage lock out of this output stage. Operation at extreme duty cycle: The integrated charge pump allows an operation at 100% duty cycle. The charge pump is strong enough to replace leakage currents during “on”-phase of the highside switch. The gate charge for fast switching of the highside switches is supplied by the bootstrap capaciData Sheet 9 Rev 2.3 2007-01-11 Data Sheet TLE 6281G tors. This means, that the bootstrap capacitor needs a minimum charging time of about 1µs, if the highside switch is operated in PWM mode (e.g. with 20kHz a maximum duty cycle of 96% can be reached). The exact value for the upper limit is given by the RC time formed by the impedance of the internal bootstrap diode and the capacitor formed by the external Mosfet (CMosfet=QGate / VGS). The size of the bootstrap capacitor has to be adapted to the external MOSFET the driver IC has to drive. Usually the bootstrap capacitor is about 10-20 times bigger than CMosfet. External components at the Vs Pin have to be considered, too. The charge pump is active when the highside switch is “ON” and the voltage level at the SHx is higher than 4V. Only under these conditions the bootstrap capacitor is charged by the charge pump. Estimation of power loss within the Driver IC The power loss within the Driver IC is strongly dependent on the use of the driver and the external components. Nevertheless a rough estimation of the worst case power loss is possible. Worst case calculation is: PLoss = (Qgate*n*const* fPWM + IVS(open))* VVs - PRGate With: PLoss = Power loss within the Driver IC fPWM = Switching freqency Qgate = Total gate charge of used MOSFETs at 10V VGS n = Number of switched MOSFETs const = Constant considering some leakage current in the driver (about 1.2) IVS(open) = Current consumption of driver without connected Mosfets during switching VVS = Voltage at Vs PRGate = Power dissipation in the external gate resistors This value can be reduced dramatically by usage of external gate resistors. Estimated Power Loss PLOSS within the Driver IC Estimated Power Loss PLOSS within the Driver IC for different gate charges QG for different supply voltages Vs at supply voltage Vs = 14V at QG = 100nC @ VGS = 10V 0,8 0,8 0,7 0,6 Vs = 8V 0,5 Vs = 14V 0,4 Vs = 18V QG = 50nC 0,6 PLOSS (W) PLOSS (W) 0,7 0,3 QG = 100nC 0,5 QG = 200nC 0,4 0,3 0,2 0,2 0,1 0,1 0 0 0 10 20 30 40 50 60 0 PWM Frequency (kHz) 10 20 30 40 50 60 PWM Frequency (kHz) Conditions : Junction temperature Tj = 25oC Number of switched MOSFET n = 2 Power dissipation in the external gate resistors PRGate = 0,2*PLoss Data Sheet 10 Rev 2.3 2007-01-11 Data Sheet TLE 6281G Gate Drive characteristics VPWM_HS BHx VPWM_HS Logic + Level Shift + VGS limit + Under voltage Vs SCD iGxx(on) iGxx(on) DHx 850 mA Peak CB GHx iGxx(off) iGHx SHx iGxx(off) 580 mA Peak Motor TLE6281G High Side Driver iGHx Test Conditions : - Turn On : VGS = 0V, Tj = 25oC - Turn Off : VGS = 10V, Tj = 25oC This figure represents the simplified internal circuit of one high side gate drive. The drive circuit for the low sides looks similar. Data Sheet 11 This figure illustrates typical voltage and current waveforms of the high side gate drive; the associated waveforms of the low side drives look similar. Rev 2.3 2007-01-11 Data Sheet TLE 6281G Truth Table Input Conditions DIR PWM DT / DIS UV OT SC 0 Output driver IC Output Bridge Out1 Out2 <3.5V 0 0 0 0 1 0 <3.5V 0 0 0 1 1 <3.5V 0 0 0 GH GL GH GL ER ER 1 1 2 2 1 2 1 0 0 1 5V 5V 1 0 1 0 5V 5V 0 1 1 0 5V 5V 1 0 <3.5V 0 0 0 1 0 1 0 5V 5V 1 0 <3.5V 1 0 0 B 0 0 B C D 1 A 0A 0 1 0 <3.5V 1 0 0 B 0 B 0 C D 1 A 1A 1 1 <3.5V 1 0 0 0 B B 0 C D 0A 1A 1 0 <3.5V 1 0 0 B 0 B 0 C D 1 A 1A 0 <3.5V 0 1 0 1 0 0 1 5V 0V 1 0 0 1 0 <3.5V 0 1 0 1 0 1 0 5V 0V 1 1 1 1 <3.5V 0 1 0 0 1 1 0 5V 0V 0 1 1 0 <3.5V 0 1 0 1 0 1 0 5V 0V 1 1 0 <3.5V 0 0 1 E 0 0 E F 5V 1A 0A 0 1 0 <3.5V 0 0 1 E 0 E 0 F 5V 1A 1A 1 1 <3.5V 0 0 1 0 E E 0 F 5V 0A 1A 1 0 <3.5V 0 0 1 E 0 E 0 F 5V 1A 1A X X X X X X X 0 0 0 0 5V 5V T T >4V X X X 0 0 0 0 5V 5V T T X 1 0 1 1 0 1 1 A) Tristate when affected by undervoltage shut down or short circuit B) 0 when affected; 1 when not affected; self recovery C) 0V when output does not correspond to input patterns; 5V when output corresponds to input patterns D) Is an output affected by undervoltage ER2 is 0V E) 0 when affected– the outputs of the affected halfbridge are shut down and stay latched until reset; 1 when not affected F) 0V when output does not correspond to input patterns – the outputs of the affected halfbridge are shut down and stay latched until reset; 5V when output corresponds to input patterns. T) Tristate X) Condition has no influence Remark: To generate fast decay control mode, set PWM to 1 and send pwm-pattern to DIR input. Data Sheet 12 Rev 2.3 2007-01-11 Data Sheet 13 Imotor VGL2 VGL1 VGH2 VGH1 DIR PWM M Vs Acceleration M Vs M Vs Motor turns right M Vs Motor stops Driving Sequence and current flow in the MOSFETs and the motor M Vs Motor turns left M Vs Motor stops t t t t t t t Data Sheet TLE 6281G Rev 2.3 2007-01-11 Data Sheet TLE 6281G Package and Ordering Code (all dimensions in mm)5 Package P-DSO 20 5 More information about packages can be found at our internet page http://www.infineon.com/packages Data Sheet 14 Rev 2.3 2007-01-11 Data Sheet TLE 6281G Published by Infineon Technologies AG, Bereich Kommunikation St.-Martin-Strasse 53, D-81541 München © Infineon Technologies AG 1999 All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Data Sheet 15 Rev 2.3 2007-01-11