TI TPS61170DRVT

TPS61170
www.ti.com
SLVS789A – NOVEMBER 2007 – REVISED FEBRUARY 2008
1.2A High Voltage Boost Converter in 2x2mm2 QFN Package
FEATURES
1
•
•
•
•
•
•
•
•
•
•
DESCRIPTION
3-V to 18-V Input Voltage Range
High Output Voltage: Up to 38 V
1.2-A integrated Switch
1.2-MHz Fixed Switching Frequency
12 V at 300 mA and 24 V at 150 mA from 5-V
Input (Typical)
Up to 93% Efficiency
On-The-Fly Output Voltage Reprogramming
Skip-Switching Cycle for Output Regulation at
Light Load
Built-in Soft Start
6-Pin, 2 mm × 2 mm QFN Package
The TPS61170 is a monolithic high voltage switching
regulator with integrated 1.2-A, 40-V power MOSFET.
It can be configured in several standard
switching-regulator topologies, including boost and
SEPIC. The device has a wide input-voltage range to
support applications with input voltage from multi-cell
batteries or regulated 5-V, 12-V power rails.
The TPS61170 uses a 1.2-MHz switching frequency,
allowing the use low-profile inductors and low-value
ceramic input and output capacitors. The external
loop compensation gives the user flexibility to
optimize loop compensation and transient response.
The device has built-in protection features, such as
pulse-by-pulse overcurrent limit, soft start and thermal
shutdown.
APPLICATIONS
•
•
•
5-V to 12-V and 24-V, 12-V to 24-V Boost
Converter
Buck Boost Regulation Using SEPIC Topology
ADSL Modems
The feedback reference voltage of the FB pin is
1.229V. It can be lowered using a 1-wire digital
interface (Easyscale™ protocol) through the CTRL
pin. Alternatively, a pulse width-modulation (PWM)
signal can be applied to the CTRL pin. The duty cycle
of the signal reduces the feedback reference voltage
proportionally.
The TPS61170 is available in a 6-pin 2 mm × 2 mm
QFN package, allowing a compact power-supply
solution.
L1
10 mH
VIN 5 V
C1
4.7 mF
C2
4.7 mF
TPS 61170
VIN
R3
10 kW
VOUT 12 V/ 300 mA
D1
SW
CTRL
FB
COMP
GND
C3
680 pF
R1
87.6 kW
R2
10 kW
L1: TOKO#A915_Y-100M
C1: Murata GRM188R61A475K
C2: Murata GRM21BR61E475K
D1: ONsemi MBR0540T1
*R3, C3: Compensation RC network
Figure 1. Typical Application
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2008, Texas Instruments Incorporated
TPS61170
www.ti.com
SLVS789A – NOVEMBER 2007 – REVISED FEBRUARY 2008
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
(1)
(2)
TA
PACKAGE (2)
PACKAGE MARKING
–40°C to 85°C
TPS61170DRV
BZS
For the most current package and ordering information, see the TI Web site at www.ti.com.
The DRV package is available in tape and reel. Add R suffix (TPS61170DRVR) to order quantities of 3000 parts per reel or add T suffix
(TPS61170DRVT) to order 250 parts per reel.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
Supply Voltages on VIN
VI
(1)
(2)
VALUE
UNIT
–0.3 to 20
V
Voltages on CTRL (2)
–0.3 to 20
V
Voltage on FB and COMP (2)
–0.3 to 3
V
–0.3 to 40
V
Voltage on SW
(2)
PD
Continuous Power Dissipation
TJ
Operating Junction Temperature Range
–40 to 150
°C
TSTG
Storage Temperature Range
–65 to 150
°C
(1)
(2)
See Dissipation Rating Table
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
DISSIPATION RATINGS
DERATING FACTOR
ABOVE TA = 25°C
BOARD PACKAGE
RθJC
RθJA
Low-K (1)DRV
20°C/W
140°C/W
20°C/W
65°C/W
High-K
(1)
(2)
(2)
DRV
TA < 25°C
TA = 70°C
TA = 85°C
7.1 mW/°C
715 mW
395 mW
285 mW
15.4 mW/°C
1540 mW
845 mW
615 mW
The JEDEC low-K (1s) board used to derive this data was a 3in×3in, two-layer board with 2-ounce copper traces on top of the board.
The JEDEC high-K (2s2p) board used to derive this data was a 3in×3in, multilayer board with 1-ounce internal power and ground planes
and 2-ounce copper traces on top and bottom of the board.
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
UNIT
VI
Input voltage range, VIN
VO
Output voltage range
L
Inductor (1)
CI
Input capacitor
CO
Output capacitor
1
10
µF
TA
Operating ambient temperature
–40
85
°C
TJ
Operating junction temperature
–40
125
°C
(1)
2
3
18
VIN
38
V
V
10
22
µH
µF
1
These values are recommended values that have been successfully tested in several applications. Other values may be acceptable in
other applications but should be fully tested by the user.
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS61170
TPS61170
www.ti.com
SLVS789A – NOVEMBER 2007 – REVISED FEBRUARY 2008
ELECTRICAL CHARACTERISTICS
VIN = 3.6 V, CTRL = VIN, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
VI
Input voltage range, VIN
3.0
IQ
Operating quiescent current into VIN
Device PWM switching no load
ISD
Shutdown current
CRTL=GND, VIN = 4.2 V
UVLO
Under-voltage lockout threshold
VIN falling
Vhys
Under-voltage lockout Hysteresis
2.2
18
V
2.3
mA
1
µA
2.5
V
70
mV
ENABLE AND REFERENCE CONTROL
V(CTRLh)
CTRL logic high voltage
VIN = 3 V to 18 V
1.2
V
V(CTRL)
CTRL logic low voltage
VIN = 3 V to 18 V
R(CTRL)
CTRL pull down resistor
toff
CTRL pulse width to shutdown
CTRL high to low
2.5
ms
tes_det
Easy Scale detection time (1)
CTRL pin low
260
µs
tes_delay
Easy Scale detection delay
tes_win
Easy Scale detection window time
0.4
400
800
1600
V
kΩ
100
µs
1
ms
VOLTAGE AND CURRENT CONTROL
VREF
Voltage feedback regulation voltage
V(REF_PWM)
Voltage feedback regulation voltage under
reprogram
VFB = 492 mV
IFB
Voltage feedback input bias current
VFB = 1.229 V
fS
Oscillator frequency
Dmax
Maximum duty cycle
tmin_on
Minimum on pulse width
Isink
Isource
Gea
Error amplifier transconductance
Rea
Error amplifier output resistance
5 pF connected to COMP
6
MΩ
fea
Error amplifier crossover frequency
5 pF connected to COMP
500
kHz
VIN = 3.6 V
0.3
VFB = 100 mV
1.204
1.229
1.254
477
492
507
mV
200
nA
1.5
MHz
1.0
1.2
90%
93%
V
40
ns
Comp pin sink current
100
µA
Comp pin source current
100
240
320
µA
400
µmho
POWER SWITCH
RDS(on)
N-channel MOSFET on-resistance
ILN_NFET
N-channel leakage current
VSW = 35 V, TA = 25°C
ILIM
N-Channel MOSFET current limit
D = Dmax
ILIM_Start
Start up current limit
D = Dmax
tHalf_LIM
Time step for half current limit
tREF
tstep
VIN = 3.0 V
0.6
0.7
Ω
1
µA
1.44
A
OC and SS
(1)
0.96
1.2
0.7
A
5
ms
Vref filter time constant
180
µs
VREF ramp up time
213
µs
EasyScale communication is allowed immediately after the CTRL pin has been low for more than tes_det. To select EasyScale™ mode,
the CTRL pin must be low for more than tes_det the end of tes_win.
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS61170
3
TPS61170
www.ti.com
SLVS789A – NOVEMBER 2007 – REVISED FEBRUARY 2008
ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.6 V, CTRL = VIN, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
EasyScale TIMING
µs
tstart
Start time of program stream
2
tEOS
End time of program stream
2
360
µs
tH_LB
High time low bit
Logic 0
2
180
µs
tL_LB
Low time low bit
Logic 0
2 × tH_LB
360
µs
tH_HB
High time high bit
Logic 1
2 × tL_HB
360
µs
tL_HB
Low time high bit
Logic 1
2
180
µs
VACKNL
Acknowledge output voltage low
Open drain, Rpullup =15 kΩ to Vin
tvalACKN
Acknowledge valid time
See
tACKN
Duration of acknowledge condition
See
0.4
V
(2)
2
µs
(2)
512
µs
THERMAL SHUTDOWN
Tshutdown
Thermal shutdown threshold
Thysteresis
Thermal shutdown threshold hysteresis
(2)
160
°C
15
°C
Acknowledge condition active 0, this condition will only be applied if the RFA bit is set. Open drain output, line needs to be pulled high
by the host with resistor load.
PIN ASSIGNMENTS
TOP VIEW
FB
COMP
GND
VIN
Thermal
Pad
CTRL
SW
6-PIN 2mm x 2mm x 0.8mm QFN
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
VIN
6
I
The input supply pin for the IC. Connect VIN to a supply voltage between 3 V and 18 V.
SW
4
I
This is the switching node of the IC. Connect SW to the switched side of the inductor.
GND
3
O
Ground
FB
1
I
Feedback pin for current. Connect to the center tap of a resistor divider to program the output voltage.
COMP
2
O
Output of the transconductance error amplifier. Connect an external RC network to this pin to compensate
the regulator.
CTRL
5
I
Control pin of the boost regulator. CTRL is a multi-functional pin which can be used for enable the device
and control the feedback voltage with a PWM signal and digital communications.
Thermal Pad
4
The thermal pad should be soldered to the analog ground plane to avoid thermal issue. If possible, use
thermal via to connect to ground plane for ideal power dissipation.
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS61170
TPS61170
www.ti.com
SLVS789A – NOVEMBER 2007 – REVISED FEBRUARY 2008
FUNCTIONAL BLOCK DIAGRAM
C2
D1
R1
1
R2
4
L1
FB
SW
Band Gap
Error
Amplifer
Vin
6
COMP
2
C1
PWM Control
R3
5
CTRL
C3
Soft
Start-up
Ramp
Generator
+
Current
Sensor
Oscillator
GND
3
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
Circuit of Figure 1, L = TOKO A915_Y-100M, D1 = ONsemi MBR0540T1, unless otherwise noted.
FIGURE
Efficiency
VIN = 5V; VOUT = 12V,18V,24V,30V;
Figure 2
Efficiency
VIN = 5V, 8.5V, 12V; VOUT = 24V;
Figure 3
Output voltage accuracy
ILOAD= 100 mA
Figure 4
Switch current limit
TA = 25°C
Figure 5
Switch current limit
Figure 6
Error amplifier transconductance
Figure 7
Easyscale step
Figure 8
PWM switching operation
VIN = 5V; VOUT = 12V; ILOAD= 250mA;
Figure 9
Load transient response
VIN = 5V; VOUT = 12V; ILOAD= 50mA to 150mA;
Figure 10
Start-up
VIN = 5V; VOUT = 12V; ILOAD= 250mA;
Figure 11
Skip-cycle switching
VIN = 9V ; VOUT = 12V, ILOAD= 100µA ;
Figure 12
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS61170
5
TPS61170
www.ti.com
SLVS789A – NOVEMBER 2007 – REVISED FEBRUARY 2008
EFFICIENCY
vs
OUTPUT CURRENT
EFFICIENCY
vs
OUTPUT CURRENT
100
100
VIN = 5 V
VIN = 12 V
VOUT = 24 V
VOUT = 12 V
90
90
VOUT = 30 V
VOUT = 18 V
VOUT = 24 V
VIN = 5 V
80
Efficiency - %
Efficiency - %
80
70
70
60
60
50
50
40
40
0
50
100
150
200
Output Current - mA
250
0
300
50
100
150
200
Output Current - mA
250
Figure 2.
Figure 3.
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
SWITCH CURRENT LIMIT
vs
DUTY CYCLE
300
1600
11.96
ILOAD = 100 mA
1500
1400
Switch Current Limit - A
11.94
VO - Output Voltage - V
VIN = 8.5 V
TA = 25°C
TA = 85°C
11.92
TA = -40°C
11.90
1300
1200
1100
1000
900
800
20
11.88
4
5
6
7
8
VI - Input Voltage - V
9
10
11
Switch Current Limit - mA
1300
1200
1100
1000
900
80
20
40
60
80
Temperature - °C
100
120
140
90
500
400
300
200
100
0
-40
-20
Figure 6.
6
70
ERROR AMPLIFIER TRANSCONDUCTANCE
vs
TEMPERATURE
1400
0
50
60
Duty Cycle - %
SWITCH CURRENT LIMIT
vs
TEMPERATURE
1500
-20
40
Figure 5.
1600
800
-40
30
Figure 4.
Error Amplifier Transconductance - mhos
3
0
20
40
60
80
Temperature - °C
100
120
140
Figure 7.
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS61170
TPS61170
www.ti.com
SLVS789A – NOVEMBER 2007 – REVISED FEBRUARY 2008
FB VOLTAGE
vs
EASY SCALE STEP
PWM SWITCHING OPERATION
1.4
SW 5 V/div
1.2
FB Voltage - V
1
0.8
VOUT 100 mV/div AC
0.6
0.4
IL 500 mA/div
0.2
0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Easy Scale Step
t - 400 ns/div
Figure 8.
Figure 9.
LOAD TRANSIENT RESPONSE
START-UP
CTRL 5 V/div
VOUT 200 mV/div AC
VOUT 5 V/div
COMP 500 mV/div
IL 500 mA/div
ILOAD 100 mA/div
t - 1 ms/div
t - 40 ms/div
Figure 10.
Figure 11.
SKIP-CYCLE SWITCHING
SW 5 V/div
VOUT 20 mV/div AC
IL 50 mA/div
t - 400 ns/div
Figure 12.
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS61170
7
TPS61170
SLVS789A – NOVEMBER 2007 – REVISED FEBRUARY 2008
www.ti.com
DETAILED DESCRIPTION
OPERATION
The TPS61170 integrates a 40-V low side FET for up to 38-V output voltages. The device regulates the output
with current mode PWM (pulse width modulation) control. The switching frequency of PWM is fixed at 1.2MHz.
The PWM control circuitry turns on the switch at the beginning of each switching cycle. The input voltage is
applied across the inductor and stores the energy as inductor current ramps up. During this portion of the
switching cycle, the load current is provided by the output capacitor. When the inductor current rises to the
threshold set by the error amplifier output, the power switch turns off and the external Schottky diode is forward
biased. The inductor transfers stored energy to replenish the output capacitor and supply the load current. This
operation repeats in every switching cycle. As shown in the block diagram, the duty cycle of the converter is
determined by the PWM control comparator which compares the error amplifier output and the current signal.
A ramp signal from oscillator is added to the current ramp. This slope compensation is to avoid sub-harmonic
oscillation that is intrinsic to the current mode control at duty cycle higher than 50%. The feedback loop regulates
the FB pin to a reference voltage through an error amplifier. The output of the error amplifier is connected to the
COMP pin. An external RC compensation network is connected to the COMP pin to optimize the feedback loop
for stability and transient response.
SOFT START-UP
Soft-start circuitry is integrated into the IC to avoid a high inrush current during start-up. After the device is
enabled by a logic high signal on the CTRL pin, the FB pin reference voltage ramps up in 32 steps, each step
takes 213µs. This ensures that the output voltage rises slowly to reduce inrush current. Additionally, for the first
5msec after the COMP voltage ramps, the current limit of the PWM switch is set to half of the normal current limit
spec. Therefore, during this period the input current is kept below 700mA (typical). See the start-up waveform for
a typical example, Figure 11.
OVERCURRENT PROTECTION
TPS61170 has a cycle-by-cycle overcurrent limit feature that turns off the power switch once the inductor current
reaches the overcurrent limit. The PWM circuitry resets itself at the beginning of the next switch cycle. During an
over-current event, this results in a decrease of output voltage with respect to load. The current limit threshold as
well as input voltage, output voltage, switching frequency and inductor value determine the maximum available
output current. Larger inductor values increases the current output capability because of the reduced current
ripple. See the APPLICATION INFORMATION section for the output current calculation.
UNDERVOLTAGE LOCKOUT (UVLO)
An undervoltage lockout prevents mis-operation of the device at input voltages below typical 2.2V. When the
input voltage is below the undervoltage threshold, the device remains off and the internal switch FET is turned
off. The undervoltage lockout threshold is set below minimum operating voltage of 3V to avoid any transient VIN
dip triggering the UVLO and causing the device to reset. For the input voltages between UVLO threshold and 3V,
the device maintains its operation, but the specifications are not ensured.
THERMAL SHUTDOWN
An internal thermal shutdown turns off the device when the typical junction temperature of 160°C is exceeded.
The IC restarts when the junction temperature drops by 15°C.
ENABLE AND SHUTDOWN
The TPS61170 enters shutdown when the CTRL voltage is less than 0.4V for more than 2.5ms. In shutdown, the
input supply current for the device is less than 1µA (max). The CTRL pin has an internal 800kΩ pull down
resistor to disable the device when the pin is left unconnected.
8
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS61170
TPS61170
www.ti.com
SLVS789A – NOVEMBER 2007 – REVISED FEBRUARY 2008
FEEDBACK REFERENCE PROGRAM MODE SELECTION
The CTRL pin is used for changing the FB pin reference voltage on-the-fly. There are two methods to program
the reference voltage, PWM signal and 1 wire interface (EasyScale™). The program mode is selected each time
the device is enabled. The default mode is the PWM signal which uses the duty cycle of the CTRL pin signal to
modulate the reference voltage. To enter the 1 wire interface mode, the following digital pattern on the CTRL pin
must be recognized by the IC every time the IC starts from the shutdown mode.
1. Pull CTRL pin high to enable the TPS61170 and to start the 1 wire mode detection window.
2. After the EasyScale detection delay (tes_delay, 100µsec) expires, drive CTRL low for more than the EasyScale
detection time (tes_detect, 260µsec).
3. The CTRL pin has to be low for more than EasyScale detection time before the EasyScale detection window
(tes_win, 1msec) expires. EasyScale detection window starts from the first CTRL pin low to high transition.
The IC immediately enters the 1 wire mode once the above 3 conditions are met. The EasyScale communication
can start before the detection window expires. Once the mode is programmed, it can not be changed without
another start up. This means the IC needs to be shutdown by pulling the CTRL low for 2.5ms and restarts. See
the Mode Detection of Feedback Reference Program figure (Figure 13) for a graphical explanation.
Insert battery
PWM signal
high
CTRL
low
PWM
mode
Startup
delay
FB ramp
Shutdown delay
200mV x duty cycle
FB
t
Insert battery
Enter ES mode
Enter ES mode
Timing window
Programming
code
Programming code
high
CTRL
low
ES detect time
ES
mode
ES detect delay
Shutdown
delay
IC
Shutdown
Programmed value
(if not programmed, 200mV default )
FB
FB ramp
FB ramp
Startup delay
50mV
Startup delay
50mV
Figure 13. Mode Detection of Feedback Reference Program
PWM PROGRAM MODE
When the CTRL pin is constantly high, the FB voltage is regulated to 1.229V typically. However, the CTRL pin
allows a PWM signal to reduce this regulation voltage. The relationship between the duty cycle and FB voltage is
given in Equation 1:
V FB + Duty 1.229 V
(1)
Where:
Duty = duty cycle of the PWM signal
1.229 V = internal reference voltage
As shown in Figure 14, the IC chops up the internal 1.229V reference voltage at the duty cycle of the PWM
signal. The pulse signal is then filtered by an internal low pass filter. The output of the filter is connected to the
error amplifier as the reference voltage for the FB pin regulation. The regulation voltage is independent of the
PWM logic voltage level which often has large variations.
For optimum performance, use the PWM mode in the range of 5kHz to 100kHz. The requirement of minimum
frequency comes from the EasyScale detection delay and detection time specification for the mode selection.
The device can mistakenly enter 1 wire mode if the PWM signal frequency is less than 5kHz. Since the CTRL pin
is logic only pin, adding external RC filter to the pin does not work.
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS61170
9
TPS61170
www.ti.com
SLVS789A – NOVEMBER 2007 – REVISED FEBRUARY 2008
VBG
1.229 V
CTRL
FB
Error
Amplifier
Figure 14. Block Diagram of Programmable FB Voltage Using PWM Signal
1 WIRE PROGRAM MODE
The CTRL pin features a simple digital interface to control the feedback reference voltage. The 1 wire mode can
save the processor power and battery life as it does not require a PWM signal all the time, and the processor can
enter idle mode if available.
The TPS61170 adopts the EasyScale™ protocol, which can program the FB voltage to any of the 32 steps with
single command. See the Table 1 for the FB pin voltage steps. The programmed reference voltage is stored in
an internal register. The default value is full scale when the device is first enabled (VFB = 1.229V). A power reset
clears the register value and reset it to default.
EasyScale™
EasyScale is a simple but very flexible one pin interface to configure the FB voltage. The interface is based on a
master-slave structure, where the master is typically a microcontroller or application processor. Figure 15 and
Table 1 give an overview of the protocol. The protocol consists of a device specific address byte and a data byte.
The device specific address byte is fixed to 72 hex. The data byte consists of five bits for information, two
address bits, and the RFA bit. The RFA bit set to high indicates the Request for Acknowledge condition. The
Acknowledge condition is only applied if the protocol was received correctly. The advantage of EasyScale
compared with other on pin interfaces is that its bit detection is in a large extent independent from the bit
transmission rate. It can automatically detect bit rates between 1.7kBit/sec and up to 160kBit/sec.
Table 1. Selectable FB Voltage
10
FB voltage
(mV)
D4
D3
D2
D1
D0
0
0.000
0
0
0
0
0
1
0.031
0
0
0
0
1
2
0.049
0
0
0
1
0
3
0.068
0
0
0
1
1
4
0.086
0
0
1
0
0
5
0.104
0
0
1
0
1
6
0.123
0
0
1
1
0
7
0.141
0
0
1
1
1
8
0.160
0
1
0
0
0
9
0.178
0
1
0
0
1
10
0.197
0
1
0
1
0
11
0.215
0
1
0
1
1
12
0.234
0
1
1
0
0
13
0.270
0
1
1
0
1
14
0.307
0
1
1
1
0
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS61170
TPS61170
www.ti.com
SLVS789A – NOVEMBER 2007 – REVISED FEBRUARY 2008
Table 1. Selectable FB Voltage (continued)
FB voltage
(mV)
D4
D3
D2
D1
D0
15
0.344
0
1
1
1
1
16
0.381
1
0
0
0
0
17
0.418
1
0
0
0
1
18
0.455
1
0
0
1
0
19
0.492
1
0
0
1
1
20
0.528
1
0
1
0
0
21
0.565
1
0
1
0
1
22
0.602
1
0
1
1
0
23
0.639
1
0
1
1
1
24
0.713
1
1
0
0
0
25
0.787
1
1
0
0
1
26
0.860
1
1
0
1
0
27
0.934
1
1
0
1
1
28
1.008
1
1
1
0
0
29
1.082
1
1
1
0
1
30
1.155
1
1
1
1
0
31
1.229
1
1
1
1
1
DATA IN
DATABYTE
Device Address
Start
Start DA7 DA6 DA5 DA4 DA3 DA2 DA1
0
1
1
1
0
0
1
DA0 EOS Start RFA
0
A1
A0
D4
D3
D2
D1
D0
EOS
DATA OUT
ACK
Figure 15. EasyScale™ Protocol Overview
Table 2. EasyScale™ Bit Description
BYTE
Device
Address
Byte
72 hex
Data byte
BIT
NUMBER
NAME
TRANSMISSION
DIRECTION
7
DA7
0 MSB device address
6
DA6
1
5
DA5
1
4
DA4
3
DA3
2
DA2
0
1
DA1
1
IN
DESCRIPTION
1
0
0
DA0
0 LSB device address
7 (MSB)
RFA
Request for acknowledge. If high, acknowledge is applied by device
6
A1
0 Address bit 1
5
A0
0 Address bit 0
4
D4
3
D3
2
D2
Data bit 2
1
D1
Data bit 1
0 (LSB)
D0
Data bit 0
IN
Data bit 4
Data bit 3
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS61170
11
TPS61170
www.ti.com
SLVS789A – NOVEMBER 2007 – REVISED FEBRUARY 2008
Table 2. EasyScale™ Bit Description (continued)
BYTE
BIT
NUMBER
NAME
TRANSMISSION
DIRECTION
DESCRIPTION
ACK
OUT
Acknowledge condition active 0, this condition will only be applied in case RFA bit is
set. Open drain output, Line needs to be pulled high by the host with a pullup
resistor. This feature can only be used if the master has an open drain output stage.
In case of a push pull output stage Acknowledge condition may not be requested!
Easy Scale Timing, without acknowledge RFA = 0
t Start
DATA IN
t Start
Address Byte
DATA Byte
Static High
Static High
DA7
0
DA0
0
D0
1
RFA
0
TEOS
TEOS
Easy Scale Timing, with acknowledge RFA = 1
t Start
DATA IN
t Start
Address Byte
DATA Byte
Static High
Static High
DA7
0
DA0
0
TEOS
RFA
1
D0
1
Controller needs to
Pullup Data Line via a
resistor to detect ACKN
DATA OUT
tLow
Low Bit
(Logic 0)
t High
tLOW
t valACK
ACKN
t ACKN
Acknowledge
true, Data Line
pulled down by
device
Acknowledge
false, no pull
down
tHigh
High Bit
(Logic 1)
Figure 16. EasyScale™— Bit Coding
All bits are transmitted MSB first and LSB last. Figure 16 shows the protocol without acknowledge request (Bit
RFA = 0), Figure 16 with acknowledge (Bit RFA = 1) request. Prior to both bytes, device address byte and data
byte, a start condition must be applied. For this, the CTRL pin must be pulled high for at least tstart (2µs) before
the bit transmission starts with the falling edge. If the CTRL pin is already at high level, no start condition is
needed prior to the device address byte. The transmission of each byte is closed with an End of Stream
condition for at least tEOS (2µs).
12
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS61170
TPS61170
www.ti.com
SLVS789A – NOVEMBER 2007 – REVISED FEBRUARY 2008
The bit detection is based on a Logic Detection scheme, where the criterion is the relation between tLOW and
tHIGH. It can be simplified to:
High Bit: tHIGH > tLOW, but with tHIGH at least 2x tLOW, see Figure 16.
Low Bit: tHIGH < tLOW, but with tLOW at least 2x tHIGH, see Figure 16.
The bit detection starts with a falling edge on the CTRL pin and ends with the next falling edge. Depending on
the relation between tHIGH and tLOW, the logic 0 or 1 is detected.
The acknowledge condition is only applied if:
• Acknowledge is requested by a set RFA bit.
• The transmitted device address matches with the device address of the device.
• 16 bits is received correctly.
If the device turns on the internal ACKN-MOSFET and pulls the CTRL pin low for the time tACKN, which is 512µs
maximum then the Acknowledge condition is valid after an internal delay time tvalACK. This means that the internal
ACKN-MOSFET is turned on after tvalACK, when the last falling edge of the protocol was detected. The master
controller keeps the line low in this period. The master device can detect the acknowledge condition with its input
by releasing the CTRL pin after tvalACK and read back a logic 0. The CTRL pin can be used again after the
acknowledge condition ends.
Note that the acknowledge condition may only be requested if the master device has an open drain output. For
the push-pull output stage, the use a series resistor in the CRTL line to limit the current to 500µA is
recommended for such cases as:
• an accidentally requested acknowledge, or
• to protect the internal ACKN-MOSFET.
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS61170
13
TPS61170
www.ti.com
SLVS789A – NOVEMBER 2007 – REVISED FEBRUARY 2008
APPLICATION INFORMATION
PROGRAM OUTPUT VOLTAGE
VOUT
R1
TPS61170
FB
R2
Figure 17. Program Output Voltage
To program the output voltage, select the values of R1 and R2 (See Figure 17) according to Equation 2.
æ R1
ö
+ 1÷
è R2
ø
Vout = 1.229 V x ç
æ Vout
ö
- 1÷
è 1.229 V
ø
R1 = R2 x ç
(2)
Considering the leakage current through the resistor divider and noise decoupling to FB pin, an optimum value
for R2 is around 10k. The output voltage tolerance depends on the VFB accuracy and the tolerance of R1 and
R2.
MAXIMUM OUTPUT CURRENT
The overcurrent limit in a boost converter limits the maximum input current, and thus the maximum input power
for a given input voltage. The maximum output power is less than the maximum input power due to power
conversion losses. Therefore, the current-limit setting, input voltage, output voltage and efficiency can all affect
the maximum output current. The current limit clamps the peak inductor current; therefore, the ripple must be
subtracted to derive the maximum DC current. The ripple current is a function of the switching frequency,
inductor value and duty cycle. The following equations take into account of all the above factors for maximum
output current calculation.
1
IP =
é
1
1 ù
+
)ú
êL ´ Fs ´ (
V
+
V
V
V
out
f
in
in û
ë
(3)
where:
IP = inductor peak to peak ripple
L = inductor value
Vf = Schottky diode forward voltage
Fs = switching frequency
Vout = output voltage
I
Vin ´ (Ilim - P ) ´ h
2
Iout _ max =
Vout
(4)
where:
Iout_max = Maximum output current of the boost converter
Ilim = overcurrent limit
η = efficiency
For instance, when Vin is 5 V, Vout is 12 V, the inductor is 10 µH, the Schottky forward voltage is 0.2 V; and then
the maximum output current is 300 mA in typical operation.
14
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS61170
TPS61170
www.ti.com
SLVS789A – NOVEMBER 2007 – REVISED FEBRUARY 2008
SWITCH DUTY CYCLE
The maximum switch duty cycle (D) of the TPS61170 is 90% (min). The duty cycle of a boost converter under
continuous conduction mode (CCM) is given by:
D + Vout * Vin
Vout
(5)
For a 5V to 12V application, the duty cycle is 58.3%, and for a 5V to 24V application, the duty cycle is 79.2%.
The duty cycle must be lower than the maximum specification of 90% in the application; otherwise, the output
voltage can not be regulated.
Once the PWM switch is turned on, the TPS61170 has minimum ON pulse width. This sets the limit of the
minimum duty cycle. For operating low duty cycle, the TPS61170 enters pulse-skipping mode. In this mode, the
device keeps the power switch off for several switching cycles to keep the output voltage in regulation. This
operation typically occurs in light load condition when the PWM operates in discontinuous mode. See the
Figure 12.
INDUCTOR SELECTION
The selection of the inductor affects steady state operation as well as transient behavior and loop stability. These
factors make it the most important component in power regulator design. There are three important inductor
specifications, inductor value, DC resistance and saturation current. Considering inductor value alone is not
enough.
The inductor’s value determines the inductor ripple current. It is recommended that the peak-to-peak ripple
current given by Equation 3 be set to 30–40% of the DC current. Also, the inductor value should not be beyond
the range in the recommended operating conditions table. It is a good compromise of power losses and inductor
size. Inductor DC current can be calculated as
I in_DC + Vout Iout
Vin h
(6)
Inductor values can have ±20% tolerance with no current bias. When the inductor current approaches saturation
level, its inductance can decrease 20% to 35% from the 0A value depending on how the inductor vendor defines
saturation current. Using an inductor with a smaller inductance value forces discontinuous PWM where the
inductor current ramps down to zero before the end of each switching cycle. This reduces the boost converter’s
maximum output current, causes large input voltage ripple and reduces efficiency. In general, large inductance
value provides much more output and higher conversion efficiency. Small inductance value can give better the
load transient response. For these reasons, a 10µH to 22µH inductor value range is recommended. Table 3 lists
the recommended inductor for the TPS61170.
TPS61170 has built-in slope compensation to avoid sub-harmonic oscillation associated with current mode
control. If the inductor value is lower than 10µH, the slope compensation may not be adequate, and the loop can
be unstable. Therefore, customers need to verify the inductor in their application if it is different from the
recommended values.
Table 3. Recommended Inductors for TPS61170
PART NUMBER
L
(µH)
DCR MAX
(mΩ)
SATURATION CURRENT
(A)
SIZE
(L × W × H mm)
VENDOR
TOKO
A915_Y-100M
10
90
1.3
5.2×5.2×3.0
VLCF5020T-100M1R1-1
10
237
1.1
5×5×2.0
TDK
CDRH4D22/HP
10
144
1.2
5×5×2.4
Sumida
LQH43PN100MR0
10
247
0.84
4.5×3.2×2.0
Murata
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS61170
15
TPS61170
SLVS789A – NOVEMBER 2007 – REVISED FEBRUARY 2008
www.ti.com
SCHOTTKY DIODE SELECTION
The high switching frequency of the TPS61170 demands a high-speed rectification for optimum efficiency.
Ensure that the diode’s average and peak current rating exceeds the average output current and peak inductor
current. In addition, the diode’s reverse breakdown voltage must exceed the switch FET rating voltage of 40V.
So, the ONSemi MBR0540 is recommended for TPS61170. However, Schottky diode of low rating voltage can
be used for low output to save the solution size and cost. For example, 12V output with 20V diode is a good
choice.
COMPENSATION CAPACITOR SELECTION
The TPS61170 has an external compensation, COMP pin, which allows the loop response to be optimized for
each application. The COMP pin is the output of the internal error amplifier. An external resistor R3 and ceramic
capacitors C3 are connected to COMP pin to provide a pole and a zero. This pole and zero, along with the
inherent pole an zero in a current mode control boost converter, determine the close loop frequency response.
This is important to a converter stability and transient response.
The following equations summarize the poles, zeros and DC gain in TPS61170, as shown in the block diagram.
They include the dominant pole (fP1), the output pole (fP2) of a boost converter, the right-half-plane zero (fRHPZ) of
a boost converter, the zero (fZ) generated by R3 and C3, and the DC gain (A).
fP1 =
fP2 =
1
2p x 6 MW x C3
2
2p x Rout x C2
fRHPZ =
fZ =
(7)
Rout
2p x L
æ Vin ö
÷
è Vout ø
(8)
2
x ç
(9)
1
2p x R3 x C3
1.229
(10)
Vin
1
A=
x Gea x 6 MW x
x Rout x
Vout
Vout x Rsense
2
(11)
where Rout is the load resistance, Gea is the error amplifier transconductance located in the ELECTRICAL
CHARACTERISTICS table, Rsense (100mΩ) is a sense resistor in the current control loop. These equations
helps generate a simple bode plot for TPS61170 loop analysis.
Increasing R3 or reducing C3 increases the close loop bandwidth which improves the transient response.
Adjusting R3 and C3 toward opposite direction increase the phase, and help loop stability. For most of the
applications, the recommended value of 10k and 680pF makes an ideal compromise between transient response
and loop stability. To optimize the compensation, use C3 in the range of 100pF to 10nF, and R3 of 10k. See the
TI application report for thorough analysis and description of the boost converter small signal model and
compensation design.
INPUT AND OUTPUT CAPACITOR SELECTION
The output capacitor is mainly selected to meet the requirements for the output ripple and loop stability. This
ripple voltage is related to the capacitor’s capacitance and its equivalent series resistance (ESR). Assuming a
capacitor with zero ESR, the minimum capacitance needed for a given ripple can be calculated using
Equation 12.
ǒV out * V inǓ Iout
C out +
Vout Fs V ripple
(12)
Where, Vripple = peak-to-peak output ripple. The additional output ripple component caused by ESR is calculated
using:
V ripple_ESR + I out RESR
Due to its low ESR, Vripple_ESR can be neglected for ceramic capacitors, but must be considered if tantalum or
electrolytic capacitors are used.
16
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS61170
TPS61170
www.ti.com
SLVS789A – NOVEMBER 2007 – REVISED FEBRUARY 2008
Care must be taken when evaluating a ceramic capacitor’s derating under dc bias, aging and AC signal. For
example, larger form factor capacitors (in 1206 size) have a resonant frequencies in the range of the switching
frequency. So, the effective capacitance is significantly lower. The DC bias can also significantly reduce
capacitance. Ceramic capacitors can loss as much as 50% of its capacitance at its rated voltage. Therefore,
choose a ceramic capacitor with a voltage rating at least 1.5X its expected dc bias voltage.
The capacitor in the range of 1µF to 4.7µF is recommended for input side. The output requires a capacitor in the
range of 1µF to 10µF. The output capacitor affects the loop stability of the boost regulator. If the output capacitor
is below the range, the boost regulator can potentially become unstable.
The popular vendors for high value ceramic capacitors are:
TDK (http://www.component.tdk.com/components.php)
Murata (http://www.murata.com/cap/index.html)
LAYOUT CONSIDERATIONS
As for all switching power supplies, especially those high frequency and high current ones, layout is an important
design step. If layout is not carefully done, the regulator could suffer from instability as well as noise problems.
To maximize efficiency, switch rise and fall times are made as short as possible. To prevent radiation of high
frequency resonance problems, proper layout of the high frequency switching path is essential. Minimize the
length and area of all traces connected to the SW pin and always use a ground plane under the switching
regulator to minimize interplane coupling. The high current path including the switch, Schottky diode, and output
capacitor, contains nanosecond rise and fall times and should be kept as short as possible. The input capacitor
needs not only to be close to the VIN pin, but also to the GND pin in order to reduce the IC supply ripple.
Figure 18 shows a sample layout
C1
R2
Vin
R1
Vin
FB
L1
R3
CTRL
COMP
CTRL
GND
SW
C3
GND
Place enough
VIAs around
thermal pad to
enhance thermal
performance
C2
Minimize the
area of this
trace
Vout
Note: minimize the trace
area at FB pin and
COMP pin
Figure 18. PCB Layout Recommendation
THERMAL CONSIDERATIONS
The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. This
restriction limits the power dissipation of the TPS61170. Calculate the maximum allowable dissipation, PD(max),
and keep the actual dissipation less than or equal to PD(max). The maximum-power-dissipation limit is determined
using Equation 13:
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS61170
17
TPS61170
www.ti.com
SLVS789A – NOVEMBER 2007 – REVISED FEBRUARY 2008
P D(max) +
125°C * T A
RqJA
(13)
where, TA is the maximum ambient temperature for the application. RθJA is the thermal resistance
junction-to-ambient given in Power Dissipation Table.
The TPS61170 comes in a thermally enhanced QFN package. This package includes a thermal pad that
improves the thermal capabilities of the package. The RθJA of the QFN package greatly depends on the PCB
layout and thermal pad connection. The thermal pad must be soldered to the analog ground on the PCB. Using
thermal vias underneath the thermal pad as illustrated in the layout example. Also see the QFN/SON PCB
Attachment application report (SLUA271).
ADDITIONAL TYPICAL APPLICATIONS
L1
10 mH
VIN 12 V
C1
4.7 mF
D1
C2
4.7 mF
TPS 61170
R3
10 kW
VOUT 24 V/ 300 mA
VIN
SW
CTRL
FB
COMP
GND
C3
680 pF
R1
185.1 kW
R2
10 kW
L1: TOKO#A915_Y-100M
C1: Murata GRM188R61A475K
C2: Murata GRM32ER71H475K
D1: ONsemi MBR0540T1
Figure 19. 12V to 24V DCDC Power Conversion
L1
10 mH
VIN 5 V
C1
4.7 mF
D1
TPS 61170
VIN
SW
VOUT 12 V/ 300 mA
C2
4.7 mF
R1
87.6 kW
ON/ OFF
Program FB
R3
10 kW
CTRL
FB
COMP
GND
C3
680pF
R2
10 kW
L1: TOKO#A915_Y-100M
C1: Murata GRM188R61A475K
C2: Murata GRM21BR61E475K
D1: ONsemi MBR0540T1
Figure 20. 5V to 12V DCDC Power Conversion With Programmable Feedback Reference Voltage
18
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS61170
TPS61170
www.ti.com
SLVS789A – NOVEMBER 2007 – REVISED FEBRUARY 2008
C4
1 mF
L1
10 mH
VIN 9 V to 15 V
C1
4.7 mF
L2
10 mH
TPS 61170
VIN
ON /OFF
DIMMING
CONTROL
D1
C2
4.7 mF
VOUT 12 V/ 300 mA
R1
87.6 kW
SW
CTRL
FB
COMP
GND
R2
10 kW
C3
220 nF
L1: TOKO#A915_Y-100M
C1: Murata GRM188R61A475K
C2: Murata GRM21BR61E475K
D1: ONsemi MBR0540T1
*L1, L2 can be replaced by 1:1 transformer
Figure 21. 12V SEPIC (Buck-Boost) Converter
L1
22 mH
VIN 4.5 V to 15 V
C2
1 mF
D2
C1
4.7 mF
VO
48 V/60 mA
D1
TPS61170
C4
4.7 mF
D3
VIN
SW
CTRL
FB
COMP
GND
R1
380 kW
C3
4.7 mF
10k
10 nF
R2
10 kW
L1: TOKO B1000AS-220M
C1: Murata GRM188R61A475K
C2: Murata GRM21BR71H105K
C3, C4: Murata GRM32ER71H475K
D1 – D3: B140
Vo = 1.23 x (R1+R2)/ R2;
Figure 22. 48V Phantom Power Application Circuit
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS61170
19
TPS61170
www.ti.com
SLVS789A – NOVEMBER 2007 – REVISED FEBRUARY 2008
C3
1 mF
L1
33 mH
VIN 3.3 V
D2
C2
1 mF
D3
D4
C1
4.7 mF
SW
CTRL
FB
COMP
GND
VO1
-48 V/30 mA
C4
4.7 mF
VO2
-24 V/40 mA
R1
23.7 kW
C5
4.7 mF
TPS61170
VIN
D1
VIN
1 kW
1 kW
10 kW
Q1
10 nF
L1: TOKO B992AS-330M
C1: Murata GRM188R61A475K
C2, C3: Murata GRM21BR71H105K
C4, C5: Murata GRM32ER71H475K
R2
1.24 kW
D1 – D4: B140
Q1: BCM62B
Q2: MMBT3904TT1
Q2
Vo2 = 1.23 x (R1/ R2); Vo1 = 2Vo2
Figure 23. –24V / –48V Buck-Boost Converter from 3.3-V Input
L1
15 mH pins 1-10
VIN 12 V
1
C1
4.7 mF
10 2
9 3
8
39 pF
VO
48 V/75 mA
D1
C2
4.7 mF
TPS61170
5.6 W
VIN
SW
CTRL
FB
R1
100 kW
Vo = 1.23 x (R1+R2)/ R2;
60 kW
COMP
R2
2.61 kW
GND
10 nF
L1: EPCOS N97
C1: Murata GRM21BR61E475K
C2: Murata GRM32ER71H475K
D1: MURA160
Figure 24. 12V to 48V Flyback Topology
20
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS61170
PACKAGE OPTION ADDENDUM
www.ti.com
20-Mar-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS61170DRVR
ACTIVE
SON
DRV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS61170DRVRG4
ACTIVE
SON
DRV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS61170DRVT
ACTIVE
SON
DRV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS61170DRVTG4
ACTIVE
SON
DRV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Apr-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS61170DRVT
Package Package Pins
Type Drawing
SON
DRV
6
SPQ
250
Reel
Reel
Diameter Width
(mm) W1 (mm)
180.0
12.4
Pack Materials-Page 1
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
2.2
2.2
1.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Apr-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS61170DRVT
SON
DRV
6
250
190.5
212.7
31.8
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DSP
Clocks and Timers
Interface
Logic
Power Mgmt
Microcontrollers
RFID
RF/IF and ZigBee® Solutions
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lprf
Applications
Audio
Automotive
Broadband
Digital Control
Medical
Military
Optical Networking
Security
Telephony
Video & Imaging
Wireless
www.ti.com/audio
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2008, Texas Instruments Incorporated