TPS61080 TPS61081 www.ti.com SLVS644D – FEBRUARY 2006 – REVISED APRIL 2013 HIGH VOLTAGE DC/DC BOOST CONVERTER WITH 0.5-A/1.3-A INTEGRATED SWITCH Check for Samples: TPS61080, TPS61081 FEATURES 1 • • • 2 • • • • • • • • • 2.5-V to 6-V Input Voltage Range Up to 27-V Output Voltage 0.5-A Integrated Switch (TPS61080) 1.3-A Integrated Switch (TPS61081) 12 V/400 mA and 24 V/170 mA From 5-V Input (TYP) Integrated Power Diode 1.2-MHz/600-kHz Selectable Fixed Switching Frequency Input to Output Isolation Short-Circuit Protection Programmable Soft Start Overvoltage Protection Up to 87% Efficiency 10-Pin 3 mm×3 mm QFN Package APPLICATIONS • • • • • • 3.3V to 12V, 5V to 12V and 24V Boost Converter White LED Backlight for Media Form Factor Display OLED Power Supply xDSL Applications TFT-LCD Bias Supply White LED Flash Light DESCRIPTION The TPS61080/1 is a 1.2MHz/600kHz fixed frequency boost regulator designed for high integration, which integrates a power switch, an input/output isolation switch and a power diode. When a short circuit condition is detected, the isolation switch opens up to disconnect the output from the input. As a result, the IC protects itself and the input source from any pin, except VIN, from being shorted to ground. The isolation switch also disconnects the output from input during shutdown to prevent any leakage current. Other provisions for protection include 0.5A/1.3A peak-to-peak over current protection, programmable soft start (SS), over voltage protection (OVP), thermal shutdown and under voltage lockout (UVLO). The IC operates from input supplies including single Li-ion battery, triple NiMH, and regulated 5V, such as USB output. The output can be boosted up to 27V. TPS61080/1 can provide the supply voltages of OLED, TFT-LCD bias, 12V and 24V power rails. The output of TPS61080/1 can also be configured as a current source to power up to 7 WLED in flash light applications. ORDERING INFORMATION TA –40°C to 85°C OVERCURRENT LIMIT PACKAGE PACKAGE MARKING 0.5A(min) TPS61080DRCR BCN 1.3A(min) TPS61081DRCR BCO 0.5A(min) TPS61080DRCT BCN 1.3A(min) TPS61081DRCT BCO TYPICAL APPLICATION Vin 5V TPS61081 VIN L EN C1 4.7 mF L1 4.7 µH Cs 47 nF L SW OUT VO 12 V/250 mA R3 100 Ω FSW SS GND TOP VIEW FB PGND R1 437 kW C3 33 pF VIN SS 4.7 µF R2 49.9 kW SW GND FB OUT Thermal Pad PGND FSW EN 10-PIN 3mm x 3mm x 1mm QFN L1: TDK VLCF5020T-4R7N1R7-1 C1: Murata GRM188R60J105K C2: Murata GRM219R61C475K C3: Feed forward capacitor for stability R3: Noise decoupling resistor Cs: Soft start programming capacitor Figure 1. 5V to 12V, 250mA Step-Up DC/DC Converter 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2013, Texas Instruments Incorporated TPS61080 TPS61081 SLVS644D – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com PIN FUNCTIONS PIN NAME NO. I/O DESCRIPTION L 1 I The inductor is connected between this pin and the SW pin. This pin connects to the source of the isolation FET as well. Minimize trace area at this pin to reduce EMI. VIN 2 I Input pin to the IC. It is the input to the boost regulator, and also powers the IC circuit. It is connected to the drain of the isolation FET as well. EN 6 I Enable pin. When the voltage of this pin falls below enable threshold for more than 74ms, the IC turns off and consumes less than 2 μA current. GND 4 Signal ground of the IC PGND 8 Power ground of the IC. It is connected to the source of the PWM switch. This pin should be made very close to the output capacitor in layout. FB 5 I Voltage feedback pin for the output regulation. It is regulated to an internal reference voltage. An external voltage divider from the output to GND with the center tap connected to this pin programs the regulated voltage. This pin can also be connected to a low side current sense resistor to program current regulation. OUT 9 O Output of the boost regulator. When the output voltage exceeds the 27V overvoltage protection (OVP) threshold, the PWM switch turns off until Vout drops 0.7V below the overvoltage threshold. SW 10 I Switching node of the IC. Connect the inductor between this pin and the L pin. SS 3 I Soft start programming pin. A capacitor between the SS pin and GND pin programs soft start timing. FSW 7 I Switching frequency selection pin. Logic high on the pin selects 1.2MHz, while logic low reduces the frequency to 600KHz for better light load efficiency. Thermal Pad – The thermal pad should be soldered to the analog ground. If possible, use thermal via to connect to ground plane for ideal power dissipation. FUNCTIONAL BLOCK DIAGRAM L1 2 1 VIN Charge Pump C1 EN EN 6 SW Current Sensor OUT SC OVP ShortCircuit BandGap SS 1.229V 3 Ramp Generator SC OVP + 9 OVP R1 Oscillator Thermal Shutdown C2 Clamp MUX FB 5 Submit Documentation Feedback C3 PWM Control 1.2MHz 600KHz Cs 2 10 L R2 Error Amplifer FSW 7 PGND GND 4 8 R3 FB Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: TPS61080 TPS61081 TPS61080 TPS61081 www.ti.com SLVS644D – FEBRUARY 2006 – REVISED APRIL 2013 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT –0.3 to 7 V –0.3 to 7 V Voltage on pin OUT (2) 30V V Voltage on pin SW (2) 30V V Supply Voltages on pin VIN (2) Voltages on pins EN, FB, SS, L and FSW (2) Continuous Power Dissipation See Dissipation Rating Table Operating Junction Temperature Range –40 to 150 °C Storage Temperature Range –65 to 150 °C (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. DISSIPATION RATINGS (1) (2) θJA TA ≤ 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C POWER RATING 3.21°C/W 270°C/W 370 mW 204 mW 148 mW 3.21°C/W 48.7°C/W 2.05 W 1.13 W 821 mW PACKAGE θJC QFN (1) QFN (2) Soldered PowerPAD™ on a standard 2-layer PCB without vias for thermal pad Soldered PowerPAD on a standard 4-layer PCB with vias for thermal pad RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input voltage range 2.5 6.0 VOUT Output voltage range VIN 27 V V L Inductor (1) 4.7 10 μH CIN Input capacitor (1) μF 1 (1) COUT Output capacitor 4.7 30 μF TA Operating ambient temperature –40 85 °C TJ Operating junction temperature –40 125 °C MAX UNIT (1) Refer to application section for further information ELECTRICAL CHARACTERISTICS VIN = 3.6 V, EN = VIN, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP SUPPLY CURRENT VIN Input voltage range IQ Operating quiescent current into VIN Device switching no load 2.5 6.0 6 mA ISD Shutdown current EN = GND 1 μA VUVLO Under-voltage lockout threshold VIN falling Vhys Under-voltage lockout hysterisis 1.65 1.8 50 V V mV ENABLE VEN Enable level voltage VIN = 2.5 V to 6 V Disable level voltage VIN = 2.5 V to 6 V Ren Enable pull down resistor toff EN pulse width to disable 1.2 0.4 400 EN high to low Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: TPS61080 TPS61081 800 1600 74 Submit Documentation Feedback V kΩ ms 3 TPS61080 TPS61081 SLVS644D – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VIN = 3.6 V, EN = VIN, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 4.75 5 5.25 4.6 5 5.4 487 500 513 mV 100 nA 1.229 1.254 V Ω SOFT START Iss Soft start bias current Vclp SS pin to FB pin accuracy TA = 25°C VSS = 500 mV μA FEEDBACK FB IFB Feedback input bias current VFB Feedback regulation voltage VFB = 1.229 V –100 1.204 POWER SWITCH AND DIODE Isolation MOSFET on-resistance RDS(ON) N-channel MOSFET on-resistance 0.06 0.1 VIN = VGS = 3.6 V 0.17 0.22 VIN = VGS = 2.5 V 0.2 0.32 1 2 0.85 1 V 1 μA ILN_NFET N-channel leakage current VDS = 28 V VF Power diode forward voltage Id = 1 A ILN_ISO Isolation FET leakage current L pin to ground Ω μA OC AND SC ILIM N-Channel MOSFET current limit (1) ISC Short circuit current limit tscd Short circuit delay time tscr Short circuit release time VSC OUT short detection threshold (2) TPS61080, FSW = High or FSW = Low 0.5 0.7 1.0 TPS61081, FSW = High or FSW = Low 1.3 1.6 2.0 TPS61080 1.0 2.2 TPS61081 2.0 3.5 VIN – VOUT A A 13 μs 57 ms 1.4 V OSCILLATOR FSW pin high 1.0 1.2 1.5 FSW pin low 0.5 0.6 0.7 90% 94% fS Oscillator frequency Dmax Maximum duty cycle Dmin Minimum duty cycle Rfsw FSW pin pull down resistance 400 FSW high logic 1.6 VFSW FB = 1.0 V MHz 5% 800 FSW low logic 1600 0.8 kΩ V OVP Vovp Output overvoltage protection VOUT rising Output overvoltage protection hysteresis VOUT falling 27 28 29 V 0.7 V 160 °C 15 °C THERMAL SHUTDOWN Tshutdown Thermal shutdown threshold Thysteresis Thermal shutdown threshold hysteresis (1) (2) 4 VIN = 3.6 V, VOUT = 15 V, Duty cycle = 76%. See Figure 6 to Figure 9 for other operation conditions. OUT short circuit condition is detected if OUT stays lower than VIN – VSC for 1.7 ms after IC enables. See the START UP section for details. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: TPS61080 TPS61081 TPS61080 TPS61081 www.ti.com SLVS644D – FEBRUARY 2006 – REVISED APRIL 2013 Table of Graphs FIGURE Efficiency VS IOUT, VIN = 3.6V OUT = 12V, 15V, 20V, 25V, FSW = HIGH, L = 4.7 μH 2 VS IOUT, VIN = 3.6V OUT = 12V, 15V, 20V, 25V, FSW = LOW, L = 10 μH 3 VS IOUT, VIN = 3V, 3.6V, 5V, OUT = 12V, FSW = HIGH, L = 4.7 μH 4 VS IOUT, VIN = 3V, 3.6V, 5V, OUT = 12V, FSW = LOW, L = 10 μH 5 Overcurrent Limit VIN = 3.0V, 3.6V, 5V, FSW = High/Low 6, 7, 8, 9 Line Regulation TPS61081, VIN = 2.5V to 6V, OUT = 12V, IOUT = 100mA 10 Load Regulation TPS61081, VIN = 3.6V, OUT = 12V 11 Soft Start TPS61081, VIN = 3.6V, OUT = 12V, IOUT = 150mA, FSW = HIGH, CSS = 47nF 12 OUT SC Protection TPS61081, VIN = 3.6V, OUT = 12V, IOUT = 150mA, FSW = HIGH 13 Transient Response TPS61080, VIN = 3.6V, OUT = 12V, IOUT = 10mA to 60mA, Cff = 33pF, L = 10μH 14 TPS61081, VIN = 3.6V, OUT = 12V, IOUT = 25mA to 150mA, Cff = 33pF, L = 4.7μH 15 Input and Output Ripple TPS61081, VIN = 3.6V, OUT = 12V, IOUT = 150mA 16 OVP TPS61080/1 17 SS to FB accuracy TPS61080/1 18 Minimum Load Requirement TPS61080/1, VIN = 3.6V and 5V, FSW = HIGH, L = 4.7μH 19 TYPICAL CHARACTERISTICS EFFICIENCY (TPS61081 FSW=HIGH) vs OUTPUT CURRENT EFFICIENCY (TPS61081 FSW=LOW) vs OUTPUT CURRENT 100 100 VI = 3.6 V 90 90 80 80 VO = 16 V 70 VO = 25 V Efficiency - % Efficiency - % VI = 3.6 V VO = 12 V VO = 20 V VO = 25 V 60 60 50 50 40 0 50 100 150 200 IO - Output Current - mA 250 300 VO = 20 V 70 40 0 50 Figure 2. VO = 16 V 100 150 200 IO - Output Current - mA VO = 12 V 250 300 Figure 3. Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: TPS61080 TPS61081 Submit Documentation Feedback 5 TPS61080 TPS61081 SLVS644D – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) EFFICIENCY (TPS61081 FSW=HIGH) vs OUTPUT CURRENT EFFICIENCY (TPS61081 FSW=LOW) vs OUTPUT CURRENT 100 100 VO = 12 V VO = 12 V 90 80 80 VI = 3 V VI = 5 V VI = 3.6 V Efficiency - % Efficiency - % 90 70 60 70 VI = 3.6 V 60 50 50 40 40 30 0 VI = 5 V VI = 3 V 30 50 100 150 200 250 IO - Output Current - mA 300 0 350 50 100 150 200 250 300 350 IO - Output Current - mA Figure 4. Figure 5. OVER CURRENT LIMIT (TPS61080 FSW=LOW) vs DUTY CYCLE OVER CURRENT LIMIT (TPS61080 FSW=HIGH) vs DUTY CYCLE 1 1 VI = 3.6 V 0.8 0.8 0.6 VI = 3 V Current Limit - A Current Limit - A VI = 3.6 V VI = 5 V 0.4 0.2 0 20 0.6 VI = 3 V 0.4 0.2 30 40 50 60 Duty Cycle - % 70 80 90 0 20 30 Figure 6. 6 VI = 5 V Submit Documentation Feedback 40 50 60 Duty Cycle - % Figure 7. 70 80 90 Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: TPS61080 TPS61081 TPS61080 TPS61081 www.ti.com SLVS644D – FEBRUARY 2006 – REVISED APRIL 2013 TYPICAL CHARACTERISTICS (continued) OVER CURRENT LIMIT (TPS61081 FSW=LOW) vs DUTY CYCLE OVER CURRENT LIMIT (TPS61081 FSW=HIGH) vs DUTY CYCLE 2 2 VI = 5 V 1.60 VI = 3.6 V 1.20 0.80 1.20 0.80 0.40 0.40 0 20 VI = 3.6 V VI = 3 V Current Limit - A Current Limit - A 1.60 VI = 3 V VI = 5 V 30 40 50 60 Duty Cycle - % Figure 8. 70 80 0 20 90 30 40 50 60 70 Duty Cycle - % 80 90 Figure 9. LINE REGULATION TPS61081 LOAD REGULATION TPS61081 12.30 12.32 12.29 12.30 VO - Output Voltage - V VO - Output Voltage - V TA = 85 °C 12.28 12.27 12.26 TA = 25 °C 12.25 12.24 TA = -40 °C TA = 85 °C 12.28 TA = 25 °C 12.26 12.24 TA = -40 °C 12.23 12.21 2.5 12.22 IO = 150 mA 12.22 VI = 3.6 V IO = 100 mA VI = 5 V 12.20 3 3.5 4 4.5 5 VI - Input Voltage - V 5.5 6 0 0.05 Figure 10. Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: TPS61080 TPS61081 0.10 0.15 0.20 0.25 0.30 IO - Output Current - A Figure 11. Submit Documentation Feedback 7 TPS61080 TPS61081 SLVS644D – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) Soft Start TPS61081 Vout SC PROTECTION TPS61081 OUT 10V/div, DC SW 10V/div, DC SS 2V/div, DC OUT 10V/div, DC Input Current 500mA/div, DC Input Current 2A/div, DC Inductor Current 500mA/div, DC L 5V/div, DC t - Time - 10 ms/div Figure 13. t - Time - 4 ms/div Figure 12. TRANSIENT RESPONSE TPS61080 TRANSIENT RESPONSE TPS61081 OUT 100 mV/div, AC OUT 200 mV/div, AC Output Current 50 mA/div, DC Output Current 100 mA/div, DC t - Time - 400 ms/div Figure 14. t - Time - 400 ms/div Figure 15. INPUT AND OUTPUT RIPPLE TPS61081 OUT 50 mV/div, AC OVP TPS61081 OUT 1 V/div, DC 27 V Offset VIN 50 mV/div, AC SW 20 V/div, DC SW 10 V/div, DC Inductor Current 1 A/div, DC Inductor Current 500 mA/div, DC t - Time - 400 ns/div Figure 16. 8 Submit Documentation Feedback t - Time - 20 ns/div Figure 17. Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: TPS61080 TPS61081 TPS61080 TPS61081 www.ti.com SLVS644D – FEBRUARY 2006 – REVISED APRIL 2013 TYPICAL CHARACTERISTICS (continued) SS TO FB ACCURACY TPS61080 MINIMUM LOAD REQUIREMENT TPS61081 1.50 1.4 VI = 3.6 V 1.2 IO - Output Current - mA FB - Voltage - V 1.20 0.90 0.60 1 0.8 VI = 5 V 0.6 0.4 VI = 3.6 V 0.30 0.2 0 0 0 0.30 0.60 0.90 SS - Voltage - V 1.20 1.50 6 7 Figure 18. 8 9 10 VO - Output Voltage - V 11 12 Figure 19. Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: TPS61080 TPS61081 Submit Documentation Feedback 9 TPS61080 TPS61081 SLVS644D – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com DETAILED DESCRIPTION OPERATION TPS61080/1 is a highly integrated boost regulator for up to 27V output. In addition to the on-chip 0.5A/1.2A PWM switch and power diode, this IC also builds in an input side isolation switch as shown in the block diagram. One common issue with conventional boost regulator is the conduction path from input to output even when PWM switch is turned off. It creates three problems, inrush current during start up, output leakage voltage under shutdown, and unlimited short circuit current. To address these issues, TPS61080/1 turns off the isolation switch under shutdown mode and short circuit condition to eliminate any possible current path. TPS61080/1 adopts current mode control with constant PWM (pulse width modulation) frequency. The switching frequency can be configured to either 600KHz or 1.2MHz through the FSW pin. 600KHz improves light load efficiency, while 1.2MHz allows using smaller external component. The PWM operation turns on the PWM switch at the beginning of each switching cycle. The input voltage is applied across the inductor and stores the energy as inductor current ramps up. The load current is provided by the output capacitor. When the inductor current across the threshold set by error amplifier output, the PWM switch is turned off, and the power diode is forward biased. The inductor transfers its stored energy to replenish the output capacitor. This operation repeats in the next switching cycle. The error amplifier compares the FB pin voltage with an internal reference, and its output determines the duty cycle of the PWM switching. This close loop system requires loop compensation for stable operation. TPS61080/1 has internal compensation circuitry which accommodates a wide range of input and output voltages. The TPS61080/1 integrates slope compensation to the current ramp to avoid the sub-harmonic oscillation that is intrinsic to current mode control schemes. START UP TPS61080/1 turns on the isolation FET when the EN pin is pulled high, provided that the input voltage is higher than the undervoltage lockout threshold. The Vgs of the isolation FET is clamped to maintain high on-resistance and limits the current to 30mA charging the output capacitor. This feature limits the in-rush current and maximum start up current to 30mA. Once the output capacitor is charged to VIN, the IC removes the Vgs clamp to fully turn on the isolation FET and at the same time actives soft start by charging the capacitor on the SS pin. If OUT stays lower than VIN-Vsc following a 1.7ms delay after enable is taken high, the IC recognizes a short circuit condition. In this case, the isolation FET turns off, and IC remains off until the EN pin toggles or VIN cycles through power on reset (POR). During the soft start phase, the SS pin capacitor is charged by internal bias current of the SS pin. The SS pin capacitor programs the ramp up slope. The SS pin voltage clamps the reference voltage of the FB pin, therefore the output capacitor rise time follows the SS pin voltage. Without the soft start, the inductor current could reach the over current limit threshold, and there is potential for output overshoot. see the APPLICATION INFORMATION section on selecting soft start capacitor values. Pulling the SS pin to ground disables the PWM switching. However, unlike being disabled by pulling EN low, the IC continues to draw quiescent current and the isolation FET remains on. OVERCURRENT AND SHORT CIRCUIT PROTECTION TPS61080/1 has a pulse by pulse over current limit feature which turns off the power switch once the inductor current reaches the overcurrent limit. The PWM circuitry resets itself at the beginning of the next switch cycle. The overcurrent threshold determines the available output current. However, the maximum output is also a function of the input voltage, output voltage, switching frequency and inductor value. Larger inductor values and 1.2MHz switching frequency increase the current output capability because of the reduced current ripple. See the APPLICATION INFORMATION section for the maximum output current calculation. In typical boost converter topologies, if the output is grounded, turning off the power switch does not limit the current because a current path exists from the input to output through the inductor and power diode. To eliminate this path, TPS61080/1 turns off the isolation FET between the input and the inductor. This circuit is triggered when the inductor current remains above short circuit current limit for more than 13μs, or the OUT pin voltage falls below VIN-1.4V for more than 1.7ms. An internal catch-diode between the L pin and ground turns on to provide a current discharge path for the inductor. If the short is caused by the output being low, then the IC shuts down and waits for EN to be toggled or a POR. If the short protection is triggered by short circuit current limit, the 10 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: TPS61080 TPS61081 TPS61080 TPS61081 www.ti.com SLVS644D – FEBRUARY 2006 – REVISED APRIL 2013 IC attempts to start up one time. After 57ms, the IC restarts in a fashion described in the above section. If the short is cleared, the boost regulator properly starts up and reaches output regulation. However, after reaching regulation, if another event of short circuit current limit occurs, the IC goes into shutdown mode again, and the fault can only be cleared by toggling the EN pin or POR. Under a permanent short circuit, the IC shuts down after a start up failure and waits for POR or the EN pin toggling. The same circuit also protects the ICs and external components when the SW pin is shorted to ground. These features provide much more comprehensive and reliable protection than the conventional boost regulator. Table 1 lists the IC protection against the short of each IC pin. Table 1. TPS61080/1 Short Circuit Protection Mode SHORTED TO GND FAULT DETECTION IC OPERATION HOW TO CLEAR THE FAULT L, SW INDUCTOR > ISC for 13 μs Turn off isolation FET IC restarts after 57ms; If it happens again, the fault can only be cleared by toggling EN or POR. OUT (during start up) OUT <Vin– 1.4V for 2 ms IC shuts down Cleared by toggling EN or POR OUT (after start up) OUT <Vin– 1.4V without delay IC shuts down Cleared by toggling EN or POR EN N/A IC disabled N/A FSW N/A 600 kHz switching frequency N/A SS N/A Disable PWM switching and no output; N/A but still dissipate quiescent current. FB N/A Over voltage protection of the OUT pin OUT voltage fails by OVP hysteresis GND, PGND, VIN N/A N/A N/A OVERVOLTAGE PROTECTION When TPS61080/1 is configured as regulated current output as shown in the TYPICAL APPLICATIONS, the output voltage can run away if the current load is disconnected. The over voltage condition can also occur if the FB pin is shorted to the ground. To prevent the SW node and the output capacitor from exceeding the maximum voltage rating, an over voltage protection circuit turns off the boost regulator as soon as the output voltage exceeds the OVP threshold. When the output voltage falls 0.7V below the OVP threshold, the regulator resumes the PWM switching unless the output voltage exceeds the OVP threshold. UNDERVOLTAGE LOCKOUT (UVLO) An undervoltage lockout prevents mis-operation of the device for input voltages below 1.65 V (typical). When the input voltage is below the undervoltage threshold, the device remains off and both PWM and isolation switch are turned off, providing isolation between input and output. The undervoltage lockout threshold is set below minimum operating voltage of 2.5V to avoid any transient VIN dip to trigger UVLO and causes converter reset. For the VIN voltage between UVLO threshold and 2.5V, the IC still maintains its operation. However, the spec is not assured. THERMAL SHUTDOWN An internal thermal shutdown turns off the isolation and PWM switches when the typical junction temperature of 160°C is exceeded. The IC restarts if the junction temperature drops by 15°C. ENABLE Connecting the EN pin low turns off the power switch immediately, but keeps the isolation FET on. If the EN pin is logic low for more than 74ms, the IC turns off the isolation FET and enters shutdown mode drawing less than 1μA current. The enable input pin has an internal 800kΩ pull down resistor to disable the device when the pin is floating. Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: TPS61080 TPS61081 Submit Documentation Feedback 11 TPS61080 TPS61081 SLVS644D – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com FREQUENCY SELECTION The FSW pin can be connected to either a logic high or logic low to program the switching frequency to1.2MHz or 600kHz respectively. The 600kHz switching frequency provides better efficiency because of lower switching losses. This advantage becomes more evident at light load when switching losses dominate overall losses. The higher switching frequency shrinks external component size and thus the size of power solution. High switching frequency also improves load transient response since the smaller value inductor takes less time to ramp up and down current. The other benefits of high switching frequency are lower output ripples and a higher maximum output current. Overall, it is recommended to use 1.2MHz switching frequency unless light load efficiency is a major concern. The FSW pin has internal 800kΩ pull up resistor to the VIN pin. Floating this pin programs the switching frequency to 1.2MHz. MAXIMUM and MINIMUM OUTPUT CURRENT The over-current limit in a boost converter limits the maximum input current and thus maximum input power from a given input voltage. Maximum output power is less than maximum input power due to power conversion losses. Therefore, the over-current limit, the input voltage, the output voltage and the conversion efficiency all affect maximum current output. Since the over-current limit clamps the peak inductor current, the current ripple has to be subtracted to derive maximum DC current. The current ripple is a function of the switching frequency, the inductor value and the duty cycle. 1 Ip + 1 ) 1 Fs L Vout)Vf*Vin Vin (1) Ǔ ǒ where Ip = inductor peak to peak ripple L = inductor value Vf = power diode forward voltage Fs = Switching frequency The following equations take into account of all the above factors for maximum output current calculation. ǒ Vin Ilim * Iout_max + Ip 2 Ǔ h Vout (2) where Ilim = overcurrent limit η = conversion efficiency To minimize the variation in the overcurrent limit threshold, the TPS61080/1 uses the VIN and OUT pin voltage to compensate for the variation caused by the slope compensation. However, the threshold still has some dependency on the VIN and OUT voltage. Use Figure 6 to Figure 9 to identify the typical over-current limit in your application, and use 25% tolerance to account for temperature dependency and process variations. Because of the minimum duty cycle of each power switching cycle of TPS61080/1, the device can lose regulation at the very light load. Use the following equations to calculate PWM duty cycle under discontinues conduction mode (DCM). Ipeak + Ǹ2 D+L Iload Ipeak Vin Vout ) Vf * Vin L Fs Fs (3) Where Ipeak = inductor peak to peak ripple in DCM Iload = load current D = PWM switching duty cycle 12 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: TPS61080 TPS61081 TPS61080 TPS61081 www.ti.com SLVS644D – FEBRUARY 2006 – REVISED APRIL 2013 If the calculated duty cycle is less than 5%, minimum load should be considered to the boost output to ensure regulation. Figure 19 provides quick reference to identify the minimum load requirements for two input voltages. APPLICATION INFORMATION PROGRAM OUTPUT VOLTAGE OUT R1 TPS61080/1 C1 C2 4.7 mF R3 100 W FB R2 Figure 20. Feed Forward Capacitor Connecting With Feedback Resistor Divider To program the output voltage, select the values of R1 and R2 (See Figure 20) according to the following equation. R1 + R2 Vout * 1Ǔ ǒ1.229V (4) A optimum value for R2 is around 50kΩ which sets the current in the resistor divider chain to 1.229V/50kΩ = 24.58μA. The output voltage tolerance depends on the VFB accuracy and the resistor divider. FEED FORWARD CAPACITOR A feed forward capacitor on the feedback divider, shown in Figure 20, improves transient response and phase margin. This network creates a low frequency zero and high frequency pole at 1 Fz + 2pR1 C1 (5) FP + 1 ǒR11 ) R21 Ǔ 2pC1 (6) The frequency of the pole is determined by C1 and paralleled resistance of R1 and R2. For high output voltage, R1 is much bigger than R2. So 1 FP + when R1 u u R2. 2pR2C1 (7) The loop gains more phase margin from this network when (Fz+Fp)/2 is placed right at crossover frequency, which is approximately 15kHz with recommended L and C. The typical value for the zero frequency is between 1kHz to 10KHz. For high output voltage, the zero and pole are further apart which makes the feed forward capacitor very effective. For low output voltage, the benefit of the feed forward capacitor is less visible. Table 2 gives the typical R1, R2 and the feed forward capacitor values at the certain output voltage. However, the transient response is not greatly improved which implies that the zero frequency is too high or low to increase the phase margin. Table 2. Recommended Feed Forward Capacitor Values With Different Output Voltage Output Voltage R1 R2 C1(Feed Forward) 12V 437kΩ 49.9kΩ 33pF 16V 600kΩ 49.9kΩ 42pF 20V 762kΩ 49.9kΩ 56pF 25V 582kΩ 30.1kΩ 120pF Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: TPS61080 TPS61081 Submit Documentation Feedback 13 TPS61080 TPS61081 SLVS644D – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com The 100Ω resistor is added to reduce noise coupling from the OUT to the FB pin through the feed forward capacitor. Without the resistor, the regulator may oscillate at high output current. SOFT START CAPACITOR The voltage at the SS pin clamps the internal reference voltage, which allows the output voltage to ramp up slowly. The soft start time is calculated as C 1.229 t ss + ss I ss (8) where Css = soft start capacitor Iss = soft start bias current (TYP 5 μA) 1.229V is the typical value of the reference voltage. During start up, input current has to be supplied to charge the output capacitor. This current is proportional to rising slope of the output voltage, and peaks when output reaches regulation. I ss V out I in_cout + Cout C ss V in h (9) Where Iin_cout = additional input current for charging the output capacitor The maximum input during soft start is V out I in_ss + I in_cout ) I load Vin h (10) Output overshoot can occur if the input current at startup exceeds the inductor saturation current and/or reaches current limit because the error amplifier loses control of the voltage feedback loop. The in-rush current can also pull down input sources, potentially causing system reset. Therefore, select Css to make Iin_ss stay below the inductor saturation current, the IC over current limit and the input's maximum supply current. TPS61080/1 can also be configured for constant current output, as shown in the typical applications. In this configuration, a current sense resistor is connected to FB pin for output current regulation. In order to reduce power loss on the sense resistor, FB pin reference voltage can be lowered by connecting a resistor to the SS pin The new reference voltage is simply the resistor value times the SS pin bias current. However, keep in mind that this reference has higher tolerance due to the tolerance of the bias current and sense resistor, and the offset of the clamp circuit. Refer to the specification VCLP and ISS to calculate the tolerance as following. K ref + ǸK2Vclp ) K2Iss ) K2R (11) Where Kref = percentage tolerance of the FB reference voltage. KVclp = percentage tolerance of the clamp circuit. Klss = percentage tolerance of the SS pin bias current. KR = percentage tolerance of the SS pin resistor. Without considering the SS pin resistor tolerance, the FB reference voltage has ±5.6% under the room temperature. INDUCTOR SELECTION Because the selection of the inductor affects steady state operation, transient behavior and loop stability, the inductor is the most important component in power regulator design. There are three important inductor specifications, inductor value, DC resistance and saturation current. Considering inductor value alone is not enough. 14 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: TPS61080 TPS61081 TPS61080 TPS61081 www.ti.com SLVS644D – FEBRUARY 2006 – REVISED APRIL 2013 The inductor's inductance value determines the inductor ripple current. It is generally recommended to set peak to peak ripple current given by Equation 4 to 30–40% of DC current. Also, the inductor value should not be beyond the range in the recommended operating conditions table. It is a good compromise of power losses and inductor size. Inductor DC current can be calculated as I out V I L_DC + out V in h (12) The internal loop compensation for PWM control is optimized for the external component shown in the typical application circuit with consideration of component tolerance. Inductor values can have ±20% tolerance with no current bias. When the inductor current approaches saturation level, its inductance can decrease 20% to 35% from the 0A value depending on how the inductor vendor defines saturation current. Using an inductor with a smaller inductance value forces discontinuous PWM in which inductor current ramps down to zero before the end of each switching cycle. It reduces the boost converter’s maximum output current, causes large input voltage ripple and reduces efficiency. An inductor with larger inductance reduces the gain and phase margin of the feedback loop, possibly resulting in instability. For these reasons, 10μH inductors are recommended for TPS61080 and 4.7μH inductors for TPS61081 for most applications. However, 10μH inductor is also suitable for 600kHz switching frequency. Regulator efficiency is dependent on the resistance of its high current path and switching losses associated with the PWM switch and power diode. Although the TPS61080/1 has optimized the internal switches, the overall efficiency still relies on inductor’s DC resistance (DCR); Lower DCR improves efficiency. However, there is a trade off between DCR and inductor size, and shielded inductors typically have higher DCR than unshielded ones. Table 3 list recommended inductor models. Table 3. Recommended Inductor for TPS61080/1 TPS61080 L (μH) DCR MAX (mΩ) SATURATION CURRENT (A) Size (L×W×H mm) VENDOR VLCF4018T 10 188 0.74 4.0 × 4.0 × 1.8 TDK CDRH4D16NP 10 118 0.96 4.0 × 4.0 × 1.8 Sumida LQH43CN100K 10 240 0.65 4.5 × 3.6 × 2.6 Murata L (μH) DCR MAX (mΩ) SATURATION CURRENT (A) Size (L×W×H mm) VENDOR VLCF5020T 4.7 122 1.74 5.0 × 5.0 × 2.0 TDK VLCF5014A 6.8 190 1.4 5.0 × 5.0 × 1.4 TDK CDRH4D14/HP 4.7 140 1.4 4.8 × 4.8 × 1.5 Sumida CDRH4D22/HP 10 144 1.5 5.0 × 5.0 × 2.4 Sumida TPS61081 INPUT AND OUTPUT CAPACITOR SELECTION The output capacitor is mainly selected to meet output ripple and loop stability requirements. This ripple voltage is related to the capacitor’s capacitance and its equivalent series resistance (ESR). Assuming a capacitor with zero ESR, the minimum capacitance needed for a given ripple can be calculated by C out + ǒVout * VinǓI out Vout Fs V ripple (13) Vripple = Peak to peak output ripple. For VIN = 3.6V, VOUT = 20V, and Fs = 1.2MHz, 0.1% ripple (20mV) would require 1.0μ capacitor, however, the minimum recommended output capacitor for control loop stability is 4.7 μF. The output capacitor value must be less than 30µF to ensure the startup current charges the output capacitor to the input voltage in less than 1.7ms. For this value, ceramic capacitors are a good choice for its size, cost and availability. The additional output ripple component caused by ESR is calculated using: V ripple_ESR + I out RESR (14) Due to its low ESR, Vripple_ESR can be neglected for ceramic capacitors, but must be considered if tantalum or electrolytic capacitors are used. Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: TPS61080 TPS61081 Submit Documentation Feedback 15 TPS61080 TPS61081 SLVS644D – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com During a load transient, the output capacitor at the output of the boost converter has to supply or absorb transient current before the inductor current ramps up its steady state value. Larger capacitors always help to reduce the voltage over and under shoot during a load transient. A larger capacitor also helps loop stability. Care must be taken when evaluating a ceramic capacitor’s derating under dc bias, aging and AC signal. For example, larger form factor capacitors (in 1206 size) have their self resonant frequencies in the range of the switching frequency. So the effective capacitance is significantly lower. The Dc bias can also significantly reduce capacitance. Ceramic capacitors can loss as much as 50% of its capacitance at its rated voltage. Therefore, almost leave margin on voltage rating to ensure adequate capacitance. The popular vendors for high value ceramic capacitors are: TDK (http://www.component.tdk.com/components.php) Murata (http://www.murata.com/cap/index.html) LAYOUT CONSIDERATION As for all switching power supplies, the layout is an important step in the design, especially for high current and high switching frequencies. If layout is not carefully done, the regulator could show stability problems as well as EMI problems. Therefore, use wide and short traces for high current paths and for power ground tracks. Input capacitor needs not only close to the VIN, but also to the GND pin to reduce the voltage ripple seen by the IC. The L and SW pin are conveniently located on the edge of the IC, therefore inductor can be placed close to the IC. The output capacitor needs to be placed near the load to minimize ripple and maximize transient performance. To minimize the effects of ground noise, use a common node for all power ground that is connected to the PGND pin, and a different one for signal ground tying to the GND pin. Connect two ground nodes together at the load if possible. This allows the GND pin to be close to the output ground for good DC regulation. Any voltage difference between these two nodes would be gained up by feedback divider on the output. It is also beneficial to have the ground of the output capacitor close to PGND since there is a large current between them. To lay out signal ground, it is recommended to use short traces separated from power ground traces. Vin Vout L1 C2 C1 Th al m er d Pa Cs PGND GND R2 R3* EN FSW R1 C3* 16 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: TPS61080 TPS61081 TPS61080 TPS61081 www.ti.com SLVS644D – FEBRUARY 2006 – REVISED APRIL 2013 TYPICAL APPLICATION 3.3 V to 12 V, 80 mA Step-up DC/DC Converter L1 10 mH TPS61080 Vin 3.3 V VIN L C1 1 mF SW R3 100 W FSW SS GND CS 47 nF 12 V/80 mA OUT EN R1 438.2 kW FB PGND C2 33 pF C3 4.7 mF R2 50 kW L1: Sumida CDRH4D16FBNP-100NC C1: Murata GRM188R60J105K; C3: Murata GRM219R61C475K Figure 21. 5 V to 24 V, 120 mA Step-up DC/DC Converter L1 4.7 mH TPS61081 Vin 5 V VIN L EN C1 4.7 mF SW FSW SS FB GND PGND CS 24 V/120 mA OUT R3 100 W R1 555.8 kW C2 120 pF C3 4.7 mF R1 30 kW 47 nF L1: TDK VLCF5020T- 4RN1R7-1 C1: Murata GRM188R60J475K; C3: Murata GRM55ER61H475K Figure 22. 50 mA Torch Light and 100 mA Flash Light L1 4.7 mH Torch light Flash light TPS61081 Vin 3.6 V VIN C1 1 mF EN L SW OUT FSW SS RSS GND 100 kW FB C2 4.7 mF PGND R1 10 W R2 10 W ON/OFF Flash light L1: TDK VLCF5020T- 4R7N1R7-1 C1: Murata GRM188R60J105K; C2: Murata GRM219R61C475K Figure 23. Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: TPS61080 TPS61081 Submit Documentation Feedback 17 TPS61080 TPS61081 SLVS644D – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com 30 WLEDs Driver in Media Factor Form Display L1 4.7 mH 10 strings VIN C1 4. 7 mF R2 80 kW PWM Signal 10.5 V/200 mA TPS61081 Vin 5 V L SW EN OUT C2 4.7 mF FSW SS GND R1 80 kW FB PGND Rset 1W L1: TDK VLCF5020T- 4R7N1R7-1 C1: Murata GRM188R60J475K; C2: Murata GRM219R61C475K Figure 24. +/ – 15 V Dual Output Converter L1 10 mH TPS61080 Vin 5 V L VIN EN C1 4.7 mF -15V/30 mA C2 0.1 mF SW 15V/30 mA OUT R1 560.3 KW FSW SS GND Cs 20nF C4 4.7 mF D2 D1 FB PGND C3 4.7 mF R1 50 KW L1: Sumida CDRH4D16NP-100NC C1: Murata GRM188R60J475K; C3,C4: Murata GRM219R61C475K D1,D2: ON Semiconductor MBR0520 Figure 25. 5 V to 50 V,50 mA Step-up DC/DC Converter with Output Doubler L1 4.7 mH 50 V/50 mA C2 1 mF TPS61081 Vin 5 V VIN EN L SS Cs 20nF GND D2 R1 794 KW SW C4 4.7 mF OUT C3 4.7 mF FSW C1 4.7 mF D1 FB PGND R2 20 KW L1: TDK VLCF5020T-4R7N1R7-1 C1: Murata GRM188R60J475K; C3: Murata GRM219R61C475K D1,D2: ON Semiconductor MBR0520 Figure 26. 18 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: TPS61080 TPS61081 TPS61080 TPS61081 www.ti.com SLVS644D – FEBRUARY 2006 – REVISED APRIL 2013 REVISION HISTORY Changes from Original (February 2006) to Revision A • Page Changed the Typical Application circuit ................................................................................................................................ 1 Changes from Revision A (February 2006) to Revision B • Page Changed from a 1 page Product Preview to the full data sheet ........................................................................................... 1 Changes from Revision B (January 2007) to Revision C Page • Added a Max value of 30µF to COUT in the Recommended Operating Conditions Table .................................................... 3 • Added sentence "The output capacitor value must be...." to the Input and Output Capacitor Selection section ............... 15 Changes from Revision C (July 2011) to Revision D Page • Changed Note 2 of the Electrical Characteristics table ........................................................................................................ 4 • Changed the first paragraph of the START UP section ..................................................................................................... 10 Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: TPS61080 TPS61081 Submit Documentation Feedback 19 PACKAGE OPTION ADDENDUM www.ti.com 15-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) TPS61080DRCR ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BCN TPS61080DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BCN TPS61080DRCT ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BCN TPS61080DRCTG4 ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BCN TPS61081DRCR ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BCO TPS61081DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BCO TPS61081DRCT ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BCO TPS61081DRCTG4 ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BCO (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 15-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TPS61080DRCR SON DRC 10 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS61080DRCT SON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS61081DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS61081DRCT SON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS61080DRCR SON DRC 10 3000 367.0 367.0 35.0 TPS61080DRCT SON DRC 10 250 210.0 185.0 35.0 TPS61081DRCR SON DRC 10 3000 367.0 367.0 35.0 TPS61081DRCT SON DRC 10 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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