Data Sheet 26184.22D 3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR A3977xED 1 44 43 OUT 1B GND 2 SLEEP GND 3 ENABLE GND 4 LOAD SUPPLY 1 HOME 5 SENSE 1 OUT 1A 6 DIR (PLCC) 42 41 40 VBB1 7 8 PFD 9 39 NC CHARGE PUMP NC NC PWM TIMER TRANSLATOR & CONTROL LOGIC RC1 10 GND 11 GND 12 GND 13 REF 14 37 CP1 36 VCP 35 GND 34 GND 33 GND REG ÷8 32 RC2 15 LOGIC SUPPLY 16 38 CP2 VREG 31 STEP 30 NC VDD NC 17 29 NC 21 22 23 24 25 26 27 28 GND GND GND SUPPLY LOAD 2 SR RESET OUT 2B MS 2 20 MS1 19 SENSE 2 18 OUT 2A VBB2 Dwg. PP-075-1 ABSOLUTE MAXIMUM RATINGS at TA = +25°C Load Supply Voltage, VBB ............. 35 V Output Current, IOUT .................. ±2.5 A* Logic Supply Voltage, VDD ........... 7.0 V Logic Input Voltage Range, VIN (tw >30 ns) ..... -0.3 V to VDD + 0.3 V (tw <30 ns) ........... -1 V to VDD + 1 V Sense Voltage, VSENSE ................. 0.5 V Reference Voltage, VREF ................ VDD Package Power Dissipation, PD ................................. See page 3 Operating Temperature Range, TA (A3977Kx) ............ -40°C to +125°C (A3977Sx) .............. -20°C to +85°C Junction Temperature, TJ ......... +150°C Storage Temperature Range, TS ......................... -55°C to +150°C * Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C. The A3977xED and A3977xLP are complete microstepping motor drivers with built-in translator. They are designed to operate bipolar stepper motors in full-, half-, quarter-, and eighth-step modes, with output drive capability of 35 V and ±2.5 A. The A3977 includes a fixed off-time current regulator that has the ability to operate in slow-, fast-, or mixed-decay modes. This currentdecay control scheme results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. The translator is the key to the easy implementation of the A3977. By simply inputting one pulse on the STEP input the motor will take one step (full, half, quarter, or eighth depending on two logic inputs). There are no phase-sequence tables, high-frequency control lines, or complex interfaces to program. The A3977 interface is an ideal fit for applications where a complex µP is unavailable or over-burdened. Internal synchronous-rectification control circuitry is provided to improve power dissipation during PWM operation. Internal circuit protection includes thermal shutdown with hysteresis, under-voltage lockout (UVLO) and crossover-current protection. Special power-up sequencing is not required. The A3977 is supplied in a choice of two power packages, a 44-pin plastic PLCC with copper batwing tabs (suffix ED), and a thin (<1.2 mm), 28pin TSSOP with an exposed thermal pad (suffix LP). The SLP package is available in a lead-free version (100% matte tin leadframe). FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ±2.5 A, 35 V Output Rating Low rDS(on) Outputs, 0.45 Ω Source, 0.36 Ω Sink Typical Automatic Current Decay Mode Detection/Selection 3.0 V to 5.5 V Logic Supply Voltage Range Mixed, Fast, and Slow Current Decay Modes Home Output Synchronous Rectification for Low Power Dissipation Internal UVLO and Thermal Shutdown Circuitry Crossover-Current Protection Always order by complete part number: Part Number A3977KED A3977KLP A3977SED A3977SED-T A3977SLP A3977SLP-T Package 44-pin PLCC 28-pin TSSOP 44-pin PLCC 44-pin PLCC; Lead-free 28-pin TSSOP 28-pin TSSOP; Lead-free 3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR FUNCTIONAL BLOCK DIAGRAM VREG LOGIC SUPPLY 2V UVLO AND FAULT VDD REF. SUPPLY CP2 CP1 CHARGE PUMP REGULATOR VCP LOAD SUPPLY BANDGAP VBB1 REF DAC SENSE1 VCP DMOS H BRIDGE + OUT1A RC1 PWM LATCH BLANKING MIXED DECAY OUT1B PWM TIMER 4 STEP MS1 MS2 CONTROL LOGIC RESET HOME SLEEP VPFD GATE DRIVE SENSE1 TRANSLATOR DIR DMOS H BRIDGE VBB2 OUT2A SR OUT2B ENABLE PWM TIMER PFD 4 PWM LATCH BLANKING MIXED DECAY RC2 + - SENSE2 DAC Dwg. FP-050-2 2 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 2002, 2003 Allegro MicroSystems, Inc. 3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR (TSSOP) 28 LOAD SUPPLY1 2 27 SLEEP DIR 3 26 ENABLE OUT1A 4 25 OUT1B PFD 5 RC1 6 AGND 7 REF 8 ÷8 CHARGE PUMP HOME VBB1 TRANSLATOR & CONTROL LOGIC 1 PWM TIMER SENSE1 24 CP2 23 CP1 22 VCP 21 PGND 20 VREG 19 STEP RC2 9 LOGIC SUPPLY 10 OUT2A 11 18 OUT2B MS2 12 17 RESET MS1 13 16 SR SENSE2 14 15 LOAD SUPPLY2 REG VDD VBB2 ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS A3977xLP 5.0 SUFFIX '–LP', RθJA = 28°C/W* 4.0 SUFFIX '–ED', RθJA = 32°C/W† 3.0 SUFFIX '–LP', RθJA = 33°C/W† 2.0 1.0 SUFFIX 'S–' SUFFIX 'K–' 0 25 50 75 100 125 AMBIENT TEMPERATURE IN °C 150 Dwg. GP-018-2A Dwg. PP-075 Package Thermal Resistance, RθJA A3977xLP ......................... 28°C/W* A3977xED ........................ 32°C/W† A3977xLP ......................... 33°C/W† * Measured on JEDEC standard “High-K” four-layer board. † Measured on typical two-sided PCB with three square inches (1935 mm2) copper ground area. Table 1. Microstep Resolution Truth Table MS1 L H L H www.allegromicro.com MS2 L L H H Resolution Full step (2 phase) Half step Quarter step Eighth step 3 3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 35 V, VDD = 3.0 V to 5.5V (unless otherwise noted) Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units 8.0 – 35 V During sleep mode 0 – 35 V VOUT = VBB – <1.0 20 µA VOUT = 0 V – <1.0 -20 µA Source driver, IOUT = -2.5 A – 0.45 0.57 Ω Sink driver, IOUT = 2.5 A – 0.36 0.43 Ω Source diode, IF = -2.5 A – – 1.4 V Sink diode, IF = 2.5 A – – 1.4 V fPWM < 50 kHz – – 8.0 mA Operating, outputs disabled – – 6.0 mA Sleep mode – – 20 µA 3.0 5.0 5.5 V Output Drivers Load Supply Voltage Range Output Leakage Current Output On Resistance Body Diode Forward Voltage Motor Supply Current VBB IDSS rDS(on) VF IBB Operating Control Logic Logic Supply Voltage Range VDD Logic Input Voltage VIN(1) 0.7VDD – – V VIN(0) – – 0.3VDD V Logic Input Current Operating IIN(1) VIN = 0.7VDD -20 <1.0 20 µA IIN(0) VIN = 0.3VDD -20 <1.0 20 µA 500* – – kHz Maximum STEP Frequency fSTEP HOME Output Voltage VOH IOH = -200 µA 0.7VDD – – V VOL IOL = 200 µA – – 0.3VDD V Blank Time Fixed Off Time tBLANK Rt = 56 kΩ, Ct = 680 pF 700 950 1200 ns toff Rt = 56 kΩ, Ct = 680 pF 30 38 46 µs continued next page … 4 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3977 MICROSTEPPPING DMOS DRIVER WITH TRANSLATOR ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 35 V, VDD = 3.0 V to 5.5V (unless otherwise noted) Limits Characteristic Control Logic (cont’d) Mixed Decay Trip Point Symbol Test Conditions Min. Typ. PFDH – 0.6VDD PFDL – 0.21VDD Ref. Input Voltage Range VREF Operating 0 – Reference Input Current IREF – 0 EG VREF = 2 V, Phase Current = 38.27% – – Gain (Gm) Error VREF = 2 V, Phase Current = 70.71% – – (note 3) – – VREF = 2 V, Phase Current = 100.00% Crossover Dead Time tDT SR enabled 100 475 – 165 Thermal Shutdown Temp. TJ Thermal Shutdown Hysteresis ∆TJ – 15 2.45 2.7 UVLO Enable Threshold VUVLO Increasing VDD UVLO Hysteresis ∆VUVLO 0.05 0.10 Logic Supply Current IDD fPWM < 50 kHz – – Outputs off – – Sleep mode – – * Operation at a step frequency greater than the specified minimum value is possible but not warranteed. NOTES: 1. Typical Data is for design information only. 2. Negative current is defined as coming out of (sourcing) the specified device terminal. 3. EG = ([VREF/8] – VSENSE)/(VREF/8) www.allegromicro.com Max. Units – – VDD ±3.0 ±10 ±5.0 ±5.0 800 – – 2.95 – 12 10 20 V V V µA % % % ns °C °C V V mA mA µA 5 3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR Functional Description Device Operation. The A3977 is a complete microstepping motor driver with built in translator for easy operation with minimal control lines. It is designed to operate bipolar stepper motors in full-, half-, quarterand eighth-step modes. The current in each of the two output H-bridges, all n-channel DMOS, is regulated with fixed off time pulse-width modulated (PWM) control circuitry. The H-bridge current at each step is set by the value of an external current sense resistor (RS), a reference voltage (VREF), and the DAC’s output voltage controlled by the output of the translator. At power up, or reset, the translator sets the DACs and phase current polarity to initial home state (see figures for home-state conditions), and sets the current regulator for both phases to mixed-decay mode. When a step command signal occurs on the STEP input the translator automatically sequences the DACs to the next level (see table 2 for the current level sequence and current polarity). The microstep resolution is set by inputs MS1 and MS2 as shown in table 1. If the new DAC output level is lower than the previous level the decay mode for that H-bridge will be set by the PFD input (fast, slow or mixed decay). If the new DAC level is higher or equal to the previous level then the decay mode for that H-bridge will be slow decay. This automatic current-decay selection will improve microstepping performance by reducing the distortion of the current waveform due to the motor BEMF. Reset Input (RESET). The RESET input (active low) sets the translator to a predefined home state (see figures for home state conditions) and turns off all of the DMOS outputs. The HOME output goes low and all STEP inputs are ignored until the RESET input goes high. Home Output (HOME). The HOME output is a logic output indicator of the initial state of the translator. At power up the translator is reset to the home state (see figures for home state conditions). 6 Step Input (STEP). A low-to-high transition on the STEP input sequences the translator and advances the motor one increment. The translator controls the input to the DACs and the direction of current flow in each winding. The size of the increment is determined by the state of inputs MS1 and MS2 (see table 1). Microstep Select (MS1 and MS2). Input terminals MS1 and MS2 select the microstepping format per table 1. Changes to these inputs do not take effect until the STEP command (see figure). Direction Input (DIR). The state of the DIRECTION input will determine the direction of rotation of the motor. Internal PWM Current Control. Each H-bridge is controlled by a fixed off time PWM current-control circuit that limits the load current to a desired value (ITRIP). Initially, a diagonal pair of source and sink DMOS outputs are enabled and current flows through the motor winding and RS. When the voltage across the current-sense resistor equals the DAC output voltage, the current-sense comparator resets the PWM latch, which turns off the source driver (slow-decay mode) or the sink and source drivers (fast- or mixed-decay modes). The maximum value of current limiting is set by the selection of RS and the voltage at the VREF input with a transconductance function approximated by: ITRIPmax = VREF/8RS The DAC output reduces the VREF output to the current-sense comparator in precise steps (see table 2 for % ITRIPmax at each step). ITRIP = (% ITRIPmax/100) x ITRIPmax It is critical to ensure that the maximum rating (0.5 V) on the SENSE terminal is not exceeded. For full-step mode, VREF can be applied up to the maximum rating of VDD, because the peak sense value is 0.707 x VREF/8. In all other modes VREF should not exceed 4 V. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR Functional Description (cont’d) Fixed Off-Time. The internal PWM current-control circuitry uses a one shot to control the time the driver(s) remain(s) off. The one shot off-time, toff, is determined by the selection of an external resistor (RT) and capacitor (CT) connected from the RC timing terminal to ground. The off time, over a range of values of CT = 470 pF to 1500 pF and RT = 12 kΩ to 100 kΩ is approximated by: toff = RTCT RC Blanking. In addition to the fixed off time of the PWM control circuit, the CT component sets the comparator blanking time. This function blanks the output of the current-sense comparator when the outputs are switched by the internal current-control circuitry. The comparator output is blanked to prevent false over-current detection due to reverse recovery currents of the clamp diodes, and/ or switching transients related to the capacitance of the load. The blank time tBLANK can be approximated by: tBLANK = 1400CT Charge Pump. (CP1 and CP2). The charge pump is used to generate a gate supply greater than VBB to drive the source-side DMOS gates. A 0.22 µF ceramic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.22 µF ceramic capacitor is required between VCP and VBB to act as a reservoir to operate the high-side DMOS devices. VREG. This internally generated voltage is used to operate the sink-side DMOS outputs. The VREG terminal should be decoupled with a 0.22 µF capacitor to ground. VREG is internally monitored and in the case of a fault condition, the outputs of the device are disabled. Enable Input (ENABLE). This active-low input enables all of the DMOS outputs. When logic high the outputs are disabled. Inputs to the translator (STEP, DIRECTION, MS1, MS2) are all active independent of the ENABLE input state. www.allegromicro.com Shutdown. In the event of a fault (excessive junction temperature, or low voltage on VCP) the outputs of the device are disabled until the fault condition is removed. At power up, and in the event of low VDD, the undervoltage lockout (UVLO) circuit disables the drivers and resets the translator to the HOME state. Sleep Mode (SLEEP). An active-low control input used to minimize power consumption when not in use. This disables much of the internal circuitry including the output DMOS, regulator, and charge pump. A logic high allows normal operation and startup of the device in the home position. When coming out of sleep mode, wait 1 ms before issuing a STEP command to allow the charge pump (gate drive) to stabilize. Percent Fast Decay Input (PFD). When a STEP input signal commands a lower output current from the previous step, it switches the output current decay to either slow-, fast-, or mixed-decay depending on the voltage level at the PFD input. If the voltage at the PFD input is greater than 0.6VDD then slow-decay mode is selected. If the voltage on the PFD input is less than 0.21VDD then fast-decay mode is selected. Mixed decay is between these two levels. This terminal should be decoupled with a 0.1 µF capacitor. Mixed Decay Operation. If the voltage on the PFD input is between 0.6VDD and 0.21VDD, the bridge will operate in mixed-decay mode depending on the step sequence (see figures). As the trip point is reached, the device will go into fast-decay mode until the voltage on the RC terminal decays to the voltage applied to the PFD terminal. The time that the device operates in fast decay is approximated by: tFD = RTCTIn (0.6VDD/VPFD) After this fast decay portion, tFD, the device will switch to slow-decay mode for the remainder of the fixed off-time period. 7 3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR Functional Description (cont’d) Synchronous Rectification. When a PWM off cycle is triggered by an internal fixed off-time cycle, load current will recirculate according to the decay mode selected by the control logic. The A3977 synchronous rectification feature will turn on the appropriate MOSFETs during the current decay and effectively short out the body diodes with the low rDS(on) driver. This will reduce power dissipation significantly and eliminate the need for external Schottky diodes for most applications. Active Mode. When the SR input is logic low, active mode is enabled and synchronous rectification will occur. This mode prevents reversal of the load current by turning off synchronous rectification when a zero current level is detected. This prevents the motor winding from conducting in the reverse direction. Disabled Mode. When the SR input is logic high, synchronous rectification is disabled. This mode is typically used when external diodes are required to transfer power dissipation from the A3977 package to the external diodes. The synchronous rectification can be set in either active mode or disabled mode. Timing Requirements (TA = +25°C, VDD = 5 V, Logic Levels are VDD and Ground) STEP 50% C A D B MS1/MS2/ DIR/RESET E SLEEP Dwg. WP-042 A. Minimum Command Active Time Before Step Pulse (Data Set-Up Time) ..... 200 ns B. Minimum Command Active Time After Step Pulse (Data Hold Time) ............ 200 ns C. Minimum STEP Pulse Width ...................... 1.0 µs D. Minimum STEP Low Time ......................... 1.0 µs E. Maximum Wake-Up Time ......................... 1.0 ms 8 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR Applications Information Layout. The printed wiring board should use a heavy ground plane. For optimum electrical and thermal performance, the driver should be soldered directly onto the board. The load supply terminal, VBB, should be decoupled with an electrolytic capacitor (>47 µF is recommended) placed as close to the device as possible. To avoid problems due to capacitive coupling of the high dv/dt switching transients, route the bridge-output traces away from the sensitive logic-input traces. Always drive the logic inputs with a low source impedance to increase noise immunity. Grounding. A star ground system located close to the driver is recommended. The 44-lead PLCC has the analog ground and the power ground internally bonded to the power tabs of the package (leads 44, 1, 2, 11 – 13, 22 – 24, and 33 – 35). Current Sensing. To minimize inaccuracies caused by ground-trace IR drops in sensing the output current level, the current-sense resistor (RS) should have an independent ground return to the star ground of the device. This path should be as short as possible. For low-value sense resistors the IR drops in the printed wiring board sense resistor’s traces can be significant and should be taken into account. The use of sockets should be avoided as they can introduce variation in RS due to their contact resistance. Allegro MicroSystems recommends a value of RS given by RS = 0.5/ITRIPmax Thermal Protection. Circuitry turns off all drivers when the junction temperature reaches 165°C, typically. It is intended only to protect the device from failures due to excessive junction temperatures and should not imply that output short circuits are permitted. Thermal shutdown has a hysteresis of approximately 15°C. On the 28-lead TSSOP package, the analog ground (lead 7) and the power ground (lead 21) must be connected together externally. The copper ground plane located under the exposed thermal pad is typically used as the star ground. www.allegromicro.com 9 3977 MICROSTEPPPING DMOS DRIVER WITH TRANSLATOR Table 2. Step Sequencing Home State = 45º Step Angle, DIR = H Full Step Half Step ¼ Step ⅛ Step Phase 1 Current (%Itripmax) (%) 1 1 1 100.00 0.00 0.0 2 98.08 19.51 11.3 3 92.39 38.27 22.5 4 83.15 55.56 33.8 5 70.71 70.71 45.0 6 55.56 83.15 56.3 7 38.27 92.39 67.5 8 19.51 98.08 78.8 9 0.00 100.00 90.0 10 –19.51 98.08 101.3 11 –38.27 92.39 112.5 12 –55.56 83.15 123.8 13 –70.71 70.71 135.0 14 –83.15 55.56 146.3 15 –92.39 38.27 157.5 16 –98.08 19.51 168.8 17 –100.00 0.00 180.0 18 –98.08 –19.51 191.3 19 –92.39 –38.27 202.5 20 –83.15 –55.56 213.8 21 –70.71 –70.71 225.0 22 –55.56 –83.15 236.3 23 –38.27 –92.39 247.5 24 –19.51 –98.08 258.8 25 0.00 –100.00 270.0 26 19.51 –98.08 281.3 27 38.27 –92.39 292.5 28 55.56 –83.15 303.8 29 70.71 –70.71 315.0 30 83.15 –55.56 326.3 31 92.39 –38.27 337.5 32 98.08 –19.51 348.8 2 1 2 3 4 3 5 6 2 4 7 8 5 9 10 3 6 11 12 7 13 14 4 8 15 16 10 Phase 2 Current (%Itripmax) (%) 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Step Angle (º) 3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR Full-Step Operation MS1 = MS2 = L, DIR = H STEP INPUT HOME OUTPUT SLOW DECAY 70.7% PHASE 1 CURRENT –70.7% SLOW DECAY 70.7% PHASE 2 CURRENT –70.7% Dwg. WK-004-15 The vector addition of the output currents at any step is 100%. www.allegromicro.com 11 3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR Half-Step Operation MS1 = H, MS2 = L, DIR = H STEP INPUT SLOW DECAY MIXED DECAY SLOW DECAY MIXED DECAY SLOW DECAY MIXED DECAY SLOW DECAY MIXED DECAY MIXED DECAY SLOW DECAY MIXED DECAY SLOW DECAY MIXED DECAY SLOW DECAY MIXED DECAY SLOW DECAY HOME OUTPUT 100% 70.7% PHASE 1 CURRENT –70.7% –100% 100% 70.7% PHASE 2 CURRENT –70.7% –100% Dwg. WK-004-14 The mixed-decay mode is controlled by the percent fast decay voltage (VPFD). If the voltage at the PFD input is greater than 0.6VDD then slow-decay mode is selected. If the voltage on the PFD input is less than 0.21VDD then fast-decay mode is selected. Mixed decay is between these two levels. 12 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR Quarter-Step Operation MS1 = L, MS2 = H, DIR = H STEP INPUT HOME OUTPUT SLOW DECAY MIXED DECAY SLOW DECAY MIXED DECAY 100% 70.7% 38.3% PHASE 1 CURRENT –38.3% –70.7% –100% MIXED DECAY SLOW DECAY MIXED DECAY SLOW DECAY 100% 70.7% 38.3% PHASE 2 CURRENT –38.3% –70.7% –100% Dwg. WK-004-13 The mixed-decay mode is controlled by the percent fast decay voltage (VPFD). If the voltage at the PFD input is greater than 0.6VDD then slow-decay mode is selected. If the voltage on the PFD input is less than 0.21VDD then fast-decay mode is selected. Mixed decay is between these two levels. www.allegromicro.com 13 3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR 8 Microstep/Step Operation MS1 = MS2 = H, DIR = H STEP INPUT HOME OUTPUT SLOW DECAY MIXED DECAY SLOW DECAY MIXED DECAY 100% 70.7% 38.3% PHASE 1 CURRENT –38.3% –70.7% –100% MIXED DECAY SLOW DECAY MIXED DECAY SLOW DECAY 100% 70.7% 38.3% PHASE 2 CURRENT –38.3% –70.7% –100% Dwg. WK-004-12 The mixed-decay mode is controlled by the percent fast decay voltage (VPFD). If the voltage at the PFD input is greater than 0.6VDD then slow-decay mode is selected. If the voltage on the PFD input is less than 0.21VDD then fast-decay mode is selected. Mixed decay is between these two levels. 14 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR Terminal List Terminal Name GND SENSE1 HOME DIR OUT1A NC PFD RC1 GND AGND REF RC2 LOGIC SUPPLY NC OUT2A MS2 MS1 SENSE2 GND LOAD SUPPLY2 SR RESET OUT2B NC STEP VREG PGND GND VCP CP1 CP2 NC OUT1B ENABLE SLEEP LOAD SUPPLY1 Terminal Description Analog and power ground Sense resistor for bridge 1 Logic output Logic Input DMOS H bridge 1 output A No (internal) connection Mixed decay setting Analog Input for fixed offtime – bridge 1 Analog and power ground Analog ground Gm reference input Analog input for fixed offtime – bridge 2 VDD, the logic supply voltage No (internal) connection DMOS H bridge 2 output A Logic input Logic input Sense resistor for bridge 2 Analog and power ground VBB2, the load supply for bridge 2 Logic input Logic input DMOS H bridge 2 output B No (internal) connection Logic input Regulator decoupling Power ground Analog and power ground Reservoir capacitor Charge pump capacitor Charge pump capacitor No (internal) connection DMOS H bridge 1 output B Logic input Logic input VBB1, the load supply for bridge 1 A3977xLP (TSSOP) – 1 2 3 4 – 5 6 – 7* 8 9 10 – 11 12 13 14 – 15 16 17 18 – 19 20 21* – 22 23 24 – 25 26 27 28 A3977xED (PLCC) 44, 1, 2 3 4 5 6 7, 8 9 10 11, 12, 13 – 14 15 16 17 18 19 20 21 22, 23, 24 25 26 27 28 29, 30 31 32 – 33, 34, 35 36 37 38 39 40 41 42 43 * AGND and PGND on the TSSOP package must be connected together externally. www.allegromicro.com 15 3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR A3977xED 18 28 29 17 0.032 0.026 0.319 0.291 0.695 0.685 0.021 0.013 Dimensions in Inches (controlling dimensions) 0.656 0.650 INDEX AREA 0.319 0.291 0.050 BSC 39 7 40 0.020 44 1 2 6 0.656 0.650 MIN 0.695 0.685 0.180 0.165 Dwg. MA-005-44A in 28 18 29 17 0.812 0.661 8.10 7.39 17.65 17.40 0.533 0.331 Dimensions in Millimeters (for reference only) 16.662 16.510 INDEX AREA 8.10 7.39 1.27 BSC 39 7 40 0.51 MIN 4.57 4.20 44 1 2 6 16.662 16.510 17.65 17.40 Dwg. MA-005-44A mm NOTES: 1. 2. 3. 4. 16 Exact body and lead configuration at vendor’s option within limits shown. Lead spacing tolerance is non-cumulative. Webbed lead frame. Terminals 1, 2, 11, 12, 13, 22, 23, 24, 33, 34, 35, and 44 are internally one piece. Supplied in standard sticks/tubes of 27 devices or add “TR” to part number for tape and reel. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR A3977xLP 0.197 28 15 0.0394 REF 0.118 0.177 0.169 0.0098 BSC INDEX AREA GAUGE PLANE SEATING PLANE 0.012 0.0075 1 2 0.030 0.018 0° TO 8° 0.026 3 Dimensions in Inches (for reference only) BSC 0.386 0.378 0.260 0.244 0.0079 0.0035 0.0472 MAX 0.0059 0.00 EXPOSED THERMAL PAD 5.0 28 Dwg. MA-008-30A in 15 1.00 REF 3.0 4.50 4.30 0.25 BSC INDEX AREA GAUGE PLANE SEATING PLANE 0.30 0.19 1 2 9.80 9.60 0.75 0.45 0° TO 8° 0.65 3 BSC Dimensions in Millimeters (controlling dimensions) 6.60 6.20 0.20 0.09 1.20 MAX 0.15 0.00 EXPOSED THERMAL PAD Dwg. MA-008-30A mm NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Supplied in standard sticks/tubes of 49 devices or add “TR” to part number for tape and reel. www.allegromicro.com 17 3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATOR The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. 18 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000