AS7C33128FT18B December 2004 ® 3.3V 128K × 18 Flow Through Synchronous SRAM Features • • • • • • • • • • • • • Organization: 131,072 words × 18 bits Fast clock to data access: 6.5/7.5/8.0/10.0 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow through operation Asynchronous output enable control Economical 100-pin TQFP package Individual byte write and Global write Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Linear or interleaved burst control Snooze mode for reduced power standby Common data inputs and data outputs Logic block diagram LBO CLK CS CLR CLK ADV ADSC ADSP 17 A[16:0] Burst logic Q D CS Address register 2 2 17 128K × 18 Memory array 15 17 CLK 18 GWE BWb D DQb 18 Q Byte Write registers BWE CLK D DQa Q BWa 2 Byte Write registers CLK CE0 CE1 CE2 D Enable register OE Q Output Buffers CE CLK ZZ Power down Input registers CLK D Enable Q delay register CLK OE 18 DQ [a,b] Selection guide –65 -75 -80 -10 Units Minimum cycle time 7.5 8.5 10 12 ns Maximum clock access time 6.5 7.5 8.0 10.0 ns Maximum operating current 250 225 200 175 mA Maximum standby current 120 100 90 90 mA Maximum CMOS standby current (DC) 30 30 30 30 mA 12/10/04; v.1.3 Alliance Semiconductor P. 1 of 19 Copyright © Alliance Semiconductor. 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AS7C33128FT18B ® 2 Mb Synchronous SRAM products list1,2 Org 128KX18 64KX32 Part Number AS7C33128PFS18B AS7C3364PFS32B Mode PL-SCD PL-SCD Speed 200/166/133 MHz 200/166/133 MHz 64KX36 128KX18 64KX32 64KX36 128KX18 64KX32 64KX36 AS7C3364PFS36B AS7C33128PFD18B AS7C3364PFD32B AS7C3364PFD36B AS7C33128FT18B AS7C3364FT32B AS7C3364FT36B PL-SCD PL-DCD PL-DCD PL-DCD FT FT FT 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns 1 Core Power Supply: VDD = 3.3V + 0.165V 2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O VDDQ = 2.5V + 0.125V for 2.5V I/O PL-SCD PL-DCD FT 12/10/04; v.1.3 : : : Pipelined Burst Synchronous SRAM - Single Cycle Deselect Pipelined Burst Synchronous SRAM - Double Cycle Deselect Flow-through Burst Synchronous SRAM Alliance Semiconductor P. 2 of 19 AS7C33128FT18B ® 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE0 CE1 NC NC BWb BWa CE2 VDD VSS CLK GWE BWE OE ADSC ADSP ADV A A Pin arrangement TQFP 14 × 20mm 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSSQ NC DQpa DQa7 DQa6 VSSQ VDDQ DQa5 DQa4 VSS NC VDD ZZ DQa3 DQa2 VDDQ VSSQ DQa1 DQa0 NC NC VSSQ VDDQ NC NC NC LBO A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A NC VDDQ VSSQ NC NC DQb0 DQb1 VSSQ VDDQ DQb2 DQb3 NC VDD NC VSS DQb4 DQb5 VDDQ VSSQ DQb6 DQb7 DQpb NC VSSQ VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC NC 12/10/04; v.1.3 Alliance Semiconductor P. 3 of 19 AS7C33128FT18B ® Functional description The AS7C33128FT18B is a high-performance CMOS 2-Mbit synchronous Static Random Access Memory (SRAM) device organized as 131,072 words × 18 bits. Fast cycle times of 7.5/8.5/10/12 ns with clock access times (tCD) of 6.5/7.5/8.0/10 ns. Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses. Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data accessed by the current address registered in the address registers by the positive edge of CLK are carried to the data-out buffer. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled low and both address strobes are high. Burst mode is selectable with the LBO input. With LBO unconnected or driven high, burst operations use an interleaved count sequence. With LBO driven low, the device uses a linear count sequence. Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 18 bits regardless of the state of individual BW[a,b] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting BWE and the appropriate individual byte BWn signals. BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are disabled when BWn is sampled LOW regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is incremented internally to the next burst address if BWn and ADV are sampled low. Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP are as follows: • ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC. • WE signals are sampled on the clock edge that samples ADSC low (and ADSP high). • Master chip enable CE0 blocks ADSP, but not ADSC. The AS7C33128FT18B family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V. These devices are available in a 100-pin TQFP package. TQFP capacitance Parameter Symbol Test conditions Min Max Unit Input capacitance CIN* VIN = 0V - 5 pF I/O capacitance CI/O* VOUT = 0V - 7 pF *Guaranteed not tested TQFP thermal resistance Description Thermal resistance (junction to ambient)1 Thermal resistance (junction to top of case)1 Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 Symbol Typical Units 1–layer θJA 40 °C/W 4–layer θJA 22 °C/W θJC 8 °C/W 1 This parameter is sampled 12/10/04; v.1.3 Alliance Semiconductor P. 4 of 19 AS7C33128FT18B ® Signal descriptions Pin Description I/O Properties CLK I CLOCK A,A0,A1 I SYNC Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted. DQ[a,b] I/O SYNC Data. Driven as output when the chip is enabled and when OE is active. CE0 I SYNC Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive, ADSP is blocked. Refer to the “Synchronous truth table” for more information. CE1, CE2 I SYNC Synchronous chip enables, active high, and active low, respectively. Sampled on clock edges when ADSC is active or when CE0 and ADSP are active. ADSP I SYNC Address strobe processor. Asserted low to load a new address or to enter standby mode. ADSC I SYNC Address strobe controller. Asserted low to load a new address or to enter standby mode. ADV I SYNC Advance. Asserted low to continue burst read/write. GWE I SYNC Global write enable. Asserted low to write all 18 bits. When high, BWE and BW[a,b] control write enable. BWE I SYNC Byte write enable. Asserted low with GWE high to enable effect of BW[a,b] inputs. BW[a,b] I SYNC Write enables. Used to control write of individual bytes when GWE is high and BWE is low. If any of BW[a,b] is active with GWE high and BWE low, the cycle is a write cycle. If all BW[a,b] are inactive, the cycle is a read cycle. OE I ASYNC Asynchronous output enable. I/O pins are driven when OE is active and chip is in read mode. LBO I STATIC Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When driven Low, device follows linear Burst order. This signal is internally pulled High. ZZ I ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused. NC - - Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock. No connect Snooze Mode SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of SNOOZE MODE is dictated by the length of time the ZZ is in a High state. The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE. When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete. Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE. 12/10/04; v.1.3 Alliance Semiconductor P. 5 of 19 AS7C33128FT18B ® Write enable truth table (per byte) Function GWE BWE BWa BWb L X X X H L L L Write Byte a H L L H Write Byte b H L H L H H X X H L H H Write All Bytes Read Key: X = don’t care, L = low, H = high, n = a, b; BWE, BWn = internal write signal. Asynchronous Truth Table Operation Snooze mode ZZ H L L L L Read Write Deselected OE X L H X X I/O Status High-Z Dout High-Z Din, High-Z High-Z Notes: 1. X means “Don’t Care” 2. ZZ pin is pulled down internally 3. For write cycles that follows read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 4. Snooze mode means power down state of which stand-by current does not depend on cycle times 5. Deselected means power down state of which stand-by current depends on cycle times Burst sequence table Interleaved burst address (LBO = 1) A1 A0 st A1 A0 A1 A0 Linear burst address (LBO = 0) A1 A0 st A1 A0 A1 A0 A1 A0 A1 A0 1 Address 00 01 10 11 1 Address 00 01 10 11 2nd Address 01 00 11 10 2nd Address 01 10 11 00 10 11 00 01 11 10 01 10 3rd Address 10 11 00 01 3rd Address 4th Address 11 10 01 00 4th Address 12/10/04; v.1.3 Alliance Semiconductor P. 6 of 19 AS7C33128FT18B ® Synchronous truth table CE01 CE1 CE2 ADSP ADSC H L L L L L L L L X X X X H H H H L X H X H X L L X X H H H H X X X X X X X X H X X X X X X X H H L L L L X X X X X X X X L X X X X X L H L H L L H H H H H H X X X X H H X H X L X L X L X X L L H H H H H H H H L H H H H ADV WRITE X X X X X X X X X L L H H L L H H X L L H H X X X X X X X H H H H H H H H H H L L L L L OE Address accessed CLK Operation DQ X X X X X L H L H L H L H L H L H X X X X X NA NA NA NA NA External External External External Next Next Current Current Next Next Current Current External Next Next Current Current L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H Deselect Deselect Deselect Deselect Deselect Begin read Begin read Begin read Begin read Continue read Continue read Suspend read Suspend read Continue read Continue read Suspend read Suspend read Begin write Continue write Continue write Suspend write Suspend write Hi−Z Hi−Z Hi−Z Hi−Z Hi−Z Q Hi−Z Q Hi−Z Q Hi−Z Q Hi−Z Q Hi−Z Q Hi−Z D3 D D D D 1 X = don’t care, L = low, H = high 2 For WRITE, L means any one or more byte write enable signals (BWa or BWb) and BWE are LOW or GWE is LOW. WRITE = HIGH for all BWx, BWE, GWE HIGH. See "Write enable truth table (per byte)," on page 6 for more information. 3 For write operation following a READ, OE must be high before the input data set up time and held high throughout the input hold time 4 ZZ pin is always Low. 12/10/04; v.1.3 Alliance Semiconductor P. 7 of 19 AS7C33128FT18B ® . Absolute maximum ratings1 Parameter Power supply voltage relative to GND Input voltage relative to GND (input pins) Input voltage relative to GND (I/O pins) Power dissipation DC output current Storage temperature (plastic) Temperature under bias Symbol VDD, VDDQ VIN VIN PD IOUT Tstg Tbias Min –0.5 –0.5 –0.5 – – –65 –65 Max +4.6 VDD + 0.5 VDDQ + 0.5 1.8 50 +150 +135 Unit V V V W mA °C °C 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability. Recommended operating conditions at 3.3V I/O Parameter Supply voltage for inputs Supply voltage for I/O Ground supply Symbol VDD VDDQ Vss Min 3.135 3.135 0 Nominal 3.3 3.3 0 Max 3.465 3.465 0 Unit V V V Min 3.135 2.375 0 Nominal 3.3 2.5 0 Max 3.465 2.625 0 Unit V V V Recommended operating conditions at 2.5V I/O Parameter Supply voltage for inputs Supply voltage for I/O Ground supply 12/10/04; v.1.3 Symbol VDD VDDQ Vss Alliance Semiconductor P. 8 of 19 AS7C33128FT18B ® DC electrical characteristics for 3.3V I/O operation Parameter Sym Conditions Min Max Unit current† |ILI| VDD = Max, 0V < VIN < VDD -2 2 µA Output leakage current |ILO| OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ -2 2 µA Address and control pins 2* Input high (logic 1) voltage VIH VDD+0.3 I/O pins 2* VDDQ+0.3 Address and control pins -0.3** 0.8 I/O pins -0.5** 0.8 Input leakage Input low (logic 0) voltage V V VIL Output high voltage VOH IOH = –4 mA, VDDQ = 3.135V 2.4 – V Output low voltage VOL IOL = 8 mA, VDDQ = 3.465V – 0.4 V DC electrical characteristics for 2.5V I/O operation Parameter Sym Conditions Min Max Unit Input leakage current† |ILI| VDD = Max, 0V < VIN < VDD -2 2 µA Output leakage current |ILO| OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ -2 2 µA Address and control pins 1.7* VIH VDD+0.3 V Input high (logic 1) voltage I/O pins 1.7* VDDQ+0.3 V Address and control pins -0.3** 0.7 V I/O pins -0.3** 0.7 V Input low (logic 0) voltage VIL Output high voltage VOH IOH = –4 mA, VDDQ = 2.375V 1.7 – V Output low voltage VOL IOL = 8 mA, VDDQ = 2.625V – 0.7 V † LBO and ZZ pins have an internal pull-up or pull-down, and input leakage = ±10 µA. * VIH max < VDD +1.5V for pulse width less than 0.2 X tCYC **V IL min = -1.5 for pulse width less than 0.2 X tCYC IDD operating conditions and maximum limits Parameter Operating power supply current1 Sym ICC ISB Standby power supply current Conditions CE0 < VIL, CE1 > VIH, CE2 < VIL, f = fMax, IOUT = 0 mA, ZZ < VIL All VIN ≤ 0.2V or > VDD – 0.2V, Deselected, f = fMax, ZZ < VIL -65 -75 -80 -10 Unit 250 225 200 175 mA 120 100 90 90 ISB1 Deselected, f = 0, ZZ < 0.2V, all VIN ≤ 0.2V or ≥ VDD – 0.2V 30 30 30 30 ISB2 Deselected, f = fMax, ZZ ≥ VDD – 0.2V, all VIN ≤ VIL or ≥ VIH 30 30 30 30 1 ICC given with no output loading. ICC increases with faster cycle times and greater output loading. 12/10/04; v.1.3 Alliance Semiconductor P. 9 of 19 mA AS7C33128FT18B ® Timing characteristics over operating range –65 Parameter -75 -80 –10 Sym Min Max Min Max Min Max Cycle time tCYC 7.5 – 8.5 – 10 Clock access time tCD – 6.5 – 7.5 Output enable LOW to data valid tOE – 3.5 – Clock HIGH to output Low Z tLZC 2.5 – Data output invalid from clock HIGH tOH 2.5 Output enable LOW to output Low Z tLZOE Output enable HIGH to output High Z Clock HIGH to output High Z Notes 1 Min Max Unit – 12 – ns – 8.0 – 10 ns 3.5 – 4.0 – 4.0 ns 2.5 – 2.5 – 2.5 – ns 2,3,4 – 2.5 – 2.5 – 2.5 – ns 2 0 – 0 – 0 – 0 – ns 2,3,4 tHZOE – 3.0 – 3.5 – 4.0 – 5.0 ns 2,3,4 tHZC – 3.0 – 3.5 – 4.0 – 5.0 ns 2,3,4 tOHOE 0 – 0 – 0 – 0 – ns Clock HIGH pulse width tCH 2.5 – 3.0 – 4.0 – 4.0 – ns 5 Clock LOW pulse width tCL 2.5 – 3.0 – 4.0 – 4.0 – ns 5 Address setup to clock HIGH tAS 1.5 – 2.0 – 2.0 – 2.0 – ns 6 Data setup to clock HIGH tDS 1.5 – 2.0 – 2.0 – 2.0 – ns 6 Write setup to clock HIGH tWS 1.5 – 2.0 – 2.0 – 2.0 – ns 6,7 Chip select setup to clock HIGH tCSS 1.5 – 2.0 – 2.0 – 2.0 – ns 6,8 Address hold from clock HIGH tAH 0.5 – 0.5 – 0.5 – 0.5 – ns 6 Data hold from clock HIGH tDH 0.5 – 0.5 – 0.5 – 0.5 – ns 6 Write hold from clock HIGH tWH 0.5 – 0.5 – 0.5 – 0.5 – ns 6,7 Chip select hold from clock HIGH tCSH 0.5 – 0.5 – 0.5 – 0.5 – ns 6,8 ADV setup to clock HIGH tADVS 1.5 – 2.0 – 2.0 – 2.0 – ns 6 ADSP setup to clock HIGH tADSPS 1.5 – 2.0 – 2.0 – 2.0 – ns 6 ADSC setup to clock HIGH tADSCS 1.5 – 2.0 – 2.0 – 2.0 – ns 6 ADV hold from clock HIGH tADVH 0.5 – 0.5 – 0.5 – 0.5 – ns 6 ADSP hold from clock HIGH tADSPH 0.5 – 0.5 – 0.5 – 0.5 – ns 6 ADSC hold from clock HIGH tADSCH 0.5 – 0.5 – 0.5 – 0.5 – ns 6 Output enable HIGH to invalid output 1 See “Notes” on page 16. Snooze Mode Electrical Characteristics Description Current during Snooze Mode ZZ active to input ignored ZZ inactive to input sampled ZZ active to SNOOZE current ZZ inactive to exit SNOOZE current 12/10/04; v.1.3 Conditions Symbol ZZ > VIH ISB2 tPDS tPUS tZZI tRZZI Alliance Semiconductor Min Max Units 30 mA cycle cycle cycle 2 2 2 0 P. 10 of 19 AS7C33128FT18B ® Key to switching waveforms Rising input Falling input don’t care Undefined Timing waveform of read cycle tCYC tCL tCH CLK tADSPS tADSPH ADSP tADSCS tADSCH ADSC tAS LOAD NEW ADDRESS tAH A1 Address A2 tWS A3 tWH GWE, BWE tCSS tCSH CE0, CE2 CE1 tADVS tADVH ADV ADV inserts wait states OE tOE tHZOE tOH tLZOE Dout Q(A2Ý01) Q(A1) Q(A2Ý10) Q(A2Ý11) Q(A3) Q(A3Ý01) Q(A3Ý10) Q(A3Ý11) tCD Read Q(A1) Suspend Read Q(A1) Read Q(A2) tHZC Burst Burst Read Suspend Burst Burst Burst Burst Read Read Q(A3) Read Read Read Read Read Q(A 2Ý01) Q(A 2Ý10) Q(A 2Ý10) Q(A 2Ý11) Q(A 3Ý01) Q(A 3Ý10) Q(A 3Ý11) DSEL Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. BW[a:d] is don’t care. 12/10/04; v.1.3 Alliance Semiconductor P. 11 of 19 AS7C33128FT18B ® Timing waveform of write cycle tCYC tCL tCH CLK tADSPS tADSPH ADSP tADSCS tADSCH ADSC ADSC LOADS NEW ADDRESS tAS tAH Address A1 A3 A2 tWS tWH BWE BW[a:b] tCSS tCSH CE0, CE2 CE1 tADVS tADVH ADV SUSPENDS BURST ADV OE tDS tDH Din D(A1) Read Q(A1) Suspend Write D(A1) D(A2) Read Q(A2) D(A2Ý01) Suspend Write D(A 2) D(A2Ý01) D(A2Ý10) D(A2Ý11) D(A3) ADV Suspend ADV ADV Burst Write Burst Burst Write D(A 2Ý01) Write Write D(A 2Ý01) D(A 2Ý10) D(A 2Ý11) D(A3Ý01) Write D(A 3) D(A3Ý10) Burst Write D(A 3Ý01) ADV Burst Write D(A 3Ý10) Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. 12/10/04; v.1.3 Alliance Semiconductor P. 12 of 19 AS7C33128FT18B ® Timing waveform of read/write cycle (ADSP Controlled; ADSC High) tCYC tCL tCH CLK tADSPS tADSPH ADSP tAS tAH Address A2 A1 A3 tWS tWH BWE BW[a:b] CE0, CE2 CE1 tADVS tADVH ADV OE tDS tDH Din D(A2) tOE tCD Dout tLZC Q(A1) Read Q(A1) tOH tLZOE tHZOE Q(A3) Suspend Read Q(A1) Read Q(A2) Suspend Write D(A 2) Read Q(A3) Q(A3Ý01) ADV Burst Read Q(A 3Ý01) Q(A3Ý10) ADV Burst Read Q(A 3Ý10) Q(A3Ý11) ADV Burst Read Q(A 3Ý11) Suspend Read Q(A 3Ý11) Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. 12/10/04; v.1.3 Alliance Semiconductor P. 13 of 19 AS7C33128FT18B ® Timing waveform of read/write cycle(ADSC controlled, ADSP = HIGH) tCH tCYC tCL CLK tADSCS tADSCH ADSC tAS ADDRESS A1 A3 A2 A5 A4 A7 A6 tWS BWE BW[a:b] tCSS tAH A8 A9 A10 tWH tCSH CE0,CE2 CE1 OE tCD tOE tLZOE Q(A1) Dout Q(A2) Q(A3) Q(A9) Q(A4) Din D(A5) READ Q(A2) READ Q(A3) READ Q(A4) Q(A10) tDH tDS READ Q(A1) tOH tHZOE D(A6) D(A7) D(A8) WRITE WRITE WRITE WRITE D(A6) D(A7) D(A8) D(A5) READ Q(A9) READ Q(A10) Note: ADV is don’t care here. 12/10/04; v.1.3 Alliance Semiconductor P. 14 of 19 AS7C33128FT18B ® Timing waveform of power down cycle tCH tCYC tCL CLK tADSPS tADSPS ADSP ADSC A2 A1 ADDRESS tWH tWS BWE BW[a:b] tCSS tCSH CE0,CE2 CE1 ADV OE tOE Din tLZOE tHZOE tHZC Dout Q(A2) Q(A1) tPUS tPDS ZZ Recovery Cycle ZZ Q(A2(Ý01)) Normal Operation Mode ZZ Setup Cycle tZZI tRZZI Isupply ISB2 Sleep State READ Q(A1) 12/10/04; v.1.3 READ Q(A2) READ Q(A1Ý01) Alliance Semiconductor READ Q(A2Ý01) P. 15 of 19 AS7C33128FT18B ® AC test conditions • Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C. • Input pulse level: GND to 3V. See Figure A. Thevenin equivalent: • Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A. +3.3V for 3.3V I/O; /+2.5V for 2.5V I/O • Input and output timing reference levels: 1.5V. Z0 = 50Ω +3.0V 90% 10% GND 90% 10% Figure A: Input waveform DOUT 50Ω VL = 1.5V for 3.3V I/O; 30 pF* = V DDQ/2 for 2.5V I/O Figure B: Output load (A) DOUT 353Ω / 1538Ω 319Ω / 1667Ω 5 pF* GND *including scope and jig capacitanc Figure C: Output load (B) Notes 1 For test conditions, see AC Test Conditions, Figures A, B, C. 2 This parameter measured with output load condition in Figure C. 3 This parameter is sampled, but not 100% tested. 4 tHZOE is less than tLZOE; and tHZC is less than tLZC at any given temperature and voltage. 5 tCH measured as HIGH above VIH and tCL measured as LOW below VIL. 6 This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet the setup and hold times for all rising edges of CLK when chip is enabled. 7 Write refers to GWE, BWE, BW[a,b]. 8 Chip select refers to CE0, CE1, CE2 12/10/04; v.1.3 Alliance Semiconductor P. 16 of 19 AS7C33128FT18B ® Package Dimensions 100-pin quad flat pack (TQFP) Hd D L1 L b A1 A2 α e He E TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.90 14.10 E 19.90 20.10 e 0.65 nominal Hd 15.85 16.15 He 21.80 22.20 L 0.45 0.75 L1 α 1.00 nominal 0° 7° Dimensions in millimeters 12/10/04; v.1.3 Alliance Semiconductor P. 17 of 19 AS7C33128FT18B ® Ordering information Package Width TQFP x18 TQFP x18 –65 AS7C33128FT18B65TQC AS7C33128FT18B65TQI -75 AS7C33128FT18B75TQC AS7C33128FT18B75TQI –80 AS7C33128FT18B80TQC AS7C33128FT18B80TQI –10 AS7C33128FT18B10TQC AS7C33128FT18B10TQI Note: Ass suffix ‘N’ to the above part number for Lead Free Parts (Ex. AS7C33128FT18B-65TQCN) Part numbering guide AS7C 1 33 2 128 3 FT 4 18 5 B 6 –XX 7 TQ 8 C/I 9 X 10 1. Alliance Semiconductor SRAM Prefix 2. Operating voltage: 33=3.3V 3. Organization: 128=128K 4. Flowthrough. 5. Organization: 18=x18 6. Production version: B= product revision 7.Clock access time: [-65 = 6.5 ns; -75 = 7.5 ns; -80 = 8.0 ns; -10 = 10.0] 8. Package type: TQ=TQFP 9. Operating temperature: C=Commercial (0° C to 70° C); I=Industrial (-40° C to 85° C) 10. X = Lead free part 12/10/04; v.1.3 Alliance Semiconductor P. 18 of 19 AS7C33128FT18B ® ® Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Part Number: AS7C33128FT18B Document Version: v.1.3 © Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. 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