ASM2P3805X June 2005 rev 0.2 3.3V CMOS Dual 1-To-5 Clock Driver Features Functional Description Advanced CMOS Technology The ASM2P3805X is a 3.3V clock driver built using Guaranteed low skew < 200pS (max) advanced CMOS technology. The device consists of two Very low propagation delay < 2.5nS (max) banks of drivers, each with a 1:5 fanout and its own output Very low duty cycle distortion < 270pS (max) enable control. The device has a "heartbeat" monitor for Very low CMOS power levels diagnostics and PLL driving. The MON output is identical to Operating frequency up to 166MHz all other outputs and complies with the output specifications TTL compatible inputs and outputs in this document. The ASM2P3805X offers low capacitance Inputs can be driven from 3.3V or 5V components inputs. The ASM2P3805X is designed for high speed clock Two independent output banks with 3-state control distribution where signal quality and skew are critical. The 1:5 fanout per bank ASM2P3805X also allows single point-to-point transmission ASM2P3805X line driving in applications such as address distribution, Where X =D for 133MHz Operation where one signal must be distributed to multiple receivers X =E for 166MHz Operation with low skew and high signal quality. "Heartbeat" monitor output VCC = 3.3V ± 0.3V Available in SSOP and QSOP Packages Pin Diagram Block Diagram OEA INA INB 5 5 OA1 – OA5 OB1 – OB5 OEB MON VCCA 1 OA1 2 OA2 3 OA3 4 GNDA 5 OA4 6 OA5 7 GNDQ 8 OEA INA 20 VCCB 19 OB1 18 OB2 17 OB3 16 GNDB 15 OB4 14 OB5 13 MON 9 12 OEB 10 11 INB A S M 2 P 3 8 0 5 X Alliance Semiconductor 2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com Notice: The information in this document is subject to change without notice. ASM2P3805X June 2005 rev 0.2 Pin Description Pin # Pin Names 9,12 ¯¯ B OE ¯¯ A, OE 10,11 INA, INB Clock Inputs 2,3,4,6,7 OA1-OA5 Clock Outputs from Bank A 19,18,17,15,14 OB1-OB5 Clock Outputs from Bank B 1 VCCA Power supply for Bank A 20 VCCB Power supply for Bank B 5 GNDA Ground for Bank A 16 GNDB Ground for Bank B 8 GNDQ Ground 13 MON Monitor Output Description 3-State Output Enable Inputs (Active LOW) Function Table1 Inputs Outputs OE ¯¯ A, OE ¯¯ B INA, INB OAn, OBn MON L L L L L H H H H L Z L H H Z H Note: 1 H = HIGH; L = LOW; Z = High-Impedance Capacitance (TA = +25°C, f = 1.0MHz) Symbol Parameter1 Conditions Typ Max Unit CIN Input Capacitance VIN= 0V 3 4 pF COUT Output Capacitance VOUT = 0V — 6 pF Note: 1 This parameter is measured at characterization but not tested. 3.3V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 2 of 12 ASM2P3805X June 2005 rev 0.2 Absolute Maximum Ratings1 Symbol Max Unit Input Power Supply Voltage -0.5 to +4.6 V VI Input Voltage -0.5 to +5.5 V VO Output Voltage -0.5 to VCC+0.5 V TJ Junction Temperature 150 °C TSTG Storage Temperature -65 to +165 °C 2 KV VCC TDV Description Static Discharge Voltage (As per JEDEC STD 22- A114-B) Note: 1 These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. DC Electrical Characteristics over Operating Range Following Conditions Apply Unless Otherwise Specified Industrial: TA = -40°C to +85°C, VCC = 3.3V ± 0.3V Symbol Test Conditions1 Parameter Min Typ2 Max Unit VIH Input HIGH Level 2 - 5.5 V VIL Input LOW Level -0.5 - 0.8 V IIH Input HIGH Current VCC= Max. VI = 5.5V - - ±1 IIL Input LOW Current VCC= Max. VI = GND - - ±1 VO = VCC - - ±1 VO = GND - - ±1 IOZH IOZL VIK High Impedance Output Current (3-State Outputs Pins) VCC= Max. Clamp Diode Voltage VCC= Min., IIN = –18mA µA - -0.7 -1.2 V 3,4 IODH Output HIGH Current VCC= 3.3V, VIN = VIH or VIL, VO = 1.5V -45 -74 -180 mA IODL Output LOW Current VCC= 3.3V, VIN = VIH or VIL, VO = 1.5V3,4 50 90 200 mA -60 -135 -240 mA IOL= 12mA 2.45 3 - IOH= –8mA 5 2.4 3 - VCC - 0.2 - - IOL= 12mA - 0.3 0.4 IOL= 8mA - 0.2 0.4 IOL= 100µA - - 0.2 IOS VOH Short Circuit Current Output HIGH Voltage 3,4 VCC= Max., VO = GND VCC= Min. VIN = VIH or VIL IOH= –100µA VOL Output LOW Voltage VCC= Min. VIN = VIH or VIL V V Notes: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, 25°C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = VCC -0.6V at rated current. 3.3V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 3 of 12 ASM2P3805X June 2005 rev 0.2 Power Supply Characteristics Symbol Parameter Test Conditions1 Min Typ2 Max Unit ICCL ICCH ICCZ Quiescent Power Supply Current VCC = Max. VIN = GND or VCC - 0.1 30 µA ∆ICC Power Supply Current per Input HIGH VCC = Max. VIN = VCC –0.6V - 45 300 µA VIN = VCC VIN = GND - 80 120 µA/MHz VIN = VCC VIN = GND - 125 150 VIN = VCC –0.6V VIN = GND - 125 150 VIN = VCC VIN = GND - 155 195 VIN = VCC –0.6V VIN= GND - 160 195 ICCD IC VCC= Max. Dynamic Power Supply CL= 15pF 3 Current per Output All Outputs Toggling Total Power Supply 4 Current VCC= Max. CL= 15pF All Outputs Toggling fi = 133MHz VCC= Max. CL= 15pF All Outputs Toggling fi = 166MHz mA Notes: 1. For conditions shown as Max or Min, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. 4. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fONO) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ∆ICC = Power Supply Current for a TTL High Input (VIN = VCC -0.6V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fO = Output Frequency NO = Number of Outputs at fO 3.3V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 4 of 12 ASM2P3805X June 2005 rev 0.2 Switching Characteristics Over Operating Range – ASM2P3805D3,4 Min2 Max Unit Propagation Delay INA to OAn, INB to OBn 1 3 nS tR Output Rise Time (Measured from 0.8V to 2V) - 1.5 nS tF Output Fall Time (Measured from 2V to 0.8V) - 1.5 nS tSK(O) Same device output pin to pin skew5 - 270 pS tSK(P) Pulse skew6,9 - 270 pS tSK(PP) Part to part skew7 - 550 pS tPZL tPZH Output Enable Time ¯¯ B to OBn ¯¯ A to OAn, OE OE - 5.2 nS tPLZ tPHZ Output Disable Time ¯¯ B to OBn ¯¯ A to OAn, OE OE - 5.2 nS fMAX Input Frequency - 133 MHz Min2 Max Unit 0.5 2.5 nS Symbol tPLH tPHL Parameter Conditions1 CL= 15pF f≤133MHz Switching Characteristics Over Operating Range – ASM2P3805E3,4 Symbol tPLH tPHL Parameter Conditions1,8 Propagation Delay INA to OAn, INB to OBn tR Output Rise Time (Measured from 0.7V to 1.7V) - 1 nS tF Output Fall Time (Measured from 1.7V to 0.7V) - 1 nS tSK(O) Same device output pin to pin skew5 - 200 pS tSK(P) Pulse skew6,9 - 270 pS tSK(PP) Part to part skew7 - 550 pS tPZL tPZH Output Enable Time ¯¯ A to OAn, OE ¯¯ B to OBn OE - 5.2 nS tPLZ tPHZ Output Disable Time ¯¯ B to OBn ¯¯ A to OAn, OE OE - 5.2 nS fMAX Input Frequency - 166 MHz CL= 15pF f ≤166MHz Notes: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. tPLH , tPHL and tSK(O) are production tested. All other parameters guaranteed but not production tested. 4. Propagation delay range indicated by Min and Max limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew. 5. Skew measured between all outputs under identical transitions and load conditions. 6. Skew measured is difference between propagation delay times tPHL and tPLH of same outputs under identical load conditions. 7. Part to part skew for all outputs given identical transitions and load conditions at identical VCC levels and temperature. 8. Airflow of 1m/s is recommended for frequencies above 133MHz. 9. This parameter is measured using f = 1MHz. 3.3V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 5 of 12 ASM2P3805X June 2005 rev 0.2 Test Circuits and Waveforms Switch Position Test Conditions Test Switch Disable Low Enable Low 6V Disable High Enable High GND Symbol VCC = 3.3V ±0.3V Unit CL 15 pF RT ZOUT of pulse generator Ω RL 33 Ω t R / tF 1 (0V to 3V or 3V to 0V) nS Definitions: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. tR / tF = Rise/Fall time of the input stimulus from the Pulse Generator. 3.3V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 6 of 12 ASM2P3805X June 2005 rev 0.2 Test Circuits and Waveforms 3.3V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 7 of 12 ASM2P3805X June 2005 rev 0.2 Package Information 20-lead SSOP ( 150 mil ) Package Dimensions Symbol Inches Min Max Millimeters Min Max A 0.053 0.069 1.346 1.753 A1 0.004 0.010 0.102 0.254 A2 …. 0.059 …. 1.499 D 0.337 0.344 8.560 8.738 c 0.007 0.012 0.178 0.274 E 0.228 0.244 5.791 6.198 E1 0.150 0.157 3.810 3.988 L 0.016 0.035 0.406 0.890 L1 0.010 BASIC 0.254 BASIC b 0.203 0.325 0.008 0.014 R1 0.003 …. 0.08 ….. a 0° 8° 0° 8° e 0.025 BASIC 0.635 BASIC 3.3V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 8 of 12 ASM2P3805X June 2005 rev 0.2 20-lead QSOP Package Symbol Dimensions Inches Millimeters Min Max Min Max A 0.060 0.068 1.52 1.73 A1 0.004 0.008 0.10 0.20 b 0.009 0.012 0.23 0.30 c 0.007 0.010 0.18 0.25 D 0.337 0.344 8.56 8.74 E 0.150 0.157 3.81 3.99 e 0.025 BSC 0.64 BSC H 0.230 0.244 5.84 6.20 h 0.010 0.016 0.25 0.41 L 0.016 0.035 0.41 0.89 S 0.056 0.060 1.42 1.52 a 0° 8° 0° 8° 3.3V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 9 of 12 ASM2P3805X June 2005 rev 0.2 Ordering Information Part Number Marking Package Type Temperature ASM2P3805DG-20-AR 2P3805DG 20-Pin SSOP, TAPE & REEL, Green Commercial ASM2P3805DG-20-AT 2P3805DG 20-Pin SSOP, TUBE, Green Commercial ASM2P3805DG-20-DR 2P3805DG 20-Pin QSOP, TAPE & REEL, Green Commercial ASM2P3805DG-20-DT 2P3805DG 20-Pin QSOP, TUBE, Green Commercial ASM2I3805DG-20-AR 2I3805DG 20-Pin SSOP, TAPE & REEL, Green Industrial ASM2I3805DG-20-AT 2I3805DG 20-Pin SSOP, TUBE, Green Industrial ASM2I3805DG-20-DR 2I3805DG 20-Pin QSOP, TAPE & REEL, Green Industrial ASM2I3805DG-20-DT 2I3805DG 20-Pin QSOP, TUBE, Green Industrial ASM2P3805EG-20-AR 2P3805EG 20-Pin SSOP, TAPE & REEL, Green Commercial ASM2P3805EG-20-AT 2P3805EG 20-Pin SSOP, TUBE, Green Commercial ASM2P3805EG-20-DR 2P3805EG 20-Pin QSOP, TAPE & REEL, Green Commercial ASM2P3805EG-20-DT 2P3805EG 20-Pin QSOP, TUBE, Green Commercial ASM2I3805EG-20-AR 2I3805EG 20-Pin SSOP, TAPE & REEL, Green Industrial ASM2I3805EG-20-AT 2I3805EG 20-Pin SSOP, TUBE, Green Industrial ASM2I3805EG-20-DR 2I3805EG 20-Pin QSOP, TAPE & REEL, Green Industrial ASM2I3805EG-20-DT 2I3805EG 20-Pin QSOP, TUBE, Green Industrial 3.3V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 10 of 12 ASM2P3805X June 2005 rev 0.2 Device Ordering Information A S M 2 P 3 8 0 5 D G - 2 0 - A T R = Tape & reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 3.3V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 11 of 12 ASM2P3805X June 2005 rev 0.2 Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Part Number: ASM2P3805X Document Version: 0.2 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003 © Copyright 2003 Alliance Semiconductor Corporation. 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