CED6060R/CEU6060R Feb. 2003 N-Channel Logic Level Enhancement Mode Field Effect Transistor FEATURES 6 60V , 30A , RDS(ON)=25m Ω @VGS=10V. Super high dense cell design for extremely low RDS(ON). D High power and current handling capability. TO-251 & TO-252 package. G D G S CEU SERIES TO-252AA(D-PAK) G D S CED SERIES TO-251(l-PAK) S ABSOLUTE MAXIMUM RATINGS (Tc=25 C unless otherwise noted) Parameter Symbol Limit Unit Drain-Source Voltage VDS 60 V Gate-Source Voltage VGS ĆȀ20 V Drain Current-Continuous @TJ=125 C -Pulsed ID 30 A IDM 120 A Drain-Source Diode Forward Current IS 30 A Maximum Power Dissipation @Tc=25 C Derate above 25 C PD 50 0.3 W W/ C TJ, TSTG -55 to 175 C Thermal Resistance, Junction-to-Case RįJC 3 C/W Thermal Resistance, Junction-to-Ambient RįJA 50 C/W Operating and Storage Temperature Range THERMAL CHARACTERISTICS 6-42 CED6060R/CEU6060R ELECTRICAL CHARACTERISTICS (TC=25 C unless otherwise noted) Parameter Condition Symbol Min Typ Max Unit a DRAIN-SOURCE AVALANCHE RATING Single Pulse Drain-Source Avalanche Energy EAS Maximum Drain-Source Avalanche Current IAS VDD =25V, L = 25µH RG =25 Ω 200 mJ 30 A OFF CHARACTERISTICS Drain-Source Breakdown Voltage BVDSS VGS = 0V, ID = 250µA Zero Gate Voltage Drain Current IDSS VDS = 60V, VGS = 0V Gate-Body Leakage IGSS VGS =Ć20V, VDS = 0V Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250µA Drain-Source On-State Resistance RDS(ON) VGS = 10V, ID = 24A On-State Drain Current ID(ON) gFS VGS = 10V, VDS = 10V VDS = 10V, ID = 24A 20 tD(ON) VDD = 30V, ID = 30A, VGS = 10V, RGEN= 7.5Ω 15 60 V 25 µA Ć100 nA 4 V 25 mΩ ON CHARACTERISTICS a Forward Transconductance SWITCHING CHARACTERISTICS Turn-On Delay Time Rise Time Turn-Off Delay Time 2 A 60 S b tr tD(OFF) 20 ns 250 300 ns 45 60 ns Fall Time tf 130 150 ns Total Gate Charge Qg 36 43 nC Gate-Source Charge Qgs Gate-Drain Charge Qgd VDS =48V, ID = 30A, VGS =10V 6-43 9 nC 19 nC 6 CED6060R/CEU6060R ELECTRICAL CHARACTERISTICS (TC=25 C unless otherwise noted) Parameter Min Typ Max Unit Condition Symbol DYNAMIC CHARACTERISTICSb CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS VDS =25V, VGS = 0V f =1.0MHZ 1178 PF 428 PF 95 PF DRAIN-SOURCE DIODE CHARACTERISTICS b Diode Forward Voltage VGS = 0V, Is =24A VSD 1.3 0.9 Notes a.Pulse Test:Pulse Width ś300ijs, Duty Cycle ś 2%. b.Guaranteed by design, not subject to production testing. 40 40 VGS=10,8,7V 35 TJ=125 C 6V 25 C 30 ID, Drain Current (A) ID, Drain Current(A) 6 Input Capacitance 25 VGS=5V 20 15 4V 10 5 30 20 10 -55 C 0 0 0 0.5 1.0 1.5 2.0 2.5 3.0 2 3 4 5 6 7 8 VDS, Drain-to-Source Voltage (V) VGS, Gate-to-Source Voltage (V) Figure 1. Output Characteristics Figure 2. Transfer Characteristics 6-44 V CED6060R/CEU6060R 1800 RDS(ON), Normalized Drain-Source On-Resistance 3.0 C, Capacitance (pF) 1500 Ciss 1200 900 600 Coss 300 Crss 0 2.0 Tj=125 C 1.5 25 C 1.0 10 15 20 25 -55 C 0.5 0 0 30 0 10 30 40 ID, Drain Current(A) Figure 3. Capacitance Figure 4. On-Resistance Variation with Drain Current and Temperature 1.15 VDS=VGS ID=250ijA 1.10 1.05 1.0 0.95 0.90 0.85 0.80 -50 -25 0 25 50 75 100 125 150 50 1.15 1.10 ID=250ijA 1.05 1.00 0.95 0.90 0.85 -50 -25 0 25 50 75 100 125 150 Tj, Junction Temperature ( C) Tj, Junction Temperature ( C) Figure 6. Breakdown Voltage Variation with Temperature Figure 5. Gate Threshold Variation with Temperature 100 50 40 Is, Source-drain current (A) gFS, Transconductance (S) 20 VDS, Drain-to Source Voltage (V) BVDSS, Normalized Drain-Source Breakdown Voltage Vth, Normalized Gate-Source Threshold Voltage VGS=10V 2.5 30 20 10 VDS=10V 0 0 10 20 30 10 1 0.4 40 IDS, Drain-Source Current (A) 0.6 0.8 1.0 1.2 1.4 VSD, Body Diode Forward Voltage (V) Figure 7. Transconductance Variation with Drain Current 6-45 Figure 8. Body Diode Forward Voltage Variation with Source Current 6 CED6060R/CEU6060R 6 300 VDS=48V ID=30A 12 100 ID, Drain Current (A) VGS, Gate to Source Voltage (V) 15 9 6 3 R 12 18 24 30 36 42 it 10 10 0ij ij s s s 10 ms 10 0m DC s 10 VGS=10V Single Pulse Tc=25 C 1 6 Lim 1m 0 0 D S( ) ON 1 48 10 Qg, Total Gate Charge (nC) 60 100 VDS, Drain-Source Voltage (V) Figure 10. Maximum Safe Operating Area Figure 9. Gate Charge VDD t on RL V IN D tf 90% 90% VOUT VOUT VGS RGEN toff td(off) tr td(on) 10% INVERTED 10% G 90% S VIN 50% 50% 10% PULSE WIDTH Figure 12. Switching Waveforms Figure 11. Switching Test Circuit r(t),Normalized Effective Transient Thermal Impedance 2 1 D=0.5 0.2 0.1 0.1 PDM 0.05 t1 t2 0.02 0.01 1. RįJA (t)=r (t) * RįJA 2. RįJA=See Datasheet 3. TJM-TA = PDM* RįJA (t) 4. Duty Cycle, D=t1/t2 Single Pulse 0.01 0.01 0.1 1 10 100 1000 Square Wave Pulse Duration (msec) Figure 13. Normalized Thermal Transient Impedance Curve 6-46 10000