TI OPA2835ID

OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
Ultra Low-Power, Rail-to-Rail Out, Negative Rail In, VFB Op Amp
Check for Samples: OPA835, OPA2835
FEATURES
DESCRIPTION
•
Fabricated using the industry-leading BiCom-3x
(SiGe complimentary bipolar) process, the OPA835
and OPA2835 are single and dual ultra low-power,
rail-to-rail output, negative rail input, voltage-feedback
operational amplifiers designed to operate over a
power supply range of 2.5V to 5.5V Single Supply
and ±1.25V to ±2.75V dual supply. Consuming only
250µA per channel and a unity gain bandwidth of
56MHz, these amplifiers set an industry leading
power-to-performance ratio for rail-to-rail amplifiers.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Ultra Low Power
– Supply Voltage: 2.5V to 5.5V
– Quiescent Current: 250µA (typ)
– Power Down Mode: 0.5µA (typ)
Bandwidth: 56 MHz
Slew Rate: 160 V/µs
Rise Time: 10ns (2VSTEP)
Settling Time: 45ns (2VSTEP)
Overdrive Recovery Time: 195ns
SNR: 0.00015% (–116.4dBc) at 1 kHz (1VRMS)
THD: 0.00003% (–130dBc) at 1 kHz (1VRMS)
HD2/HD3: –70dBc/–73dBc at 1 MHz (2Vpp)
Input Voltage Noise: 9.3nV/rtHz (f=100 kHz)
Input Offset Voltage: 100 µV (500 µV max)
CMRR: 113dB
Output Current Drive: 40mA
RRO – Rail-to-Rail Output
Input Voltage Range: –0.2V to 3.9V (5V supply)
Operating Temperature Range: –40°C–125°C
APPLICATIONS
•
•
•
•
•
•
•
OPA835 Related Products
DESCRIPTION
2.7V
VSIG
VSIG
2.7V
4.02k
2.5V
100
OPA835
4.02k
V S-
AIN - dBc
DUALS
TRIPLES
QUADS
—
OPA2830
—
OPA4830
Rail-to-Rail, Low
Power
OPA836
OPA2836
—
—
Rail-to-Rail, Fixed
Gain
OPA832
OPA2832
OPA3832
—
General-Purpose, High
Slew Rate
OPA690
OPA2690
OPA3690
—
Low-Noise, DC
Precision
OPA820
OPA2822
—
OPA4820
V S+
VIN
-40
1.35V
5V
2k
SINGLES
Rail-to-Rail
0
0V
The OPA835 and OPA2835 are offered in following
package options:
• OPA835 Single: SOT23-6 (DBV), and 10 pin RUN
with integrated gain resistors.
• OPA2835 Dual: SOIC-8 (D), MSOP-10 (DGS),
and 10 pin RUN.
The devices are characterized for operation over the
extended industrial temperature range –40°C to
125°C.
Low Power Signal Conditioning
Audio ADC Input Buffer
Low Power SAR and ΔΣ ADC Driver
Portable Systems
Low Power Systems
High Density Systems
Ultrasonic Flow Meter
-20
For battery powered portable applications where
power is of key importance, the OPA835's and
OPA2835's low power consumption and high
frequency performance offers designers performance
versus power not attainable in other devices. Coupled
with a power savings mode to reduce current to
<1.5μA, the device offers a very attractive solution for
high frequency amplifiers in battery powered
applications.
+In VDD
2.2nF
REF
ADS8326
-In
-60
2k
2k
-80
-100
-120
-140
0
20,000
40,000
60,000
80,000
Frequency (Hz)
100,000
120,000
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGING/ORDERING INFORMATION (1)
PRODUCT
CHANNEL
COUNT
PACKAGE –
LEAD
PACKAGE
DESIGNATOR
SPECIFIED TEMPERATURE
RANGE
PACKAGE
MARKING
OPA835
1
SOT23-6
DBV
–40°C to 125°C
QUM
OPA835IDBVT
TAPE and REEL, 250
OPA835
1
SOT23-6
DBV
–40°C to 125°C
QUM
OPA835IDBVR
TAPE and REEL, 3000
OPA835 (2)
1
WQFN-10
RUN
–40°C to 125°C
835
OPA835IRUNT
TAPE and REEL, 250
OPA835 (2)
1
WQFN-10
RUN
–40°C to 125°C
835
OPA835IRUNR
TAPE and REEL, 3000
OPA2835 (2)
2
SOIC-8
D
–40°C to 125°C
2835
OPA2835ID
RAIL, 75
OPA2835 (2)
2
SOIC-8
D
–40°C to 125°C
2835
OPA2835IDR
TAPE and REEL, 2500
OPA2835 (2)
2
VSSOP-10
DGS
–40°C to 125°C
2835
OPA2835IDGS
RAIL, 80
OPA2835 (2)
2
VSSOP-10
DGS
–40°C to 125°C
2835
OPA2835IDGSR
TAPE and REEL, 2500
OPA2835 (2)
2
WQFN-10
RUN
–40°C to 125°C
2835
OPA2835IRUNT
TAPE and REEL, 250
OPA2835 (2)
2
WQFN-10
RUN
–40°C to 125°C
2835
OPA2835IRUNR
TAPE and REEL, 3000
(1)
(2)
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Product Preview
ABSOLUTE MAXIMUM RATINGS
UNITS
VS– to VS+
Supply voltage
5.5
VI
Input voltage
VID
Differential input voltage
1V
Ii
Continuous input current
0.85 mA
IO
Continuous output current
VS– - 0.7V to VS+ + 0.7V
60 mA
Continuous power dissipation
See Thermal Characteristics Specification
TJ
Maximum junction temperature
TA
Operating free-air temperature range
–40°C to 125°C
150°C
Tstg
Storage temperature range
–65°C to 150°C
HBM
6 kV
ESD ratings CDM
1 kV
MM
200 V
THERMAL INFORMATION
THERMAL METRIC (1)
OPA835
OPA835
OPA2835
OPA2835
OPA2835
SOT23-6
(DBV)
RUN-10
SOIC-8
(D)
MSOP-10
(DGS)
RUN-10
(DGS)
6 PINS
10 PINS
8 PINS
10 PINS
10 PINS
θJA
Junction-to-ambient thermal resistance
194
TBD
TBD
TBD
TBD
θJCtop
Junction-to-case (top) thermal resistance
129.2
TBD
TBD
TBD
TBD
θJB
Junction-to-board thermal resistance
39.4
TBD
TBD
TBD
TBD
ψJT
Junction-to-top characterization parameter
25.6
TBD
TBD
TBD
TBD
ψJB
Junction-to-board characterization parameter
38.9
TBD
TBD
TBD
TBD
θJCbot
Junction-to-case (bottom) thermal resistance
n/a
TBD
TBD
TBD
TBD
(1)
2
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2011, Texas Instruments Incorporated
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
SPECIFICATIONS: VS = 2.7 V
Test conditions unless otherwise noted: VS+ = +2.7V, VS– = 0V, VOUT = 1VPP, RF = 0Ω, RL = 2kΩ, G = 1V/V, Input and Output
Referenced to mid-supply. TA = 25°C. Unless otherwise noted
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
TEST
LEVEL (1)
MHz
C
AC PERFORMANCE
Small-signal bandwidth
VOUT = 100 mVPP, G = 1
51
VOUT = 100 mVPP, G = 2
22.5
VOUT = 100 mVPP, G = 5
7.2
VOUT = 100 mVPP, G = 10
3
Gain-bandwidth product
VOUT = 100 mVPP, G = 10
30
MHz
C
Large-signal bandwidth
VOUT = 1 VPP, G = 1
24
MHz
C
Bandwidth for 0.1dB flatness
VOUT = 1 VPP, G = 2
4
MHz
C
110/130
V/µs
C
Slew rate, Rise/Fall
Rise/Fall time
9.5/9
ns
C
Settling time to 1%, Rise/Fall
35/30
ns
C
60/65
ns
C
Settling time to 0.01%, Rise/Fall
120/90
ns
C
Overshoot/Undershoot
0.5/0.2
%
C
Settling time to 0.1%, Rise/Fall
nd
2
Order Harmonic Distortion
3rd Order Harmonic Distortion
VOUT = 1VSTEP, G = 2
f = 10 kHz, VIN_CM = mid-supply – 0.5V
-133
f = 100 kHz, VIN_CM = mid-supply – 0.5V
-110
f = 1 MHz, VIN_CM = mid-supply – 0.5V
-73
f = 10 kHz, VIN_CM = mid-supply – 0.5V
-137
f = 100 kHz, VIN_CM = mid-supply – 0.5V
-125
C
dBc
C
C
C
dBc
C
f = 1 MHz, VIN_CM = mid-supply – 0.5V
-78
dBc
C
3rd Order Intermodulation Distortion
f = 1 MHz, 200 kHz Tone Spacing, VOUT Envelope = 1VPP,
VIN_CM = mid-supply – 0.5V
-75
-81
dBc
C
Input voltage noise
f = 100 KHz
9.3
nV/√Hz
C
147
Hz
C
0.45
pA/√Hz
C
14.7
2nd Order Intermodulation Distortion
Voltage Noise 1/f corner frequency
Input current noise
f = 1 MHz
Current Noise 1/f corner frequency
kHz
C
140/125
ns
C
f = 100 kHz
0.028
Ω
C
f = 10 kHz
TBD
dB
C
Overdrive recovery time, Over/Under
Overdrive = 0.5 V
Closed-loop output impedance
Channel to channel crosstalk
(OPA2835)
(1)
C
Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C; over temperature limits by characterization and
simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.
Copyright © 2011, Texas Instruments Incorporated
3
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
SPECIFICATIONS: VS+ = 2.7 V
Test conditions unless otherwise noted: VS+ = +2.7V, VS– = 0V, VOUT = 1VPP, RF = 0Ω, RL = 2kΩ, G = 1V/V, Input and Output
Referenced to mid-supply. TA = 25°C. Unless otherwise noted
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
TEST
LEVEL (1)
dB
A
DC PERFORMANCE
Open-loop voltage gain (AOL)
100
Input referred offset voltage
Input offset voltage drift (2)
Input bias current
Input offset current
Input offset current drift (2)
±500
±880
TA = 0°C to 70°C
TA = –40°C to 85°C
±1040
TA = –40°C to 125°C
±1850
TA = 0°C to 70°C
±1.4
TA = –40°C to 85°C
±1.5
±9
TA = –40°C to 125°C
±2.25
±13.5
200
400
A
µV
B
±8.5
TA = 25°C
50
TA = 0°C to 70°C
47
410
TA = –40°C to 85°C
45
425
TA = –40°C to 125°C
45
530
±0.25
±1.4
TA = –40°C to 85°C
±0.175
±1.05
TA = –40°C to 125°C
TA = 0°C to 70°C
Input bias current drift (2)
120
±100
TA = 25°C
±0.185
±1.1
TA = 25°C
±13
±100
TA = 0°C to 70°C
±13
±100
TA = –40°C to 85°C
±13
±100
TA = –40°C to 125°C
±13
±100
TA = 0°C to 70°C
±0.205
±1.230
TA = –40°C to 85°C
±0.155
±0.940
TA = –40°C to 125°C
±0.155
±0.940
TA = 25°C, <3dB degradation in CMRR limit
–0.2
TA = –40°C to 125°C, <3dB degradation in
CMRR limit
–0.2
µV/°C
B
A
nA
nA/°C
B
B
A
nA
B
nA/°C
B
0
V
A
0
V
B
INPUT
Common-mode input range low
Common-mode input range high
TA = 25°C, <3dB degradation in CMRR limit
1.5
1.6
V
A
TA = –40°C to 125°C, <3dB degradation in
CMRR limit
1.5
1.6
V
B
Common-mode rejection ratio
91
Input impedance common mode
Input impedance differential mode
dB
A
200||1.2
110
kΩ || pF
C
200||1
kΩ || pF
C
OUTPUT
Linear output voltage low
Linear output voltage high
Output saturation voltage, High / Low
Linear output current drive
(1)
(2)
4
TA = 25°C, G = 5
0.15
0.2
V
A
TA = –40°C to 125°C, G = 5
0.15
0.2
V
B
V
A
TA = 25°C, G = 5
2.45
TA = –40°C to 125°C, G = 5
2.45
TA = 25°C, G = 5
TA = 25°C
±25
TA = –40°C to 125°C
±20
2.5
V
B
45/13
2.5
mV
C
±35
mA
A
mA
B
Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C; over temperature limits by characterization and
simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.
Input Offset Voltage Drift, Input Bias Current Drift, and Input Offset Current Drift are average values calculated by taking data at the end
points, computing the difference, and dividing by the temperature range.
Copyright © 2011, Texas Instruments Incorporated
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
SPECIFICATIONS: VS+ = 2.7 V (continued)
Test conditions unless otherwise noted: VS+ = +2.7V, VS– = 0V, VOUT = 1VPP, RF = 0Ω, RL = 2kΩ, G = 1V/V, Input and Output
Referenced to mid-supply. TA = 25°C. Unless otherwise noted
PARAMETER
CONDITIONS
MIN
UNITS
TEST
LEVEL (1)
5.5
V
B
340
µA
A
µA
B
dB
A
V
A
V
A
TYP
MAX
245
345
POWER SUPPLY
Specified operating voltage
Quiescent operating current
2.5
TA = 25°C
190
TA = –40°C to 125°C
135
Power supply rejection (±PSRR)
91
105
POWER DOWN (PIN MUST BE DRIVEN)
Enable voltage threshold
Specified "on" above VS–+ 2.1 V
Disable voltage threshold
Specified "off" below VS–+ 0.7 V
Powerdown pin bias current
PD = 0.7 V
20
500
nA
A
Powerdown quiescent current
PD = 0.7 V
0.5
1.5
µA
A
Turn-on time delay
Time from PD = high to VOUT = 90% of final
value
250
ns
C
Turn-off time delay
Time from PD = low to VOUT = 10% of original
value
50
ns
C
Copyright © 2011, Texas Instruments Incorporated
1.4
0.7
2.1
1.4
5
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
SPECIFICATIONS: VS = 5 V
Test conditions unless otherwise noted: VS+ = +5V, VS– = 0V, VOUT = 2VPP, RF = 0Ω, RL = 2kΩ, G = 1V/V, Input and Output
Referenced to mid-supply. TA = 25°C. Unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
TEST
LEVEL (1)
MHz
C
AC PERFORMANCE
Small-signal bandwidth
VOUT = 100 mVPP, G = 1
56
VOUT = 100 mVPP, G = 2
22.5
VOUT = 100 mVPP, G = 5
7.4
VOUT = 100 mVPP, G = 10
3.1
Gain-bandwidth product
VOUT = 100 mVPP, G = 10
31
MHz
C
Large-signal bandwidth
VOUT = 2 VPP, G = 1
31
MHz
C
Bandwidth for 0.1dB flatness
VOUT = 2 VPP, G=2
14.5
MHz
C
160/260
V/µs
C
10/7
ns
C
45/45
ns
C
50/55
ns
C
82/85
ns
C
2.5/1.5
%
C
Slew rate, Rise/Fall
Rise/Fall time
Settling time to 1%, Rise/Fall
Settling time to 0.1%, Rise/Fall
VOUT = 2V Step, G=2
Settling time to 0.01%, Rise/Fall
Overshoot/Undershoot
nd
2
Order Harmonic Distortion
3rd Order Harmonic Distortion
2nd Order Intermodulation Distortion
3rd Order Intermodulation Distortion
f = 10 kHz
–135
f = 100 kHz
–105
f = 1 MHz
-70
f = 10 kHz
–139
f = 100 kHz
–122
dBc
C
C
C
dBc
C
f = 1 MHz
-73
f = 1 MHz, 200 kHz Tone Spacing, VOUT Envelope =
2VPP
–70
dBc
C
–83
dBc
C
Signal to Noise Ratio, SNR
f = 1kHz, VOUT = 1 VRMS, 22kHz bandwidth
Total Harmonic Distortion, THD
f = 1kHz, VOUT = 1 VRMS
Input voltage noise
f = 100 KHz
Voltage Noise 1/f corner frequency
Input current noise
C
f = 1 MHz
Current Noise 1/f corner frequency
0.00015
-116.4
0.00003
-130
C
%
dBc
C
%
C
dBc
C
9.3
nV/√Hz
C
147
Hz
C
0.45
pA/√Hz
C
14.7
Hz
C
195/135
ns
C
Overdrive recovery time, Over/Under
Overdrive = 0.5 V
Closed-loop output impedance
f = 100 kHz
0.028
Ω
C
Channel to channel crosstalk
(OPA2835)
f = 10 kHz
TBD
dB
C
(1)
6
Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C; over temperature limits by characterization and
simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.
Copyright © 2011, Texas Instruments Incorporated
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
SPECIFICATIONS: VS = 5 V
Test conditions unless otherwise noted: VS+ = +5V, VS– = 0V, VO = 2VPP, RF = 0Ω, RL = 2kΩ, G = 1V/V, Input and Output
Referenced to mid-supply. TA = 25°C. Unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
TEST
LEVEL (1)
dB
A
DC PERFORMANCE
Open-loop voltage gain (AOL)
100
Input referred offset voltage
Input offset voltage drift (2)
Input bias current
Input offset current
Input offset current drift (2)
±500
±880
TA = 0°C to 70°C
TA = –40°C to 85°C
±1040
TA = –40°C to 125°C
±1850
TA = 0°C to 70°C
±1.4
TA = –40°C to 85°C
±1.5
±9
TA = –40°C to 125°C
±2.25
±13.5
200
400
A
µV
B
±8.5
TA = 25°C
50
TA = 0°C to 70°C
47
410
TA = –40°C to 85°C
45
425
TA = –40°C to 125°C
45
530
±0.25
±1.4
TA = –40°C to 85°C
±0.175
±1.05
TA = –40°C to 125°C
TA = 0°C to 70°C
Input bias current drift (2)
120
±100
TA = 25°C
±0.185
±1.1
TA = 25°C
±13
±100
TA = 0°C to 70°C
±13
±100
TA = –40°C to 85°C
±13
±100
TA = –40°C to 125°C
±13
±100
TA = 0°C to 70°C
±0.205
±1.23
TA = –40°C to 85°C
±0.155
±0.94
TA = –40°C to 125°C
±0.155
±0.94
TA = 25°C, <3dB degradation in CMRR limit
–0.2
TA = –40°C to 125°C, <3dB degradation in CMRR limit
–0.2
µV/°C
B
A
nA
nA/°C
B
B
A
nA
B
nA/°C
B
0
V
A
0
V
B
INPUT
Common-mode input range low
Common-mode input range high
TA = 25°C, <3dB degradation in CMRR limit
3.8
3.9
V
A
TA = –40°C to 125°C, <3dB degradation in CMRR limit
3.8
3.9
V
B
94
113
dB
A
200||1.2
kΩ || pF
C
200||1
kΩ || pF
C
Common-mode rejection ratio
Input impedance common mode
Input impedance differential mode
OUTPUT
Linear output voltage low
Linear output voltage high
Output saturation voltage, High / Low
Linear output current drive
(1)
(2)
TA = 25°C, G = 5
0.15
0.2
V
A
TA = –40°C to 125°C, G = 5
0.15
0.2
V
B
V
A
TA = 25°C, G = 5
4.75
TA = –40°C to 125°C, G = 5
4.75
TA = 25°C, G = 5
TA = 25°C
±30
TA = –40°C to 125°C
±25
4.8
V
B
70/25
4.8
mV
C
±40
mA
A
mA
B
Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C; over temperature limits by characterization and
simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.
Input Offset Voltage Drift, Input Bias Current Drift, and Input Offset Current Drift are average values calculated by taking data at the end
points, computing the difference, and dividing by the temperature range.
Copyright © 2011, Texas Instruments Incorporated
7
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
SPECIFICATIONS: VS = 5 V (continued)
Test conditions unless otherwise noted: VS+ = +5V, VS– = 0V, VO = 2VPP, RF = 0Ω, RL = 2kΩ, G = 1V/V, Input and Output
Referenced to mid-supply. TA = 25°C. Unless otherwise noted.
PARAMETER
CONDITIONS
MIN
UNITS
TEST
LEVEL (1)
5.5
V
B
350
µA
A
µA
B
dB
A
V
A
V
A
A
TYP
MAX
250
365
POWER SUPPLY
Specified operating voltage
Quiescent operating current
2.5
TA = 25°C
215
TA = –40°C to 125°C
150
Power supply rejection (±PSRR)
93
110
POWER DOWN (PIN MUST BE DRIVEN)
Enable voltage threshold
Specified "on" above VS–+ 2.1 V
Disable voltage threshold
Specified "off" below VS–+ 0.7 V
Powerdown pin bias current
PD = 0.7 V
20
500
nA
Powerdown quiescent current
PD = 0.7 V
0.5
1.5
µA
A
Turn-on time delay
Time from PD = high to VOUT = 90% of final value
200
ns
C
Turn-off time delay
Time from PD = low to VOUT = 10% of original value
60
ns
C
8
1.4
0.7
2.1
1.4
Copyright © 2011, Texas Instruments Incorporated
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
DEVICE INFORMATION
PIN CONFIGURATIONS
OPA835 (TOP VIEW)
OPA835 (TOP VIEW)
SOT23-6 (DBV)
RUN-10
VS+
VOUT
1
6
VS+
VS-
2
5
PD
VIN+
3
4
VIN-
VOUT
1
VIN-
2
VIN+
3
PD
4
10
9
FB1
8
FB2
7
FB3
6
FB4
1k
+ -
- +
750
250
5
VS-
OPA2835 (TOP VIEW)
OPA2835 (TOP VIEW)
SOIC-8 (D)
MSOP-10 (DGS)
VOUT1
1
VIN1-
2
VIN1+
3
VS-
4
+
+
VOUT1
1
VOUT2
VIN1-
2
6
VIN2-
VIN1+
3
5
VIN2+
VS-
4
PD1
5
8
VS+
7
10
+
+
VS+
9
VOUT2
8
VIN2-
7
VIN2+
6
PD2
OPA2835 (TOP VIEW)
RUN-10
VS+
VOUT1
1
VIN1-
2
VIN1+
3
PD1
4
10
9
VOUT2
8
VIN2-
7
VIN2+
6
PD2
+ -
- +
5
VS-
Copyright © 2011, Texas Instruments Incorporated
9
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
PIN FUNCTIONS
PIN
NUMBER
DESCRIPTION
NAME
OPA835 DBV PACKAGE
1
VOUT
Amplifier output
2
VS–
Negative power supply input
3
VIN+
Amplifier non-inverting input
4
VIN–
Amplifier inverting input
5
PD
Amplifier Power Down, low = low power mode, high = normal operation (PIN MUST BE DRIVEN)
6
VS+
Positive power supply input
OPA835 RUN PACKAGE
1
VOUT
Amplifier output
2
VIN–
Amplifier inverting input
3
VIN+
Amplifier non-inverting input
4
PD
Amplifier Power Down, low = low power mode, high = normal operation (PIN MUST BE DRIVEN)
5
VS–
Negative power supply input
6
FB4
Connection to bottom of 250 Ω internal gain setting resistors
7
FB3
Connection to junction of 750 and 250 Ω internal gain setting resistors
8
FB2
Connection to junction of 1k and 750 Ω internal gain setting resistors
9
FB1
Connection to top of 1kΩ internal gain setting resistors
10
VS+
Positive power supply input
OPA2835 D PACKAGE
1
VOUT1
Amplifier 1 output
2
VIN1–
Amplifier 1 inverting input
3
VIN1+
Amplifier 1 non-inverting input
4
VS–
5
VIN2+
Negative power supply input
Amplifier 2 non-inverting input
6
VIN2–
Amplifier 2 inverting input
7
VOUT2
Amplifier 2 output
8
VS+
Positive power supply input
OPA2835 DSG PACKAGE
1
VOUT1
Amplifier 1 output
2
VIN1–
Amplifier 1 inverting input
3
VIN1+
Amplifier 1 non-inverting input
4
VS–
Negative power supply input
5
PD1
Amplifier 1 Power Down, low = low power mode, high = normal operation (PIN MUST BE DRIVEN)
6
PD2
Amplifier 2 Power Down, low = low power mode, high = normal operation (PIN MUST BE DRIVEN)
7
VIN2+
Amplifier 2 non-inverting input
8
VIN2–
Amplifier 2 inverting input
9
VOUT2
Amplifier 2 output
10
VS+
Positive power supply input
OPA2835 RUN PACKAGE
10
1
VOUT1
Amplifier 1 output
2
VIN1–
Amplifier 1 inverting input
3
VIN1+
Amplifier 1 non-inverting input
4
PD1
Amplifier 1 Power Down, low = low power mode, high = normal operation (PIN MUST BE DRIVEN)
5
VS–
Negative power supply input
6
PD2
Amplifier 2 Power Down, low = low power mode, high = normal operation (PIN MUST BE DRIVEN)
7
VIN2+
Amplifier 2 non-inverting input
Copyright © 2011, Texas Instruments Incorporated
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
PIN FUNCTIONS (continued)
PIN
NUMBER
DESCRIPTION
NAME
8
VIN2–
Amplifier 2 inverting input
9
VOUT2
Amplifier 2 output
10
VS+
Positive power supply input
SPACER
TYPICAL PERFORMANCE GRAPHS: VS = 2.7 V
Test conditions unless otherwise noted: VS+ = +2.7V, VS– = 0V, VOUT = 1Vpp, RF = 0Ω, RL = 2kΩ, G = 1V/V, Input and Output
Referenced to mid-supply unless otherwise noted. TA = 25°C.
Table of Graphs
FIGURES
Small Signal Frequency Response
Figure 1
Large Signal Frequency Response
Figure 2
Noninverting Pulse Response
Figure 3
Inverting Pulse Response
Figure 4
Slew rate
vs Output Voltage Step
Output Overdrive Recovery
Figure 5
Figure 6
Harmonic Distortion
vs Frequency
Figure 7
Harmonic Distortion
vs Load Resistance
Figure 8
Harmonic Distortion
vs Output Voltage
Figure 9
Harmonic Distortion
vs Gain
Figure 10
Output Voltage Swing
vs Load Resistance
Figure 11
Output Saturation Voltage
vs Load Current
Figure 12
Output Impedance
vs Frequency
Figure 13
Frequency Response with Capacitive Load
Figure 14
Series Output Resistor
vs Capacitive Load
Figure 15
Input Referred Noise
vs Frequency
Figure 16
Open Loop Gain
vs Frequency
Figure 17
Common Mode/Power Supply Rejection Ratios
vs Frequency
Figure 18
Power Down Response
Figure 19
Input Offset Voltage
Input Offset Voltage
Figure 20
vs Free-Air Temperature
Input Offset Voltage Drift
Figure 22
Input Offset Current
Input Offset Current
Input Offset Current Drift
Copyright © 2011, Texas Instruments Incorporated
Figure 21
Figure 23
vs Free-Air Temperature
Figure 24
Figure 25
11
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
TYPICAL PERFORMANCE GRAPHS: VS = 2.7 V
21
21
VS = 2.7 V,
VOUT = 100 mVpp,
G = 10
18
15
G=5
G=5
12
Gain Magnitude - dB
Gain Magnitude - dB
RL = 2 kW
RL = 2 kW
15
VS = 2.7 V,
VOUT = 1 Vpp,
G = 10
18
9
6
G=2
3
12
9
6
G=2
G=1
3
0
0
-3
-3
G=1
G = -1
-6
-6
G = -1
-9
100k
1M
10M
f - Frequency - Hz
-9
100k
100M
10M
100M
f - Frequency - Hz
Figure 1. Small Signal Frequency Response
Figure 2. Large Signal Frequency Response
3
2.5
VS = 2.7 V,
G = 1,
RF = 0 W
VS = 2.7 V,
G = -1,
RF = 2 kW
2.5
RL = 2 kW
VO - Output Voltage - V
2 R = 2 kW
L
VO - Output Voltage - V
1M
1.5
VOUT = 1.5 Vpp
1
0.5
VOUT = 2 Vpp
2
1.5
VOUT = 0.5 Vpp
1
0.5
VOUT = 0.5 Vpp
0
500
t - Time - ns
0
1000
Figure 3. Noninverting Pulse Response
1000
Figure 4. Inverting Pulse Response
0.75
140
VS = 2.7 V,
G = 2,
120 R = 2 kW
F
3.75
VS = 2.7 V,
G = 5,
RF = 2 kW,
RL = 2 kW
0.5
100
Falling
VI - Input Voltage - V
Slew Rate - V/ms
500
t - Time - ns
80
Rising
60
VIN
3.25
VOUT
2.75
RL = 2 kW
2.25
1.75
1.25
0.25
0.75
0.25
40
VO - Output Voltage - V
0
0
0
-0.25
20
-0.75
0
0.5
0.6
0.7
0.8
Output Voltage Step - V
0.9
Figure 5. Slew Rate vs Output Voltage Step
12
1
-0.25
0
500
1000
t - Time - ns
1500
-1.25
2000
Figure 6. Output Overdrive Recovery
Copyright © 2011, Texas Instruments Incorporated
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
TYPICAL PERFORMANCE GRAPHS: VS = 2.7 V (continued)
-50
-30
VS = 2.7 V,
G = 1,
VOUT = 1 Vpp,
-40
RF = 0 W,
RL = 2 kW
-60
-70
-80
-90
HD2
-100
HD3
-110
-60
Harmonic Distortion - dBc
Harmonic Distortion - dBc
-50
VS = 2.7 V,
G = 1,
f = 1 MHz,
RF = 0 W
VOUT = 1 Vpp
-55
-65
HD2
-70
-75
HD3
-80
-120
-85
-130
-90
100
-140
f - Frequency - Hz
1k
RLOAD - Load Resistance - W
Figure 7. Harmonic Distortion vs Frequency
Figure 8. Harmonic Distortion vs Load Resistance
10k
1M
100k
10M
-30
-40
VS = 2.7 V,
G = 1,
f = 1 MHz,
RF = 0 W,
VS = 2.7 V,
G = 1,
f = 1 MHz,
VOUT = 1 Vpp,
-45
-50
RL = 2 kW
Harmonic Distortion - dBc
Harmonic Distortion - dBc
-40
-50
-60
HD2
-70
RL = 2 kW
-55
-60
HD3
-65
-70
HD2
-75
-80
-80
HD3
-85
-90
-90
0
1
VO - Output Voltage - Vpp
1
2
Figure 9. Harmonic Distortion vs Output Voltage
3
2
3
4
5
6
Gain - V/V
7
8
9
10
Figure 10. Harmonic Distortion vs Gain
1
VS = 2.7 V,
G = 5,
RF = 2 kW
2.5
VS = 2.7 V,
G = 5,
RF = 2 kW
VOUT = High
VSAT - Saturation Voltage - V
VO - Output Voltage - V
10k
2
1.5
1
0.1
VOUT = High
VOUT = Low
0.01
0.5
VOUT = Low
0
10
100
1k
10k
RL - Load Resistance - W
Figure 11. Output Voltage Swing vs Load Resistance
Copyright © 2011, Texas Instruments Incorporated
0.001
0.1
1
10
IL - Load Current - mA
100
Figure 12. Output Saturation Voltage vs Load Current
13
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
TYPICAL PERFORMANCE GRAPHS: VS = 2.7 V (continued)
1000
3
VS = 2.7 V,
G=1
100
CL = 10 pF
Gain Magnitude - dB
ZO - Output Impedance - W
0
10
1
RO = 0 W
CL = 100 pF
CL = 22 pF
RO = 40.2 W
RO = 76.8 W
CL = 220 pF
-3
CL = 1 pF
RO = 24.9 W
RO = 0 W
CL = 560 pF
RO = 13 W
-6
0.1
VS = 2.7 V,
G = 1,
RF = 0 W
CL = 1000 pF
RO = 10 W
RL = 2 kW
0.01
10k
1M
10M
f - Frequency - Hz
100k
100M
-9
100k
1G
Figure 13. Output Impedance vs Frequency
10M
f - Frequency - Hz
1M
100M
1G
Figure 14. Frequency Response with Capacitive Load
100
100
VS = 2.7 V,
G = 1,
RF = 0 W,
VS = 2.7 V
Vn, In - nV/ ÖHz, pa/Ö Hz
RO - Output Resistor - W
RL = 2 kW
10
Voltage Noise
10
1
Current Noise
1
10
100
0.1
10
1000
100
1k
CLOAD - Capacitive Load - pF
VS = 2.7 V
-50
-10
-100
-20
Open Loop Gain Phase
-150
Open Loop Gain Magnitude
-200
-250
10
100
1k
10k
100k
1M
f - Frequency - Hz
10M
100M
Figure 17. Open Loop Gain vs Frequency
14
10M
0
0
VS = 2.7 V
1G
CMRR/PSRR - dB
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
-10
-20
-30
-40
1
1M
Figure 16. Input Reffered Noise vs Frequency
AOL - Phase - deg
AOL - Magnitude - dB
Figure 15. Series Output Resistor vs Capacitive Load
10k
100k
f - Frequency - Hz
PSRR
-30
-40
CMRR
-50
-300
-60
-350
-70
-400
-80
10k
100k
1M
f - Frequency - Hz
10M
100M
Figure 18. Common Mode/Power Supply Rejection Ratios
vs Frequency
Copyright © 2011, Texas Instruments Incorporated
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
TYPICAL PERFORMANCE GRAPHS: VS = 2.7 V (continued)
3
1600
VS = 2.7 V,
G = 2,
RF = 2 kW
2.5
VPD
1412
1400
RL = 2 kW
1143
1200
2
962
Count
VOUT / VPD
1000
1.5
800
VOUT
582
600
1
395
400
0.5
158
52
>692
<484.4
<346
<415.2
17 2 1 0 0 0 0
<276.8
<138.4
<207.6
<0
<69.2
<-138.4
<-69.2
<-276.8
1000
<-207.6
500
t - Time - ns
<-415.2
<-346
0
<-553.6
<-484.4
0
<-692
0
<-622.8
0 0 0 1 4 13 26
<553.6
<622.8
<692
112
200
VOS - Offset Voltage - mV
Figure 20. Input Offset Voltage
800
3.5
600
3
0°C to 70°C
-40°C to 85°C
-40°C to 125°C
400
2.5
200
2
Count
VOS - Offset Voltage - mV
Figure 19. Power Down Response
0
1.5
-200
1
-400
0.5
-600
0
-800
-40
-20
0
20
40
60
80
100
120
TA - Free-Air Temperature - °C
-5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VOS - Drift - mV/°C
Figure 21. Input Offset Voltage vs Free-Air Temperature
Figure 22. Input Offset Voltage Drift
100
1200
80
967
904
60
IOS - Offset Current - nA
1000
772
800
Count
695
600
402
369
400
40
20
0
-20
-40
213
174
-60
200
80
36
81
37 24 14
31
4 4
9 3 13 16 32
<45
>45
<36
<40.5
<27
<31.5
<22.5
<13.5
<18
<0
<4.5
<9
<-9
<-4.5
<-13.5
<-36
<-31.5
<-27
<-22.5
<-18
<-45
<-40.5
0
-80
-100
-40
-20
0
20
40
60
80
100
120
TA - Free-Air Temperature - °C
IOS - Offset Current - nA
Figure 23. Input Offset Current
Copyright © 2011, Texas Instruments Incorporated
Figure 24. Input Offset Current vs Free-Air Temperature
15
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
TYPICAL PERFORMANCE GRAPHS: VS = 2.7 V (continued)
7
6
0°C to 70°C
-40°C to 85°C
-40°C to 125°C
5
Count
4
3
2
1
0
-250 -200-150-100-50 0
50 100 150 200 250 300 350 400 450 500 550
IOS - Drift - pA/°C
Figure 25. Input Offset Current Drift
16
Copyright © 2011, Texas Instruments Incorporated
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
TYPICAL PERFORMANCE GRAPHS: VS = 5 V
Test conditions unless otherwise noted: VS+ = +5V, VS– = 0V, VOUT = 2Vpp, RF = 0Ω, RL = 2kΩ, G = 1V/V, Input and Output
Referenced to mid-supply unless otherwise noted. TA = 25°C.
Table of Graphs
FIGURES
Small Signal Frequency Response
Figure 26
Large Signal Frequency Response
Figure 27
Noninverting Pulse Response
Figure 28
Inverting Pulse Response
Figure 29
Slew rate
vs Output Voltage Step
Output Overdrive Recovery
Figure 30
Figure 31
Harmonic Distortion
vs Frequency
Figure 32
Harmonic Distortion
vs Load Resistance
Figure 33
Harmonic Distortion
vs Output Voltage
Figure 34
Harmonic Distortion
vs Gain
Figure 35
Output Voltage Swing
vs Load Resistance
Figure 36
Output Saturation Voltage
vs Load Current
Figure 37
Output Impedance
vs Frequency
Figure 38
Frequency Response with Capacitive Load
Figure 39
Series Output Resistor
vs Capacitive Load
Figure 40
Input Referred Noise
vs Frequency
Figure 41
Open Loop Gain
vs Frequency
Figure 42
Common Mode/Power Supply Rejection Ratios
vs Frequency
Figure 43
Power Down Response
Figure 44
Input Offset Voltage
Input Offset Voltage
Figure 45
vs Free-Air Temperature
Input Offset Voltage Drift
Figure 47
Input Offset Current
Input Offset Current
Input Offset Current Drift
Copyright © 2011, Texas Instruments Incorporated
Figure 46
Figure 48
vs Free-Air Temperature
Figure 49
Figure 50
17
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
TYPICAL PERFORMANCE GRAPHS: VS = 5 V
21
21
VS = 5 V,
VOUT = 100 mVpp,
G = 10
18
RL = 2 kW
G=5
12
9
6
G=2
3
G=1
9
6
G=2
3
0
-3
-3
1M
G = -1
G=1
-6
G = -1
-9
100k
G=5
12
0
-6
RL = 2 kW
15
Gain Magnitude - dB
10M
-9
100k
100M
1M
Figure 26. Small Signal Frequency Response
5
VS = 5 V,
4.5 G = -1,
RF = 2 kW
4 R = 2 kW
4.5
4
3.5
VOUT = 4 Vpp
L
VOUT = 4 Vpp
VO - Output Voltage - V
VO - Output Voltage - V
100M
Figure 27. Large Signal Frequency Response
5
VS = 5 V,
G = 1,
RF = 0 W
3
2.5
RL = 2 kW
2
1.5
1
3.5
3
2.5
VOUT = 0.5 Vpp
2
1.5
1
0.5
0.5
VOUT = 0.5 Vpp
0
0
0
500
t - Time - ns
0
1000
Figure 28. Noninverting Pulse Response
250
500
t - Time - ns
1000
Figure 29. Inverting Pulse Response
300
6.25
1.25
VS = 5 V,
G = 2,
RF = 2 kW
Falling
1
VS = 5 V,
G = 5,
RF = 2 kW,
VIN
5.75
VOUT
5.25
4.75
RL = 2 kW
RL = 2 kW
4.25
VI - Input Voltage - V
Slew Rate - V/ms
10M
f - Frequency - Hz
f - Frequency - Hz
200
Rising
150
100
3.75
0.75
3.25
2.75
0.5
2.25
1.75
1.25
0.25
VO - Output Voltage - V
Gain Magnitude - dB
15
VS = 5 V,
VOUT = 2 Vpp,
G = 10
18
0.75
0.25
50
0
0
0
1
2
Output Voltage Step - V
3
Figure 30. Slew Rate vs Output Voltage Step
18
4
-0.25
0
-0.25
500
1000
t - Time - ns
1500
-0.75
-1.25
2000
Figure 31. Output Overdrive Recovery
Copyright © 2011, Texas Instruments Incorporated
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
TYPICAL PERFORMANCE GRAPHS: VS = 5 V (continued)
-30
-50
-50
VS = 5 V,
G = 1,
VOUT = 2 Vpp,
-60
RL = 2 kW
VS = 5 V,
G = 1,
f = 1 MHz,
RF = 0 W
VOUT = 2 Vpp
-55
RF = 0 W,
Harmonic Distortion - dBc
Harmonic Distortion - dBc
-40
-70
-80
-90
HD2
-100
-110
HD3
-60
-65
HD2
-70
HD3
-75
-80
-120
-85
-130
-140
10k
100k
1M
-90
100
10M
f - Frequency - Hz
1k
10k
RLOAD - Load Resistance - W
Figure 32. Harmonic Distortion vs Frequency
Figure 33. Harmonic Distortion vs Load Resistance
-40
-40
VS = 5 V,
G = 1,
f = 1 MHz,
RF = 0 W,
Harmonic Distortion - dBc
-50
VS = 5 V,
-45 G = 1,
f = 1 MHz,
-50 V
OUT = 2 Vpp,
Harmonic Distortion - dBc
-45
RL = 2 kW
-55
HD3
-60
HD2
-65
-70
-75
-55
-65
HD2
-70
-75
-80
-85
-85
-90
1
-90
1
2
VO - Output Voltage - Vpp
3
4
2
Figure 34. Harmonic Distortion vs Output Voltage
VS = 5 V,
G = 5,
RF = 2 kW
3
4
5
6
Gain - V/V
7
8
9
10
Figure 35. Harmonic Distortion vs Gain
1
5
HD3
-60
-80
0
RL = 2 kW
VOUT = High
VS = 5 V,
G = 5,
RF = 2 kW
VSAT - Saturation Voltage - V
VO - Output Voltage - V
4
3
2
VOUT = High
0.1
VOUT = Low
1
VOUT = Low
0
10
100
1k
10k
RL - Load Resistance - W
Figure 36. Output Voltage Swing vs Load Resistance
Copyright © 2011, Texas Instruments Incorporated
0.01
0.1
1
10
IL - Load Current - mA
100
Figure 37. Output Saturation Voltage vs Load Current
19
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
TYPICAL PERFORMANCE GRAPHS: VS = 5 V (continued)
ZO - Output Impedance - W
100
3
VS = 5 V,
G=1
VS = 5 V,
G = 1,
RF = 0 W
RL = 2 kW
0
Gain Magnitude - dB
10
1
0.1
CL = 10 pF
CL = 100 pF
RO = 0 W
RO = 40.2 W
CL = 220 pF
-3
CL = 1 pF
RO = 24.9 W
RO = 0 W
CL = 560 pF
CL = 22 pF
RO = 13 W
RO = 76.8 W
CL = 1000 pF
-6
RO = 10 W
0.01
10K
100K
1M
10M
f - Frequency - Hz
100M
-9
100k
1G
Figure 38. Output Impedance vs Frequency
10M
f - Frequency - Hz
1M
100M
1G
Figure 39. Frequency Response with Capacitive Load
100
100
VS = 5 V,
G = 1,
RF = 0 W,
VS = 5 V
Vn, In - nV/ ÖHz, pa/Ö Hz
RO - Output Resistor - W
RL = 2 kW
10
Voltage Noise
10
1
Current Noise
1
10
100
0.1
10
1000
100
1k
CLOAD - Capacitive Load - pF
VS = 5 V
VS = 5 V
-50
-10
-100
-20
Open Loop Gain Phase
-150
-200
Open Loop Gain Magnitude
-250
10
100
1k
10k
100k
1M
f - Frequency - Hz
10M
100M
Figure 42. Open Loop Gain vs Frequency
20
10M
0
0
CMRR/PSRR - dB
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
-10
-20
-30
-40
1
1M
Figure 41. Input Reffered Noise vs Frequency
AOL - Phase - deg
AOL - Magnitude - dB
Figure 40. Series Output Resistor vs Capacitive Load
10k
100k
f - Frequency - Hz
-30
CMRR
-40
-50
-300
-60
-350
-70
-400
1G
PSRR
-80
10k
100k
1M
f - Frequency - Hz
10M
100M
Figure 43. Common Mode/Power Supply Rejection Ratios
vs Frequency
Copyright © 2011, Texas Instruments Incorporated
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
TYPICAL PERFORMANCE GRAPHS: VS = 5 V (continued)
5
1600
4.5
VS = 5 V,
G = 2,
RF = 2 kW
VPD
4
1404
1400
RL = 2 kW
1156
1200
3.5
VOUT
Count
VOUT / VPD
965
1000
3
2.5
800
590
2
600
1.5
377
400
1
170
108
>692
<484.4
13 2 1 0 0 0 0
<553.6
<622.8
<692
<138.4
<207.6
<0
<69.2
<-138.4
<-69.2
<-276.8
<-207.6
<-415.2
<-346
1000
<-553.6
<-484.4
500
t - Time - ns
<-692
0
<-622.8
0
0
<346
<415.2
53
0 0 0 1 3 11 26
<276.8
200
0.5
VOS - Offset Voltage - mV
Figure 45. Input Offset Voltage
800
3.5
600
3
0°C to 70°C
-40°C to 85°C
-40°C to 125°C
400
2.5
200
2
Count
VOS - Offset Voltage - mV
Figure 44. Power Down Response
0
1.5
-200
1
-400
0.5
-600
-800
-40
0
-20
0
20
40
80
60
100
120
TA - Free-Air Temperature - °C
-5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VOS - Drift - mV/°C
Figure 46. Input Offset Voltage vs Free-Air Temperature
1000
Figure 47. Input Offset Voltage Drift
100
948
895
80
900
800
60
754
IOS - Offset Current - nA
715
Count
700
600
500
397
382
400
300
205
188
20
0
-20
-40
-60
200
94
100
40
75
37 7 5 9 20 34
36 26 14 5 3 31
IOS - Offset Current - nA
Figure 48. Input Offset Current
Copyright © 2011, Texas Instruments Incorporated
<45
>45
<36
<40.5
<27
<31.5
<22.5
<13.5
<18
<0
<4.5
<9
<-9
<-4.5
<-13.5
<-36
<-31.5
<-27
<-22.5
<-18
<-45
<-40.5
0
-80
-100
-40
-20
0
20
40
60
80
100
120
TA - Free-Air Temperature - °C
Figure 49. Input Offset Current vs Free-Air Temperature
21
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
TYPICAL PERFORMANCE GRAPHS: VS = 5 V (continued)
9
8
0°C to 70°C
-40°C to 85°C
-40°C to 125°C
7
Count
6
5
4
3
2
1
0
-250 -200-150-100-50 0
50 100 150 200 250 300 350 400 450 500 550
IOS - Drift - pA/°C
Figure 50. Input Offset Current Drift
22
Copyright © 2011, Texas Instruments Incorporated
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
APPLICATION INFORMATION
The following circuits show application information for the OPA835 and OPA2835. For simplicity, power supply
decoupling capacitors are not shown in these diagrams.
Non-Inverting Amplifier
The OPA835 and OPA2835 can be used as non-inverting amplifiers with signal input to the non-inverting input,
VIN+. A basic block diagram of the circuit is shown in Figure 51.
If we set VIN = VREF + VSIG, then
æ
RF ö
V
= VSIG ç 1 +
÷ + VREF
OUT
RG ø
è
(1)
RF
G= 1 +
RG , and V
The signal gain of the circuit is set by:
REF provides a reference around which the input and
output signals swing. Output signals are in-phase with the input signals.
The OPA835 and OPA2835 are designed for the nominal value of RF to be 2kΩ in gains other than +1. This
gives excellent distortion performance, maximum bandwidth, best flatness, and best pulse response. RF = 2kΩ
should be used as a default unless other design goals require changing to other values All test circuits used to
collect data for this data sheet had RF = 2kΩ for all gains other than +1. Gain of +1 is a special case where RF is
shorted and RG is left open.
VSIG
VS+
VREF
VIN
RG
OPA 835
VOUT
GVSIG
VREF
VS-
VREF
RF
Figure 51. Non-Inverting Amplifier
Inverting Amplifier
The OPA835 and OPA2835 can be used as inverting amplifiers with signal input to the inverting input, VIN-,
through the gain setting resistor RG. A basic block diagram of the circuit is shown in Figure 52.
If we set VIN = VREF + VSIG, then
æ -R ö
VOUT = VSIG ç F ÷ + VREF
è RG ø
(2)
G=
-RF
RG and V
The signal gain of the circuit is set by:
REF provides a reference point around which the input
and output signals swing. Output signals are 180˚ out-of-phase with the input signals. The nominal value of RF
should be 2kΩ for inverting gains.
Copyright © 2011, Texas Instruments Incorporated
23
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
VS+
VREF
VSIG
VREF
OPA 835
RG
VIN
VOUT
GVSIG
VREF
VSRF
Figure 52. Inverting Amplifier
Attenuators
The non-inverting circuit of Figure 51 has minimum gain of 1. To implement attenuation, a resistor divider can be
placed in series with the positive input, and the amplifier set for gain of 1 by shorting VOUT to VIN- and removing
RG. Since the op amp input is high impedance, the attenuation is set by the resistor divider.
The inverting circuit of Figure 52 can be used as an attenuator by making RG larger than RF. The attenuation is
simply the resistor ratio. For example a 10:1 attenuator can be implemented with RF = 2kΩ and RG = 20kΩ.
Differential to Signal Ended Amplifier
Figure 53 shows a differential amplifier that is used to convert differential signals to single-ended and provides
gain (or attenuation) and level shifting. This circuit can be used in applications like a line receiver for converting a
differential signal from a CAT 5 cable to single-ended.
If we set VIN+ = VCM + VSIG+ and VIN- = VCM + VSIG-, then
æR ö
VOUT = (VIN+ - VIN - ) ´ ç F ÷ + VREF
è RG ø
G=
(3)
RF
RG , V is rejected, and V
The signal gain of the circuit is set by:
CM
REF provides a level shift around which
the output signal swings. The single ended output signal is in-phase with the differential input signal.
VSIG-
RF
VCM
VINVIN+
VSIG+
VCM
RG
VOUT
OPA835
RG
G[(VSIG+)-(VSIG-)]
RF
VREF
VREF
Figure 53. Differential to Single Ended Amplifier
Line termination can be accomplished with a resistor shunt across the input. The impedance seen differential
from the line will be the resistor value in parallel with the amplifier circuit. For low gain and low line impedance
the resistor value to add is approximately the impedance of the line. For example if 100Ω CAT5 cable is used
with a gain of 1 amplifier and RF = RG = 2 kΩ, adding a 100Ω shunt across the input will give a differential
impedance of 99Ω; this should be adequate for most applications.
For best CMRR performance, resistors must be matched. A rule of thumb is CMRR ≈ the resistor tolerance; so
0.1% tolerance will provide about 60dB CMRR.
24
Copyright © 2011, Texas Instruments Incorporated
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
Differential to Differential Amplifier
Figure 54 shows a differential amplifier that is used to amplify differential signals. This circuit has high input
impedance and is often used in differential line driver applications where the signal source is a high impedance
driver like a differential DAC that needs to drive a line.
If we set VIN± = VCM + VSIG± then
æ
2RF ö
V
= VIN ± ´ ç 1 +
÷ + VCM
OUT ±
RG ø
è
(4)
G= 1 +
2RF
RG , and V passes with unity gain. The amplifier in essence
The signal gain of the circuit is set by:
CM
combines two non-inverting amplifiers into one differential amplifier with the RG resistor shared, which makes RG
effectively 1/2 its value when calculating the gain. The output signals are in-phase with the input signals.
VINOPA 835
VOUT-
VSIGGVSIGVCM
VCM
RF
RG
RF
VSIG+
GVSIG+
VCM
VCM
OPA 835
VOUT+
VIN+
Figure 54. Differential to Differential Amplifier
Instrumentation Amplifier
Figure 55 is an instrumentation amplifier that combines the high input impedance of the differential to differential
amplifier circuit and the common-mode rejection of the differential to single-ended amplifier circuit. This circuit is
often used in applications where high input impedance is required like taps from a differential line or in cases
where the signal source is a high impedance.
If we set VIN+ = VCM + VSIG+ and VIN- = VCM + VSIG-, then
VOUT =
(VIN+ - VIN- )
æ
2RF1 ö æ RF2
´ ç1 +
÷ ç
RG1 ø è RG2
è
ö
÷ + VREF
ø
(5)
The signal gain of the circuit is set by:
æ
2R F1 ö
G = ç1 +
÷
RG 1 ø
è
swings. The single
æ R F2 ö
ç
÷
è R G2 ø , VCM is rejected, and VREF provides a level shift around which the output signal
ended output signal is in-phase with the differential input signal.
Copyright © 2011, Texas Instruments Incorporated
25
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
VINOPA 835
VSIG-
RF2
VCM
RF1
RG1
RG2
RG2
VSIG+
G[(VSIG+)-(VSIG-)]
RF2
VCM
OPA 835
VIN+
VOUT
OPA 835
RF1
VREF
VREF
Figure 55. Instrumentation Amplifier
Integrated solutions are available, but the OPA835 provides a much lower power high frequency solution. For
best CMRR performance, resistors must be matched. A rule of thumb is CMRR ≈ the resistor tolerance; so 0.1%
tolerance will provide about 60dB CMRR.
Input Common-Mode Voltage Range
When the primary design goal is a linear amplifier, with high CMRR, it is important to not violate the input
common-mode voltage range (VICR) of an op amp.
Common-mode input range low and high specifications in the table data use CMRR to set the limit. The limits are
chosen to ensure CMRR will not degrade more than 3dB below its limit if the input voltage is kept within the
specified range. The limits cover all process variations and most parts will be better than specified. The typical
specifications are from 0.2V below the negative rail to 1.1V below the positive rail.
Assuming the op amp is in linear operation the voltage difference between the input pins is very small (ideally
0V) and input common-mode voltage can be analyzed at either input pin and the other input pin is assumed to
be at the same potential. The voltage at VIN+ is easy to evaluate. In non-inverting configuration, Figure 51, the
input signal, VIN, must not violate the VICR. In inverting configuration, Figure 51, the reference voltage, VREF,
needs to be within the VICR.
The input voltage limits have fixed headroom to the power rails and track the power supply voltages. For with
single 5V supply the linear input voltage range is –0.2V to 3.9 V and with 2.7V supply it is –0.2V to 1.6V. The
delta from each power supply rail is the same in either case; –0.2V and 1.1V.
Output Voltage Range
The OPA835 and OPA2835 are rail-to-rail output RRO) op amps. Rail-to-rail output typically means the output
voltage can swing to within a couple hundred milli-volts of the supply rails. There are different ways to specify
this; one is with the output still in linear operation and another is with the output saturated. Saturated output
voltages are closer to the power supply rails than linear outputs, but the signal is not a linear representation of
the input. Linear output is a better representation of how well a device performs when used as a linear amplifier.
Both saturation and linear operation limits are affected by the current in the output, where higher currents lead to
more loss in the output transistors.
Data in the ELECTRICAL SPECIFICATIONS tables list both linear and saturated output voltage specifications
with 2kΩ load. Figure 11 and Figure 36 show saturated voltage swing limits versus output load resistance and
Figure 12 and Figure 37 show the output saturation voltage versus load current. Given a light load, the output
voltage limits have nearly constant headroom to the power rails and track the power supply voltages. For
example with 2kΩ load and single 5V supply the linear output voltage range is 0.15V to 4.8V and with 2.7V
supply it is 0.15V to 2.5V. The delta from each power supply rail is the same in either case; 0.15V and 0.2V.
With devices like the OPA835 and OPA2835, where the input range is lower than the output range, it is typical
that the input will limit the available signal swing only in non-inverting gain of 1. Signal swing in non-inverting
configurations in gains > +1 and inverting configurations in any gain is generally limited by the output voltage
limits of the op amp.
26
Copyright © 2011, Texas Instruments Incorporated
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
Split-Supply Operation (±1.25V to ±2.75V)
To facilitate testing with common lab equipment, the OPA835 EVM SLOU314 is built to allow for split-supply
operation. This configuration eases lab testing because the mid-point between the power rails is ground, and
most signal generators, network analyzers, oscilloscopes, spectrum analyzers and other lab equipment reference
their inputs and outputs to ground.
Figure 56 shows a simple non-inverting configuration analogous to Figure 51 with ±2.5V supply and VREF equal
to ground. The input and output will swing symmetrically around ground. Due to its ease of use, split supply
operation is preferred in systems where signals swing around ground, but it requires generation of two supply
rails.
+2.5 V
RG
VSIG
VOUT
OPA 835
Load
-2.5 V
RF
Figure 56. Split Supply Operation
Single-Supply Operation (2.5V to 5.5V)
Many newer systems use single power supply to improve efficiency and reduce the cost of the power supply.
OPA835 and OPA2835 are designed for use with single-supply power operation and can easily be used with
single-supply power with no change in performance from split supply as long as the input and output are biased
within the linear operation of the device.
To change the circuit from split supply to single supply, level shift of all voltages by 1/2 the difference between
the power supply rails. For example, changing from ±2.5V split supply to 5V single supply is shown conceptually
in Figure 57.
5V
VSIG
RG
VOUT
OPA 835
Load
RF
2.5 V
Figure 57. Single Supply Concept
A more practical circuit will have an amplifier or other circuit before to provide the bias voltage for the input and
the output provides the bias for the next stage.
Figure 58 shows a typical non-inverting amplifier situation. With 5V single supply, a mid supply reference
generator is needed to bias the negative side via RG. To cancel the voltage offset that would otherwise be
caused by the input bias currents, R1 is chosen to be equal to RF in parallel with RG. For example if gain of 2 is
required and RF = 2kΩ, select RG = 2kΩ to set the gain and R1 = 1kΩ for bias current cancellation. The value for
C is dependent on the reference, but at least 0.1µF is recommended to limit noise.
Copyright © 2011, Texas Instruments Incorporated
27
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
Signal and bias
from previous stage
VSIG
2.5 V
5V
R1
RO
OPA 835
5V
RG
2.5 V
REF
VOUT
GVSIG
2.5 V
C
RF
Signal and bias to
next stage
Figure 58. Non-Inverting Single Supply with Reference
Figure 59 shows a similar non-inverting single supply scenario with the reference generator replaced by the
Thevenin equivalent using resistors and the positive supply. RG’ and RG” form a resistor divider from the 5V
supply and are used to bias the negative side with their parallel sum equal to the equivalent RG to set the gain.
To cancel the voltage offset that would otherwise be caused by the input bias currents, R1 in is chosen to be
equal to RF in parallel with RG’ in parallel with RG” (R1=RF||RG’||RG”). For example if gain of 2 is required and RF
= 2kΩ, selecting RG’ = RG” = 4kΩ gives equivalent parallel sum of 2kΩ, sets the gain to 2, and references the
input to mid supply (2.5V). R1 is then set to 1kΩ for bias current cancellation. This can be lower cost, but note the
extra current draw required in the resistor divider.
Signal and bias
from previous stage
VSIG
2.5 V
5V
R1
RG’
5V
RO
OPA 835
VOUT
GVSIG
2.5 V
RG”
RF
Signal and bias to
next stage
Figure 59. Non-Inverting Single Supply with Resistors
Figure 60 shows a typical inverting amplifier situation. With 5V single supply, a mid supply reference generator is
needed to bias the positive side via R1. To cancel the voltage offset that would otherwise be caused by the input
bias currents, R1 is chosen to be equal to RF in parallel with RG. For example if gain of -2 is required and RF =
2kΩ, select RG = 1kΩ to set the gain and R1 = 665Ω for bias current cancellation. The value for C is dependent
on the reference, but at least 0.1µF is recommended to limit noise into the op amp.
28
Copyright © 2011, Texas Instruments Incorporated
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
5V
5V
R1
2.5 V
REF
RO
VOUT
OPA 835
C
GVSIG
2.5 V
RG
Signal and bias to
next stage
RF
VSIG
2.5 V
Signal and bias
from previous stage
Figure 60. Inverting Single Supply with Reference
Figure 61 shows a similar inverting single supply scenario with the reference generator replaced by the Thevenin
equivalent using resistors and the positive supply. R1 and R2 form a resistor divider from the 5V supply and are
used to bias the positive side. To cancel the voltage offset that would otherwise be caused by the input bias
currents, set the parallel sum of R1 and R2 equal to the parallel sum of RF and RG. C should be added to limit
coupling of noise into the positive input. For example if gain of –2 is required and RF = 2kΩ, select RG = 1kΩ to
set the gain. R1 = R2 = 1.33kΩ for mid supply voltage bias and for op amp input bias current cancellation. A good
value for C is 0.1µF. This can be lower cost, but note the extra current draw required in the resistor divider.
5V
5V
R1
RO
R2
C
OPA 835
VOUT
GVSIG
2.5 V
RG
VSIG
RF
Signal and bias to
next stage
2.5 V
Signal and bias
from previous stage
Figure 61. Inverting Single Supply with Resistors
Pulse Aplication with Single-Supply
For pulsed applications, where the signal is at ground and pulses to some positive or negative voltage, the circuit
bias voltage considerations are different than with a signal that swings symetrical about a reference point and the
circuit configuration should be adjusted accordingly. Figure 62 shows a pulsed situation where the signal is at
ground (0V) and pulses to a positive value.
Copyright © 2011, Texas Instruments Incorporated
29
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
Signal and bias
from previous stage
VSIG
0V
5V
R1
RO
VOUT
OPA 835
GVSIG
RG
0V
RF
Signal and bias to
next stage
Figure 62. Non-Inverting Single Supply with Pulse
If the input signal pulses negative from ground, an inverting amplifier is more appropriate as shown in Figure 63.
A key consideration in both non-inverting and inverting cases is that the input and output voltages are kept within
the limits of the amplifier, and since the VICR of the OPA835 includes the negative supply rail, the op amp lends
itself to this application.
5V
R1
OPA 835
VOUT
GVSIG
RG
Signal and bias
from previous stage
0V
VSIG
RO
0V
RF
Signal and bias to
next stage
Figure 63. Inverting Single Supply with Pulse
Power-Down Operation
The OPA835 and OPA2835 include a power-down mode. Under logic control, the amplifiers can be switched
from normal operation to a standby current of <1.5µA. When the PD pin is connected high, the amplifier is active.
Connecting PD pin low disables the amplifier, and places the output in a high impedance state. Note: the op
amp’s output in gain of +1 is high impedance similar to a 3-state high impedance gate, but in other gains the
feedback network is a parallel load.
The PD pin must be actively driven high or low and should not be left floating. If the power-down mode is not
used, PD should be tied to the positive supply rail.
PD logic states are TTL with reference to the negative supply rail, VS-. When the op amp is powered from single
supply and ground, driving from logic devices with similar VDD voltages to the op amp should not require any
special consideration. When the op amp is powered from split supply, VS- is below ground and an open collector
type of interface with pull-up resistor is more appropriate. Pull-up resistor values should be lower than 100k and
the drive logic should be negated due to the inverting action of an open collector gate.
30
Copyright © 2011, Texas Instruments Incorporated
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
Low Power Applications and the Efects of Resistor Values on Bandwidth
The OPA835 and OPA2835 are designed for the nominal value of RF to be 2 kΩ in gains other than +1. This
gives excellent distortion performance, maximum bandwidth, best flatness, and best pulse response. It also loads
the amplifier. For example; in gain of 2 with RF = RG = 2 kΩ, RG to ground, and VOUT = 4V, 1mA of current will
flow through the feedback path to ground. In gain of +1, RG is open and no current will flow to ground. In low
power applications, it is desirable to reduce this current by increasing the gain setting resistors values. Using
larger value gain resistors has two primary side effects (other than lower power) due to their interaction with
parasitic circuit capacitance.
1. Lowers the bandwidth.
2. Lowers the phase margin
(a) This will cause peaking in the frequency response.
(b) And will cause over shoot and ringing in the pulse response.
Figure 64 shows the small signal frequency response on OPA835EVM for non-inverting gain of 2 with RF and RG
equal to 2kΩ, 10kΩ, and 100kΩ. The test was done with RL = 2kΩ. Due to loading effects of RL, lower values
may reduce the peaking, but higher values will not have a significant effect.
21
Gain Magnitude - dB
VS = 5 V,
18 VOUT = 100 Vpp,
G = 2,
15 RL = 2 kW
RF = 100 kW
RF = 10 kW
12
9
RF = 2 kW
6
RF = 100 kW
CF = 1 pF
3
0
RF = 10 kW
CF = 1 pF
-3
-6
-9
0
1
10
100
f - Frequency - MHz
Figure 64. Frequency Response with Various Gain Setting Resistor Values
As expected, larger value gain resistors cause lower bandwidth and peaking in the response (peaking in
frequency response is synonymous with overshoot and ringing in pulse response). Adding 1pF capacitors in
parallel with RF helps compensate the phase margin and restores flat frequency response. Figure 65 shows the
test circuit used.
VIN
RG
OPA 835
VOUT
2 kW
RF
CF
Figure 65. G=2 Test Circuit for Various Gain Setting Resistor Values
Copyright © 2011, Texas Instruments Incorporated
31
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
Driving Capacitive Loads
The OPA835 and OPA2835 can drive up to a nominal capacitive load of 10pF on the output with no special
consideration. When driving capacitive loads greater than this, it is recommended to use a small resister (RO) in
series with the output as close to the device as possible. Without RO, capacitance on the output will interact with
the output impedance of the amplifier causing phase shift in the loop gain of the amplifier that will reduce the
phase margin. This will cause peaking in the frequency response and overshoot and ringing in the pulses
response. Interaction with other parasitic elements may lead to instability or oscillation. Inserting RO will isolate
the phase shift from the loop gain path and restore the phase margin; however, it will also limit the bandwidth.
Figure 66 shows the test circuit and Figure 40 shows the recommended values of RO versus capacitive loads,
CL. See Figure 39 for frequency response with various values.
RO
VIN
VOUT
OPA835
CL
2 kW
Figure 66. RO versus CL Test Circuit
Active Filters
The OPA835 and OPA2835 can be used to design active filters. Figure 68 and Figure 67 show MFB and
Sallen-Key circuits designed using FilterPro™ http://focus.ti.com/docs/toolsw/folders/print/filterpro.html to
implement 2nd order low-pass butterworth filter circuits. Figure 69 shows the frequency response.
1.82 kW
220 pF
1.82 kW
4.22 kW
OPA 835
1.5 nF
Figure 67. MFB 100kHz 2nd Order Low-Pass Butterworth Filter Circuit
2.2 nF
562 W
6.19 kW
330 pF
OPA835
Figure 68. Sallen-Key 100kHz 2nd Order Low-Pass Butterworth Filter Circuit
32
Copyright © 2011, Texas Instruments Incorporated
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
VS = 5 V,
VOUT = 100 mVpp
Gain Magnitude - dB
0
MFB
-10
-20
Sallen-Key
-30
-40
1k
10k
100k
1M
f - Frequency - Hz
Figure 69. MFB and Sallen-Key 2nd Order Low-Pass Butterworth Filter Response
MFB and Sallen-Key filter circuits offer similar performance. The main difference is the MFB is an inverting
amplifier in the pass band and the Sallen-Key is non-inverting. The primary pro for each is the Sallen-Key in unity
gain has no resistor gain error term, and thus no sensitivity to gain error, while the MFB has inherently better
attenuation properties beyond the bandwidth of the op amp.
Audio Frequency Performance
The OPA835 and OPA2835 provide excellent audio performance with very low quiescent power. To show
performance in the audio band, a 2700 series Audio Analyzer from Audio Precision was used to test THD+N and
FFT at 1VRMS output voltage. Figure 70 is the test circuit used. Note the 100pF capacitor to ground on the input
helped to decouple noise pick up in the lab and improved noise performance.
Figure 71 shows the THD+N performance with 100kΩ and 300Ω loads, and with no weighting and A-weighting.
With no weighting the THD+N performance is dominated by the noise for both loads. A-weighting provides
filtering that improves the noise so a larger difference can be seen between the loads due to more distortion with
RL = 300Ω.
Figure 72 and Figure 73 show FFT output with a 1kHz tone and 100kΩ and 300Ω loads. To show relative
performance of the device versus the test set, one channel has the OPA835 in line between generator output
and analyzer input and the other channel is in “Gen Mon” loopback mode, which internally connects the signal
generator to the analyzer input. With 100kΩ load, Figure 72, the curves are basically indistinguishable from each
other except for noise, which means the OPA835 cannot be directly measured. With 300Ω load, Figure 73, the
main difference between the curves is OPA835 shows higher even order harmonics, but odd order is masked by
the test set performance.
VIN
From AP
+2.5 V
VOUT
To AP
100 pF OPA 835
10 W
-2.5 V
Figure 70. OPA835 AP Analyzer Test Circuit
Copyright © 2011, Texas Instruments Incorporated
33
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
0
VS = 5 V,
VOUT = 1 VRMS,
-95 G = 1,
RF = 0 W,
BW = 80 kHz
-100
-20
-30
No weighting
RL = 300 W,
-40
RL = 100 kW
-105
A-weighting
RL = 300 W,
-110
VS = 5 V,
VOUT = 1 VRMS,
G = 1,
RF = 0 W
-10
FFT - dBV
THD+N - Total Harmonic Distortion + Noise - dBv
-90
-50
-60
-70
-80
-90
RL = 100 kW
-100
Gen Mon - 100k
-110
-115
-120
RL = 100k
-130
-120
10
-140
100
1k
f - Frequency - Hz
10k
0
100k
Figure 71. OPA835 1Vrms 20Hz to 80kHz THD+N
2k
4k
6k
8k
10k
12k
f - Frequency - Hz
14
16k
18k
20k
Figure 72. OPA835 and AP Gen Mon 1kHz FFT
Plot; VOUT = 1VRMS, RL = 100kΩ
0
VS = 5 V,
VOUT = 1 VRMS,
G = 1,
RF = 0 W
-10
-20
-30
-40
FFT - dBV
-50
-60
-70
-80
-90
Gen Mon - 300
-100
-110
RL = 300
-120
-130
-140
0
2k
4k
6k
8k
10k
12k
f - Frequency - Hz
14
16k
18k
20k
Figure 73. OPA835 and AP Gen Mon 1kHz FFT Plot;
VOUT = 1VRMS, RL = 300Ω
ADC Driver Performance
The OPA835 provides excellent performance when driving high performance delta-sigma (ΔΣ) and successive
approximation register (SAR) ADCs in low power audio and industrial applications.
34
Copyright © 2011, Texas Instruments Incorporated
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
OPA835 and ADS8326 Combined Performance
To show achievable performance, the OPA835 is tested as the drive amplifier for the ADS8326. The ADS8326 is
a 16-bit, micro power, SAR ADC with pseudo-differential inputs and sample rates up to 250kSPS. It offers
excellent noise and distortion performance in a small 8-pin SOIC or MSOP package. Low power and small size
make the ADS8326 and OPA835 an ideal solution for portable and battery-operated systems, for remote
data-acquisition modules, simultaneous multichannel systems, and isolated data acquisition.
The circuit shown in Figure 74 is used to test the performance, Figure 75 is the FFT plot with 10kHz input
frequency showing the spectral performance, and the tabulated AC analysis results are in Table 1.
2.7 V
VSIG
VSIG
0V
2.7V
4.02 k
2k
1.35 V
5V
VS+
VIN
2.5 V
100
OPA835
4.02 k
2.2 nF
VS-
+In VDD REF
ADS 8326
-In
2k
2k
Figure 74. OPA835 and ADS8326 Test Circuit
0
-20
AIN - dBc
-40
-60
-80
-100
-120
-140
0
20
40
60
80
f - Frequency - Hz
100
120
Figure 75. ADS8326 and OPA835 10kHz FFT
Table 1. AC Analysis
Tone (Hz)
Signal (dBFS)
SNR (dBc)
THD (dBc)
SINAD (dBc)
SFDR (dBc)
10k
–0.85
81.9
–87.5
80.8
89.9
Copyright © 2011, Texas Instruments Incorporated
35
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
Layout Recommendations
OPA835 EVM (SLOU314) should be used as a reference when designing the circuit board. It is recommended to
follow the EVM layout of the external components near to the amplifier, ground plane construction, and power
routing as closely as possible. General guidelines are:
1. Signal routing should be direct and as short as possible into an out of the op amp.
2. The feedback path should be short and direct avoiding vias if possible especially with G = +1.
3. Ground or power planes should be removed from directly under the amplifier’s negative input and output
pins.
4. A series output resistor is recommended to be placed as near to the output pin as possible. See
“Recommended Series Output Resistor vs. Capacitive Load” (Figure 40) for recommended values given
expected capacitive load of design.
5. A 2.2µF power supply decoupling capacitor should be placed within 2 inches of the device and can be
shared with other op amps. For spit supply, a capacitor is required for both supplies.
6. A 0.1µF power supply decoupling capacitor should be placed as near to the power supply pins as possible.
Preferably within 0.1 inch. For split supply, a capacitor is required for both supplies.
7. The PD pin uses TTL logic levels. If not used it should tied to the positive supply to enable the amplifier. If
used, it must be actively driven. A bypass capacitor is not necessary, but can be used for robustness in noisy
environments.
36
Copyright © 2011, Texas Instruments Incorporated
OPA835, OPA2835
SLOS713B – JANUARY 2011 – REVISED MAY 2011
www.ti.com
REVISION HISTORY
Changes from Revision A (March 2011) to Revision B
•
Page
Changed OPA835 from product preview to production data ................................................................................................ 1
Copyright © 2011, Texas Instruments Incorporated
37
PACKAGE OPTION ADDENDUM
www.ti.com
3-Jun-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
OPA835IDBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
OPA835IDBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
OPA835IRUNR
PREVIEW
QFN
RUN
10
3000
TBD
Call TI
Call TI
OPA835IRUNT
PREVIEW
QFN
RUN
10
250
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jun-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
OPA835IDBVR
SOT-23
DBV
6
3000
178.0
9.0
OPA835IDBVT
SOT-23
DBV
6
250
178.0
9.0
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.23
3.17
1.37
4.0
8.0
Q3
3.23
3.17
1.37
4.0
8.0
Q3
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jun-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA835IDBVR
SOT-23
DBV
6
3000
180.0
180.0
18.0
OPA835IDBVT
SOT-23
DBV
6
250
180.0
180.0
18.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
www.ti.com/audio
Communications and Telecom www.ti.com/communications
Amplifiers
amplifier.ti.com
Computers and Peripherals
www.ti.com/computers
Data Converters
dataconverter.ti.com
Consumer Electronics
www.ti.com/consumer-apps
DLP® Products
www.dlp.com
Energy and Lighting
www.ti.com/energy
DSP
dsp.ti.com
Industrial
www.ti.com/industrial
Clocks and Timers
www.ti.com/clocks
Medical
www.ti.com/medical
Interface
interface.ti.com
Security
www.ti.com/security
Logic
logic.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Power Mgmt
power.ti.com
Transportation and
Automotive
www.ti.com/automotive
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
Wireless
www.ti.com/wireless-apps
RF/IF and ZigBee® Solutions
www.ti.com/lprf
TI E2E Community Home Page
e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2011, Texas Instruments Incorporated