DS1077 EconOscillator/Divider www.maxim-ic.com PIN ASSIGNMENT FEATURES § § § § § § § § § § § § Processor-controlled or standalone solidstate oscillator Frequency changes on-the-fly Dual low-jitter, synchronous fixed frequency outputs 2-wire serial interface Frequency outputs 8.1kHz to 133MHz ±0.5% variation over temp (+25°C to +70°C) ±0.5% initial tolerance Nonvolatile (NV) frequency settings Single 5V supply No external components Power-down mode Synchronous output gating STANDARD FREQUENCY OPTION Note: x denotes package option DS1077x-133 133.333MHz to DS1077x-125 125.000MHz to DS1077x-120 120.000MHz to DS1077x-100 100.000MHz to DS1077x-66 66.666MHz to 16.2kHz 15.2kHz 14.6kHz 12.2kHz 8.1kHz OUT1 1 8 SCL OUT0 2 7 SDA VVCC DD 3 6 CTRL1 GND 4 5 CTRL0 150mil SO 118mil µSOP Package PIN DESCRIPTION OUT1 OUT0 VCC GND CTRL1 CTRL0 SDA SCL - Main Oscillator Output - Reference Output - Power Supply Voltage - Ground - Control Pin for OUT1 - Control Pin for OUT0 - 2-Wire Serial Data Input/Output - 2-Wire Serial Clock ORDERING INFORMATION Note: XXX denotes frequency option DS1077Z-XXX 8-Pin 150mil SO DS1077U-XXX 8-Pin 118mil µSOP DESCRIPTION The DS1077 is a dual-output, programmable, fixed-frequency oscillator requiring no external components for operation. The DS1077 can be used as a processor-controlled frequency synthesizer or as a standalone oscillator. The two synchronous output operating frequencies are user-adjustable in submultiples of the master frequency through the use of two on-chip programmable prescalers and a divider. The specific output frequencies chosen are stored in NV (EEPROM) memory. The DS1077 defaults to these values upon power-up. The DS1077 features a 2-wire serial interface that allows in-circuit on-the-fly programming of the programmable prescalers (P0 & P1) and divider (N) with the desired values being stored in NV (EEPROM) memory. Design changes can be accommodated in-circuit on-the-fly by simply programming different values into the device (or reprogramming previously programmed devices). Alternatively, for fixed frequency applications, previously programmed devices can be used and no connection to the serial interface is required. Pre-programmed devices can be ordered in customerrequested frequencies. The DS1077 is available in 8-pin SO or µSOP packages, allowing the generation of a clock signal easily, economically, and using minimal board area. Chip-scale packaging is also available on request. EconOscillator is a trademark of Dallas Semiconductor. 1 of 21 022703 DS1077 BLOCK DIAGRAM 1077 Figure1 CONTROL LOGIC (TABLE 1) SEL0 EN0 PDN0 INTERNAL OSCILLATOR Enable Select DIV1 MCLK Power-Down 0M1 0M0 1M1 CTRL0 P0 PRESCALER (M DIVIDER) MUX OUT0 1M0 EN0 SEL0 PDN0 0M1 0M0 DIV1 PDN1 CONTROL REGISTERS PROGRAMMABLE “N” DIVIDER P1 PRESCALER (M DIVIDER) 2-WIRE INTERFACE Power-Down 1M1 1M0 PDN1 SDA Enable CONTROL LOGIC (TABLE 2) SCL 2 of 21 OUT1 CTRL1 DS1077 OVERVIEW A block diagram of the DS1077 is shown in Figure 1. The DS1077 consists of four major components: 1) Internal Master Oscillator, 2) Prescalers, 3) Programmable Divider, and 4) Control Registers. The internal oscillator is factory-trimmed to provide a master frequency (Master CLK) that can be routed directly to the outputs (OUT0 & OUT1) or through separate prescalers (P0 & P1). OUT1 can also be routed through an additional divider (N). The Prescaler (P0) divides the Master Clock by 1, 2, 4, or 8 to be routed directly to the OUT0 pin. The Prescaler (P1) divides the Master Clock by 1, 2, 4, or 8, which can be routed directly to the OUT1 pin or to the Divider (N) input, which is then routed to the OUT1 pin. The Programmable Divider (N) divides the Prescaler Output (P1) by any number selected between 2 and 1025 to provide the Main Output (OUT1) or it can be bypassed altogether by use of the DIV1 register bit. The value of N is stored in the DIV register. The Control Registers are user-programmable through a 2-wire serial interface to determine operating frequency (values of P0, P1, & N) and modes of operation. The register values are stored in EEPROM and therefore only need to be programmed to alter frequencies and operating modes. PIN DESCRIPTIONS Output 1 (OUT1)—This pin is the main oscillator output; its frequency is determined by the control register settings for the prescaler P1 (mode bits 1M1 & 1M0) and divider N (DIV word). Output 0 (OUT0)—A reference output, OUT0, is taken from the output of the reference select Mux. Its frequency is determined by the control register settings for CTRL0 and values of Prescaler P0 (mode bits 0M1 & 0M0) (see Table 1). Control Pin 0 (CTRL0)—A multifunctional input pin that can be selected as a MUX SELECT, OUTPUT ENABLE and/or a POWER-DOWN. Its function is determined by the user-programmable control register values EN0, SEL0, and PDN0 (see Table 1). Control Pin 1 (CTRL1)—A multifunctional input pin that can be selected as a OUTPUT ENABLE and/or a POWER-DOWN. Its function is determined by the user-programmable control register value of PDN1 (see Table 2). Serial Data Input/Output (SDA)—Input/Output pin for the 2-wire serial interface used for data transfer. Serial Clock Input (SCL)—Input pin for the 2-wire serial interface used to synchronize data movement on the serial interface. 3 of 21 DS1077 DEVICE MODE USING OUT0 Table 1 EN0 (BIT) SEL0 (BIT) PDN0 (BIT) 0 0 0 CTRL0 (PIN) 1 OUT0 (PIN) HI-Z 0 HI-Z CTRL0 FUNCTION POWERDOWN* DEVICE MODE POWER-DOWN ACTIVE 1 MCLK/M MUX SELECT ACTIVE 0 MCLK 1 HI-Z OUTPUT 1 0 0 ACTIVE ENABLE 0 MCLK 1 HI-Z OUTPUT 1 1 0 ACTIVE** ENABLE 0 MCLK/M 1 HI-Z POWER-DOWN POWERX 0 1 DOWN 0 MCLK ACTIVE 1 HI-Z POWER-DOWN POWERX 1 1 DOWN 0 MCLK/M ACTIVE *This mode is for applications where OUT0 is not used, but CTRL0 is used as a device shutdown. **Default Condition 0 1 0 DEVICE MODE USING OUT1 Table 2 PDN1 (BIT) CTRL1 (PIN) CTRL1 FUNCTION OUT1 DEVICE MODE 0 0 OUTPUT ENABLE OUT CLK ACTIVE** 0 1 OUTPUT ENABLE HI-Z ACTIVE** 1 0 POWER-DOWN OUT CLK ACTIVE 1 1 POWER-DOWN HI-Z POWER-DOWN **Default Condition NOTE: Both CTRL0 and CTRL1 can be configured as power-downs. They are internally “OR” connected so that either of the control pins can be used to provide a power-down function for the whole device, subject to appropriate settings of the PDN0 and PDN1 register bits (see Table 3). 4 of 21 DS1077 SHUTDOWN CONTROL WITH PDN0 AND PDN1 Table 3 PDN0 PDN1 SHUTDOWN CONTROL (BIT) (BIT) 0 0 NONE* 0 1 CTRL1 1 0 CTRL0 1 1 CTRL0 OR CTRL1 *CTRL0 performs a power-down if SEL0 and EN0 are both 0 (see Table 1). REGISTER FUNCTIONS The user programmable registers can be programmed by the user to determine the mode of operation (MUX), operating frequency (DIV), and bus settings (BUS). Details of how these registers are programmed can be found in a later section; in this section the functions of the registers are described. The register settings are nonvolatile, the values being stored automatically or as required in EEPROM when the registers are programmed via the SDA and SCL pins. MUX WORD MSB Name * PDN1 Default 0 0 setting PDN0 0 SEL0 1 EN0 1 0M1 0 0M0 0 LSB 1M1 0 MSB LSB 1M0 DIV1 - - - - - 0 0 x x x x x x first data byte second data byte *This bit must be set to zero. DIV1 (bit) This bit allows the output of the Prescaler P1 to be routed directly to the OUT1 pin (DIV1 = 1). The N divider is bypassed so the programmed value of N is ignored. If DIV1 = 0 (default) the N divider functions normally. 0M1, 0M0, 1M1, 1M0 (bits) These bits set the prescalers P0 and P1, to divide by 1, 2, 4, or 8 (see Table 4). PRESCALER DIVISOR M SETTINGS Table 4 0M1 0M0 0 0 0 Prescaler P0 Divisor “M” Prescaler P1 Divisor “M” 1M1 1M0 1** 0 0 1** 1 2 0 1 2 1 0 4 1 0 4 1 1 8 1 1 8 **Default Condition 5 of 21 DS1077 EN0 (bit) (Default EN0 = 1) 1) If EN0 = 1 and PDN0 = 0 the CTRL0 pin functions as an Output Enable for OUT0, the frequency of the output being determined by the SEL0 bit. 2) If PDN0 = 1, the EN0 bit is ignored, CTRL0 will function as a power-down, and output OUT0 will always be enabled on power-up, its frequency being determined by the SEL0 bit. 3) If EN0 = 0 the function of CTRL0 is determined by the SEL0 and PDN0 bits (see Table 1). SEL0 (Default SEL0 = 1) 1) If SEL0 = 1 and EN0 = PDN0 = 0, the CTRL0 pin determines the state of the MUX (i.e., the output frequency of OUT0). 2) If CTRL0 = 0 the output will be the Master clock frequency. 3) If CTRL0 = 1 the output will be the output frequency of the M prescaler. 4) If either EN0 or PDN0 = 1 then SEL0 determines the frequency of OUT0 when it is enabled. 5) If SEL0 = 0 the output will be the Master clock frequency. 6) If SEL0 = 1 the output will be the output frequency of the M prescaler (see Table 1). PDN0 (Default PDN0 = 0) 1) This bit (if set to 1) causes CTRL0 to perform a power-down function, regardless of the setting of the other bits. 2) If PDN0 = 0 the function of CTRL0 is determined by the values of EN0 and SEL0. NOTE: When EN0 = SEL0 = PDN0 = 0, CTRL0 also functions as a power-down. This is a special case where all the OUT0 circuitry is disabled even when the device is powered up for power to saving when OUT0 is not used (see Table 1). PDN1 (Default PDN1 = 0) 1) If PDN1 = 1, CTRL1 will function as a power-down. 2) If PDN1 = 0, CTRL1 functions as an output enable for OUT1 only (see Table 2.) NOTE (ON OUTPUT ENABLE AND POWER-DOWN): 1) Both enables are “smart” and wait for the output to be low before going to Hi-Z. 2) Power-down sequence first disables both outputs before powering down the device. 3) On power-up the outputs are disabled until the clock has stabilized (~8000 cycles). 4) In power-down mode, the device cannot be programmed. 5) A power-down command must persist for at least two cycles of the lowest output frequency plus 10ms. 6 of 21 DS1077 DIV WORD MSB N9 N8 N7 N6 N5 N4 first data byte N3 LSB MSB N2 N1 N0 X X X X second data byte X LSB X N These ten bits determine the value of the programmable divider (N). The range of divisor values is from 2 to 1025, and is equal to the programmed value of N plus 2 (see Table 5). PROGRAMMABLE DIVISOR N VALUES Table 5 BIT VALUE 0 000 000 000** 0 000 000 001 1 111 111 111 **Default Condition DIVISOR (N) 2 3 1025 BUS WORD Name Factory Default 0* 0* 0* *These bits are reserved and must be set to zero. 0* WC 0 A0, A1, A2 A2 0 A1 0 A0 0 (Default Setting = 000) These are the device select bits that determine the address of the device. WC (Default Setting WC = 0) This bit determines when/if the EEPROM is written to after register contents have been changed. If WC = 0 the EEPROM is written automatically after a write register command. If WC = 1 the EEPROM is only written when the “WRITE ” command is issued. Regardless of the value of the WC bit, the value of the BUS Register (A0, A1, A2) is always written immediately to the EEPROM. 7 of 21 DS1077 2-WIRE SERIAL DATA BUS The DS1077 supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the message is called a “master.” The devices that are controlled by the master are “slaves.” The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS1077 operates as a slave on the 2-wire bus. Connections to the bus are made via the open-drain I/O lines, SDA and SCL. A pull-up resistor (5kW) is connected to SDA. The following bus protocol has been defined (See Figure 2): § Data transfer may be initiated only when the bus is not busy. § During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is high will be interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain HIGH. Start data transfer: A change in the state of the data line from HIGH to LOW while the clock is HIGH defines a START condition. Stop data transfer: A change in the state of the data line from LOW to HIGH while the clock line is HIGH defines the STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited, and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Within the bus specifications a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate) are defined. The DS1077 works in both modes. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the byte has been received. The master device must generate an extra clock pulse, which is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. When the DS1077 EEPROM is being written to, it will not be able to perform additional responses. In this case, the slave DS1077 will send a notacknowledge to any data transfer request made by the master. It will resume normal operation when the EEPROM operation is complete. A master must signal an end-of-data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. 8 of 21 DS1077 DATA TRANSFER ON 2-WIRE SERIAL BUS Figure 2 SDA MSB slave address R/W direction bit acknowledgement signal from receiver acknowledgement signal from receiver SCL 1 START CONDITION 2 6 7 8 9 1 2 3-8 ACK 8 9 ACK repeated if more bytes are transferred STOP CONDITION OR REPEATED START CONDITION Figure 2 details how data transfer is accomplished on the 2-wire bus. Depending upon the state of the R/ W bit, two types of data transfer are possible: 1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next, follows a number of data bytes. The slave returns an acknowledge bit after each received byte. 2) Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. Next, follows a number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not acknowledge is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus will not be released. The DS1077 may operate in the following two modes: 1) Slave receiver mode: Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after the slave address and direction bit have been received. 2) Slave transmitter mode: The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit will indicate that the transfer direction is reversed. Serial data is transmitted on SDA by the DS1077 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. 9 of 21 DS1077 SLAVE ADDRESS A control byte is the first byte received following the START condition from the master device. The control byte consists of a 4-bit control code; for the DS1077, this is set as 1011 binary for read and write operations. The next three bits of the control byte are the device select bits (A2, A1, A0) and can be written to the EEPROM. They are used by the master device to select which of eight devices are to be accessed. The select bits are in effect the three least significant bits of the slave address. The last bit of the control byte (R/ W ) defines the operation to be performed. When set to a one a read operation is selected, and when set to a zero, a write operation is selected. Following the START condition, the DS1077 monitors the SDA bus, checking the device type identifier being transmitted. Upon receiving the 1011 code (changeable with one mask) and appropriate device select bits, the slave device outputs an acknowledge signal on the SDA line. 10 of 21 DS1077 2-WIRE SERIAL COMMUNICATION WITH DS1077 Figure 3 Send a “Standalone” Command SCL SDA S 1 Start 0 1 1 A2 A1 A0 W Address Byte A C7 C6 C5 C4 C3 C2 C1 C0 DS1077 ACK Command Byte A P DS1077 Stop ACK Write MSB of a Two-Byte Register SCL SDA S 1 0 Start 1 1 A2 A1 A0 W Address Byte A C7 C6 C5 C4 C3 C2 C1 C0 DS1077 ACK Command Byte A D7 D6 D5 D4 D3 D2 D1 D0 DS1077 ACK MSByte A P DS1077 Stop ACK Write to a Two-Byte Register SCL SDA S 1 0 Start 1 1 A2 A1 A0 W Address Byte A C7 C6 C5 C4 C3 C2 C1 C0 DS1077 ACK Command Byte A D7 D6 D5 D4 D3 D2 D1 D0 DS1077 ACK MSByte A D7 D6 D5 D4 D3 D2 D1 D0 DS1077 ACK LSByte A P DS1077 Stop ACK Write a Single Byte to an Addressed Register SCL SDA S 1 0 Start 1 1 A2 A1 A0 W Control Byte A C7 C6 C5 C4 C3 C2 C1 C0 DS1077 ACK Command Byte A A7 A6 A5 A4 A3 A2 A1 A0 DS1077 ACK Byte Address A D7 D6 D5 D4 D3 D2 D1 D0 DS1077 ACK Data Byte A DS1077 Stop ACK Write Multiple Bytes to an Addressed Register SCL SDA S Start 1 0 1 1 A2 A1 A0 W Control Byte A C7 C6 C5 C4 C3 C2 C1 C0 DS1077 ACK Command Byte A A7 A6 A5 A4 A3 A2 A1 A0 DS1077 ACK Starting Byte Address SCL SDA D7 D6 D5 D4 D3 D2 D1 D0 Byte (n+1) A D7 D6 D5 D4 D3 D2 D1 D0 DS1077 ACK Byte N A P DS1077 Stop ACK 11 of 21 A D7 D6 D5 D4 D3 D2 D1 D0 DS1077 ACK Byte n P A DS1077 ACK DS1077 2-WIRE SERIAL COMMUNICATION WITH DS1077 Figure 3 (continued) Read Single Byte Register or MSB from a Two-Byte Register SCL SDA S 1 0 Start 1 1 A2 A1 A0 W Control Byte A C7 C6 C5 C4 C3 C2 C1 C0 DS1077 ACK Command Byte A R 1 0 1 1 A2 A1 A0 Rd DS1077 Repeated Control Byte ACK Start A D7 D6 D5 D4 D3 D2 D1 D0 DS1077 ACK MSByte N Master Stop NACK Read from a Two-Byte Register SCL SDA S 1 0 Start 1 1 A2 A1 A0 W Control Byte A C7 C6 C5 C4 C3 C2 C1 C0 DS1077 ACK Command Byte A R 1 0 1 1 A2 A1 A0 Rd DS1077 Repeated Control Byte ACK Start A D7 D6 D5 D4 D3 D2 D1 D0 DS1077 ACK MSByte A Master ACK SCL D7 D6 D5 D4 D3 D2 D1 D0 SDA LSByte N P Master Stop NACK Read Multiple Bytes from an Addressed Register SCL SDA S 1 Start 0 1 1 A2 A1 A0 W Control Byte A C7 C6 C5 C4 C3 C2 C1 C0 DS1077 ACK Command Byte A A7 A6 A5 A4 A3 A2 A1 A0 DS1077 ACK A R 1 0 1 1 A2 A1 A0 Rd Starting Byte Address DS1077 Repeated Control Byte ACK Start SCL SDA D7 D6 D5 D4 D3 D2 D1 D0 Byte n A D7 D6 D5 D4 D3 D2 D1 D0 Master ACK Byte (n+1) A D7 D6 D5 D4 D3 D2 D1 D0 Master ACK Byte N 12 of 21 N P Master Stop NACK P A DS1077 ACK DS1077 COMMAND SET Data and control information is read from and written to the DS1077 in the format shown in Figure 3. To write to the DS1077, the master will issue the slave address of the DS1077 and the R/ W bit will be set to 0. After receiving an acknowledge, the bus master provides a command protocol. After receiving this protocol, the DS1077 will issue an acknowledge, and then the master may send data to the DS1077. If the DS1077 is to be read, the master must send the command protocol as before, and then issue a repeat START condition and then the control byte again, this time with the R/W bit set to 1 to allow reading of the data from the DS1077. The command set for the DS1077 is as follows: Access DIV [01] If R/ W is 0, this command writes to the DIV register. After issuing this command, the next data byte value is to be written into the DIV register. If R/ W is 1, the next data byte read is the value stored in the DIV register. Access MUX [02] If R/ W is 0, this command writes to the MUX register. After issuing this command, the next data byte value is to be written into the MUX register. If R/ W is 1, the next data byte read is the value stored in the MUX register. Access BUS [0D] If R/ W is 0, this command writes to the BUS register. After issuing this command, the next data byte value is to be written into the BUS register. If R/ W is 1, the next data byte read is the value stored in the BUS register. Write E2 [3F] If WC = 0 the EEPROM is automatically written to at the end of each command. This is a DEFAULT condition. In this case the command WRITE E2 is not needed. If WC = 1, the EEPROM is only written when the WRITE E2 command is issued. On receipt of the WRITE E2 command the contents of the DIV and MUX registers are written into the EEPROM, thus locking in the register settings. EXCEPTION: The bus register is always automatically written to EEPROM after a write, regardless of the value of WC. APPLICATION INFORMATION Power-Supply Decoupling To achieve best results, decouple the power supply with 0.01µF and 0.1µF high-quality, ceramic, surfacemount capacitors as close as possible to VCC/GND of the device. Surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications. Current Consumption The active supply current can be significantly reduced by disabling OUT0 when not required and setting its prescaler to divide by 8. Likewise, bypassing OUT1’s divider (and using only the prescaler) also significantly reduces the supply current. 13 of 21 DS1077 ABSOLUTE MAXIMUM RATINGS Voltage on Any Pin Relative to Ground Operating Temperature Range Programming Temperature Range Storage Temperature Range Soldering Temperature -0.5V to 6.0V -40°C to +85°C 0°C to +70°C -55°C to +125°C See IPC/JEDEC J-STD-020A Specification DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Supply Voltage VCC High-Level Output Voltage (OUT1,OUT0) Low-Level Output Voltage (OUT1,OUT0) High-Level Input Voltage (CTRL1, CTRL0) High-Level Input Voltage (SDA, SCL) Low-Level Input Voltage (CTRL1, CTRL0) Low-Level Input Voltage (SDA, SCL) High-Level Input Current (CTRL1, CTRL0, SDA, SCL) Low-Level Input Current (CTRL1, CTRL0, SDA, SCL) Supply Current (Active) Standby Current (Power-Down) CONDITION VOH IOH = -4mA, VCC = min VOL IOL = 4mA (TA = -40°C to +85°C, VCC = 5V ±5%) MIN TYP MAX UNITS NOTES 4.75 5 5.25 V 1 2.4 V 0.4 V VIH 2.1 VCC+ 0.3V V VIH 0.7Vcc VCC+ 0.3V V VIL -0.3V 0.8 V VIL -0.3V 0.3Vcc IIH VIH = VCC = 5.25V 1 µA IIL VCC = 5.25V, VIL= 0 ICC ICCQ CL = 15pF (Both Outputs) (-40°C to +85°C) Power-Down Mode 14 of 21 -1 µA 2 50 mA 5 µA 10 DS1077 AC ELECTRICAL CHARACTERISTICS PARAMETER Output Frequency Tolerance Over Temperature SYMBOL ∆fO Output Frequency Tolerance Over Voltage ∆fO Combined Freq. Variation ∆fO Output Frequency Min Output Frequency Max fOUT (TA = -40°C to +85°C; VCC = 5V ±5%) CONDITION MIN TYP MAX VCC = 5V, 25°C -0.5 0 +0.5 VCC = 5V, 70°C -0.5 0 +0.5 VCC = 5V, -3.3 -40°C to +25°C VCC = 5V, -1.4 +25°C to +85°C VCC = 4.75V, -1.0 25°C VCC = 5.25V, 25°C Over Temp (0°C to +70°C) -1.65 & Voltage 8.13 +2.7 UNITS NOTES % 11 +1.4 -0.7 % +0.7 +1.0 +1.25 % 133 kHz MHz 2 Power-Up Time tPOR + tSTAB 0.1 1 ms 5 Enable OUT1 from PDN tSTAB 0.1 1 ms 3 Enable OUT0 from PDN tSTAB 0.1 1 ms 3 OUT1 Hi-Z from PDN tHiZ 1 ms 3 OUT0 Hi-Z from PDN tHiZ 1 ms 3 Load Capacitance CL 50 pF 4 60 % 15 Output Duty Cycle (OUT1, OUT0) Output Jitter 40 fOUT=133MHz M=1; DIV1=1 CL=12pF 3 sigma pk-topk 15 of 21 30 psec DS1077 AC ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE (-40°C to +85°C; VCC= 5V±5%) PARAMETER SYMBOL CONDITION SCL Clock Frequency fSCL Bus Free Time Between a STOP and START Condition Hold Time (Repeated) START Condition LOW Period of SCL tBUF Fast Mode Standard Mode Fast Mode Standard Mode tHD:STA tLOW HIGH Period of SCL tHIGH Set-Up Time for a Repeated START Data Hold Time tSU:STA tHD:DAT Data Set-Up Time tSU:DAT Rise Time of Both SDA and SCL Signals Fall Time of Both SDA and SCL Signals Set-Up Time For STOP Capacitive Load for Each Bus Line Input Capacitance tR tF tSU:STO Fast Mode Standard Mode Fast Mode Standard Mode Fast Mode Standard Mode Fast Mode Standard Mode Fast Mode Standard Mode Fast Mode Standard Mode Fast Mode Standard Mode Fast Mode Standard Mode Fast Mode Standard Mode MIN TYP MAX 400 100 UNITS NOTES kHz 1.3 4.7 µs 0.6 4.0 1.3 4.7 0.6 4.0 0.6 4.7 0 0 100 250 µs 6 µs µs µs 0.9 µs 7,8 ns 300 1000 300 20 + 0.1CB 20 + 0.1CB 0.6 4.0 ns 9 ns 9 µs CB 400 CI 5 pF 9 pF NONVOLATILE MEMORY CHARACTERISTICS PARAMETER Writes SYMBOL CONDITION +85°C MIN 10,000 TYP MAX UNITS NOTES NOTES: 1) 2) 3) 4) 5) 6) All voltages are referenced to ground. 8.13kHz is obtained from a -66MHz standard part. PDN is a power-down signal applied to either CTRL0 or CTRL1 pins as appropriate. Output voltage swings may be impaired at high frequencies combined with high output loading. After this period, the first clock pulse is generated. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH MIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. 7) The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. 16 of 21 DS1077 8) A fast mode device can be used in a standard mode system, but the requirement tSU:DAT>250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR MAX + tSU:DAT = 1000ns + 250ns = 1250ns before the SCL line is released. 9) CB is the total capacitance of one bus line in pF. 10) OUT0 and OUT1 are operating at oscillator master frequency without divider. 11) Typical frequency shift due to aging is ±0.5%. Aging stressing includes Level 3 preconditioning with 1000 temperature cycles of -55°C to +125°C, 336hr max VCC biased +125°C bake. Level 3 preconditioning consists of a 24hr +125°C storage bake, 192hr moisture soak at +30°C/60% R.H., and three solder reflow passes. TIMING DIAGRAM SDA tBUF tLOW tHD:STA tR tF t SP SCL t HD:STA STOP START t HD:DAT tHIGH t SU:DAT t SU:STO t SU:STA REPEATED START ORDERING INFORMATION DS1077 133 = 125 = 120 = 100 = 66 = 133.333MHz 125.000MHz 120.000MHz 100.000MHz 66.666MHz Z= U= SO µSOP Example: DS1077Z-100 17 of 21 DS1077 TYPICAL OPERATING CHARACTERISTICS (VCC = 5.0V, T = +25°C, unless otherwise specified) SUPPLY CURRENT vs. VOLTAGE 45.00 40.00 CURRENT (mA) 35.00 30.00 25.00 20.00 15.00 DS1077-133 10.00 DS1077-100 5.00 DS1077-66 0.00 4.5 4.7 4.9 5.1 5.3 5.5 VOLTAGE (V) SUPPLY CURRENT vs. DIVISOR (N) DS1077-133 34 32 CURRENT (mA) 30 28 26 24 4.75V 5.0V 22 5.25V 20 0 200 400 600 800 DIVISOR (N) 18 of 21 1000 DS1077 TYPICAL OPERATING CHARACTERISTICS (continued) (VCC = 5.0V, T = +25°C, unless otherwise specified) SUPPLY CURRENT vs. DIVISOR (N) 35 30 CURRENT (mA) 25 20 15 10 DS1077-133 DS1077-100 5 DS1077-66 0 0 200 400 600 800 1000 DIVISOR (N) SUPPLY CURRENT vs. TEMPERATURE 45 CURRENT (mA) 40 35 30 DS1077-133 DS1077-100 25 DS1077-66 20 0 10 20 30 40 50 TEMPERAT URE (C) 19 of 21 60 70 DS1077 TYPICAL OPERATING CHARACTERISTICS (continued) (VCC = 5.0V, T = +25°C, unless otherwise specified) TEMPCO 2 1.5 % Change from 25C 1 0.5 0 -0.5 DS1077-133 DS1077-100 -1 DS1077-66 MUX=3040h DIV=0000h -1.5 -2 0 10 20 30 40 50 60 70 TEMPERAT URE (C) VOLTCO 2.00 % CHANGE FROM 5V 1.50 1.00 0.50 0.00 -0.50 DS1077-133 -1.00 -1.50 DS1077-100 MUX=3040h DIV=0000h DS1077-66 -2.00 4.75 4.85 4.95 5.05 VOLTAGE (V) 20 of 21 5.15 5.25 DS1077 TYPICAL OPERATING CHARACTERISTICS (continued) (VCC = 5.0V, T = +25°C, unless otherwise specified) SHUTDOWN CURRENT vs. TEMPERATURE 4 3.5 CURRENT (µA) 3 2.5 2 1.5 DS1077-66 1 0.5 0 0 10 20 30 40 T EMPERAT URE (C) 21 of 21 50 60 70