TLC59401 www.ti.com SBVS137 – DECEMBER 2009 16-CHANNEL LED DRIVER WITH DOT CORRECTION AND GRAYSCALE PWM CONTROL Check for Samples: TLC59401 FEATURES APPLICATIONS • • • • • • 1 23 • • • • • • • • 16 Channels 12-Bit (4096 Steps) Grayscale PWM Control Dot Correction – 6-Bit (64 Steps) Drive Capability (Constant-Current Sink) – 0 mA to 80 mA (VCC ≤ 3.6 V) – 0 mA to 120 mA (VCC > 3.6 V) LED Power-Supply Voltage up to 17 V VCC = 3.0 V to 5.5 V Serial Data Interface Controlled Inrush Current 30-MHz Data Transfer Rate CMOS Level I/O Error Information – LOD: LED Open Detection – TEF: Thermal Error Flag VCC GND SCLK Monocolor, Multicolor, Full-Color LED Displays LED Signboards Display Back-Lighting DESCRIPTION The TLC59401 is a 16-channel, constant-current sink, LED driver. Each channel has an individually adjustable 4096-step grayscale PWM brightness control and a 64-step constant-current sink (dot correction). The dot correction adjusts the brightness variations between LED channels and other LED drivers. Both grayscale control and dot correction are accessible via a serial interface. A single external resistor sets the maximum current value of all 16 channels. The TLC59401 features two error information circuits. The LED open detection (LOD) indicates a broken or disconnected LED at an output terminal. The thermal error flag (TEF) indicates an over-temperature condition. XLAT SIN CNT MODE 1 0 IREF Max. OUTn Current V REF =1.24V GS Register MODE 1 0 11 0 GSCLK BLANK 0 DC Register 5 GS Counter 0 Status Information: LOD, TED, DC DATA 191 0 CNT 96 12−Bit Grayscale PWM Control Constant-Current Driver OUT0 Delay x0 6−Bit Dot Correction LED Open Detection Input Shift Register CNT 192 192 GS Register 23 96 95 1 0 96 12 DC Register 11 12−Bit Grayscale PWM Control Constant-Current Driver OUT1 Delay x1 6−Bit Dot Correction 6 MODE LED Open Detection 96 Temperature Error Flag (TEF) LED Open Detection (LOD) CNT Input Shift Register GS Register 191 XERR 180 DC Register 95 12−Bit Grayscale PWM Control Constant-Current Driver OUT15 Delay x15 6−Bit Dot Correction 90 191 LED Open Detection SOUT Figure 1. Functional Block Diagram 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments Incorporated. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated TLC59401 SBVS137 – DECEMBER 2009 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) (1) TA PACKAGE PART NUMBER –40°C to +85°C 28-pin HTSSOP PowerPAD™ TLC59401PWP –40°C to +85°C 32-pin 5 mm x 5 mm QFN TLC59401RHB For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. TLC59401 VI Input voltage range (2) IO Output current (dc) VI Input voltage range VO Output voltage range ESD rating VCC UNIT –0.3 to 6 V 130 mA V(BLANK), V(SCLK), V(XLAT), V(MODE), V(SIN), V(GSCLK), V(IREF), V(TEST) –0.3 to VCC +0.3 V V(SOUT), V(XERR) –0.3 to VCC +0.3 V V(OUT0) to V(OUT15) HBM (JEDEC JESD22-A114, human body model) CDM (JEDEC JESD22-C101, charged device model) TJ(max) Operating junction temperature –0.3 to 18 V 2 kV 500 V +150 °C °C TSTG Storage temperature range –55 to +150 TA Operating ambient temperature range –40 to +85 °C HTSSOP (PWP) (4) 31.58 °C/W QFN (RHB) (4) 35.9 °C/W Package thermal impedance (3) (1) (2) (3) (4) 2 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. The package thermal impedance is calculated in accordance with JESD 51-7. With PowerPAD soldered on PCB with 2-oz. trace of copper. See TI application report SLMA002 for further information. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC59401 TLC59401 www.ti.com SBVS137 – DECEMBER 2009 RECOMMENDED OPERATING CONDITIONS PARAMETER TEST CONDITIONS MIN NOM MAX UNIT DC CHARACTERISTICS VCC Supply Voltage 3 5.5 V VO Voltage applied to output (OUT0 – OUT15) VIH 17 V High-level input voltage 0.8 VCC VCC V VIL Low-level input voltage GND 0.2 VCC V IOH High-level output current VCC = 5 V at SOUT IOL Low-level output current VCC = 5 V at SOUT, XERR OUT0 to OUT15, VCC ≤ 3.6 V –1 mA 1 mA 80 mA IOLC Constant output current 120 mA TJ Operating junction temperature –40 +125 °C TA Operating free-air temperature range –40 +85 °C OUT0 to OUT15, VCC > 3.6 V AC CHARACTERISTICS At VCC = 3 V to 5.5 V and TA = –40°C to +85°C, unless otherwise noted. f(SCLK) Data shift clock frequency SCLK 30 MHz f(GSCLK) Grayscale clock frequency GSCLK 30 MHz twh0/twl0 SCLK pulse duration SCLK = high/low (see Figure 12) 16 ns twh1/twl1 GSCLK pulse duration GSCLK = high/low (see Figure 12) 16 ns twh2 XLAT pulse duration XLAT = high (see Figure 12) 20 ns twh3 BLANK pulse duration BLANK = high (see Figure 12) 20 ns tsu0 SIN - SCLK↑ (see Figure 12) tsu1 SCLK↓ - XLAT↑ (see Figure 12) 10 tsu2 MODE↑↓ - SCLK↑ (see Figure 12) 10 MODE↑↓ - XLAT↑ (see Figure 12) 10 tsu4 BLANK↓ - GSCLK↑ (see Figure 12) 10 tsu5 XLAT↑ - GSCLK↑ (see Figure 12) 30 th0 SCLK↑ - SIN (see Figure 12) th1 XLAT↓ - SCLK↑ (see Figure 12) 10 tsu3 th2 Setup time Hold Time 5 ns 3 SCLK↑ - MODE↑↓ (see Figure 12) 10 th3 XLAT↓ - MODE↑↓ (see Figure 12) 10 th4 GSCLK↑ - BLANK↑ (see Figure 12) 10 ns DISSIPATION RATINGS (1) PACKAGE POWER RATING TA < +25°C DERATING FACTOR ABOVE TA = +25°C POWER RATING TA = +70°C POWER RATING TA = +85°C 28-pin HTSSOP with PowerPAD soldered (1) 3958 mW 31.67 mW/°C 2533 mW 2058 mW 28-pin HTSSOP without PowerPAD soldered 2026 mW 16.21 mW/°C 1296 mW 1053 mW 32-pin QFN (1) 3482 mW 27.86 mW/°C 2228 mW 1811 mW The PowerPAD is soldered to the PCB with a 2-oz. copper trace. See application report SLMA002 for further information. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC59401 3 TLC59401 SBVS137 – DECEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS At VCC = 3 V to 5.5 V and TA = –40°C to +85°C, unless otherwise noted. TLC59401 PARAMETER TEST CONDITIONS VOH High-level output voltage IOH = –1 mA, SOUT VOL Low-level output voltage IOL = 1 mA, SOUT II Input current MIN TYP VI = VCC or GND; BLANK, TEST, GSCLK, SCLK, SIN, XLAT pin –1 VI = GND; MODE pin –1 Supply current V 1 μA 1 μA 50 μA 0.9 6 mA No data transfer, all output OFF, VO = 1 V, R(IREF) = 1.3 kΩ 5.2 12 mA Data transfer 30 MHz, all output ON, VO = 1 V, R(IREF) = 1.3 kΩ 16 25 mA Data transfer 30 MHz, all output ON, VO = 1 V, R(IREF) = 640 Ω 30 60 mA 61 69 mA 0.1 μA ±1 ±4 % Constant output current All output ON, VO = 1 V, R(IREF) = 640 Ω Ilkg Leakage output current All output OFF, VO = 15 V, R(IREF) = 640 Ω , OUT0 to OUT15 54 All output ON, VO = 1 V, R(IREF) = 640 Ω, OUT0 to OUT15, –20°C to +85°C (1) All output ON, VO = 1 V, R(IREF) = 640 Ω, OUT0 to OUT15 Constant sink current error 0.5 No data transfer, all output OFF, VO = 1 V, R(IREF) = 10 kΩ IO(LC) ΔIO(LC0) UNIT V VI = VCC; MODE pin ICC MAX VCC – 0.5 (1) ±1 ±8 All output ON, VO = 1 V, R(IREF) = 320 Ω, VCC > 3.6 V, OUT0 to OUT15, –20°C to +85°C (1) ±1 ±6 All output ON, VO = 1 V, R(IREF) = 320 Ω, VCC > 3.6 V, OUT0 to OUT15 (1) ±1 ±8 % ΔIO(LC1) Constant sink current error Device to device, averaged current from OUT0 to OUT15, R(IREF) = 1920 Ω (20 mA) (2) –2, +0.4 ±4 % ΔIO(LC2) Constant sink current error Device to device, averaged current from OUT0 to OUT15, R(IREF) = 480 Ω (80 mA) (2) –2.7, +2 ±4 % All output ON, VO = 1 V, R(IREF) = 640 Ω OUT0 to OUT15, VCC = 3 V to 5.5 V (3) ±1 ±4 %/V All output ON, VO = 1 V, R(IREF) = 320 Ω OUT0 to OUT15, VCC > 3.6 V (3) ±1 ±6 %/V ΔIO(LC3) Line regulation All output ON, VO = 1 V to 3 V, R(IREF) = 640 Ω, OUT0 to OUT15 (4) ±2 ±6 %/V ΔIO(LC4) Load regulation All output ON, VO = 1 V to 3 V, R(IREF) = 320 Ω, VCC > 3.6 V, OUT0 to OUT15 (4) ±2 ±8 %/V T(TEF) Thermal error flag threshold Junction temperature (5) V(LED) LED open detection threshold V(IREF) Reference voltage output (1) (2) (3) (4) (5) 4 R(IREF) = 640 Ω +150 1.20 +170 °C 0.3 0.4 V 1.24 1.28 V The deviation of each output from the average of OUT0-15 constant current. It is calculated by Equation 1 in Table 1. The deviation of average of OUT1-15 constant current from the ideal constant-current value. It is calculated by Equation 2 in Table 1. The ideal current is calculated by Equation 3 in Table 1. The line regulation is calculated by Equation 4 in Table 1. The load regulation is calculated by Equation 5 in Table 1. Not tested. Specified by design. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC59401 TLC59401 www.ti.com SBVS137 – DECEMBER 2009 Table 1. Test Parameter Equations D(%) = D(%) = I OUTn - I OUTavg _ 0 -15 IOUTavg _ 0 -15 IOUTavg - I OUT (IDEAL ) I OUT (IDEAL ) ´ 100 (1) ´ 100 (2) æ 1.24 V ö ÷÷ IOUT (IDEAL ) = 31.5 ´ çç è R IREF ø D(% / V ) = D(% / V ) = (3) (IOUTn at VCC = 5.5 V ) - (I OUTn at VCC = 3.0 V ) 100 ´ (I OUTn at VCC = 3.0 V ) 2.5 (4) (IOUTn at VOUTn = 3.0 V ) - (IOUTn at VOUTn = 1.0 V ) 100 ´ (IOUTn at VOUTn = 1.0 V ) 2 .0 (5) SWITCHING CHARACTERISTICS At VCC = 3 V to 5.5 V, CL = 15 pF, and TA = –40°C to 85°C, unless otherwise noted. PARAMETER tr0 tr1 tf0 tf1 Rise time Fall time TEST CONDITIONS MIN TYP SOUT MAX 16 OUTn, VCC = 5 V, TA = +60°C, DCn = 3Fh 10 SOUT 30 16 OUTn, VCC = 5 V, TA = +60°C, DCn = 3Fh 10 30 UNIT ns ns tpd0 SCLK - SOUT (see Figure 12) 30 ns tpd1 BLANK - OUT0 (see Figure 12) 60 ns tpd2 1000 ns tpd3 GSCLK - OUT0 (see Figure 12) 60 ns tpd4 XLAT - IOUT (dot correction) (see Figure 12) 60 ns 20 30 ns –50 10 ns td ton_err Propagation delay time OUTn - XERR (see Figure 12) Output delay time OUTn - OUT(n+1) (see Figure 12) Output on-time error touton – Tgsclk (see Figure 12), GSn = 01h, GSCLK = 11 MHz –90 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC59401 5 TLC59401 SBVS137 – DECEMBER 2009 www.ti.com PIN CONFIGURATIONS PWP PACKAGE 28-PIN HTSSOP PowerPAD (TOP VIEW) XLAT 3 26 TEST SCLK 4 25 GSCLK SIN 5 24 MODE 6 OUT0 7 OUT1 8 OUT2 TEST IREF IREF 27 VCC 2 NC BLANK (1) VCC NC 28 GND 1 BLANK GND XLAT RHB PACKAGE 32-PIN 5 mm × 5 mm QFN (TOP VIEW) 32 31 30 29 28 27 26 25 SCLK 1 24 GSCLK SOUT SIN 2 23 SOUT 23 XERR MODE 3 22 XERR 22 OUT15 OUT0 4 21 OUT15 21 OUT14 OUT1 5 20 OUT14 9 20 OUT13 OUT2 6 19 OUT13 OUT3 10 19 OUT12 OUT3 7 18 OUT12 OUT4 11 18 OUT11 OUT4 8 17 OUT11 OUT5 12 17 OUT10 OUT6 13 16 OUT9 OUT7 14 15 OUT8 9 10 11 12 13 14 15 16 OUT6 OUT7 NC NC OUT8 OUT9 OUT10 Thermal Pad OUT5 Thermal Pad (1) NC = no connection. 6 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC59401 TLC59401 www.ti.com SBVS137 – DECEMBER 2009 TERMINAL FUNCTION TERMINAL PWP RHB NAME NO. NO. I/O DESCRIPTION BLANK 2 31 I Blank all outputs. When BLANK is high, all OUTn outputs are forced OFF. GS counter is also reset. When BLANK is low, OUTn are controlled by the grayscale PWM control. GND 1 30 G Ground GSCLK 25 24 I Reference clock for grayscale PWM control IREF 27 26 I/O NC - 12, 13, 28, 29 OUT0 7 4 O Constant-current output. Multiple outputs can be configured in parallel to increase the constant-current capability. Different voltages can be applied to each output. OUT1 8 5 O Constant-current output OUT2 9 6 O Constant-current output OUT3 10 7 O Constant-current output OUT4 11 8 O Constant-current output OUT5 12 9 O Constant-current output OUT6 13 10 O Constant-current output OUT7 14 11 O Constant-current output OUT8 15 14 O Constant-current output OUT9 16 15 O Constant-current output OUT10 17 16 O Constant-current output OUT11 18 17 O Constant-current output OUT12 19 18 O Constant-current output OUT13 20 19 O Constant-current output OUT14 21 20 O Constant-current output OUT15 22 21 O Constant-current output SCLK 4 1 I Serial data shift clock Reference current terminal. The maximum current for the outputs OUT0-OUT15 is set with a resistor from IREF to GND. Any capacitance does not need to be connected between IREF and GND. No connection SIN 5 2 I Serial data input SOUT 24 23 O Serial data output TEST 26 25 I Test pin: TEST must be connected to VCC VCC 28 27 I Power-supply voltage MODE 6 3 I Input mode-change pin. When MODE = GND, the device is in GS mode. When MODE = VCC, the device is in DC mode. XERR 23 22 O Error output. XERR is an open-drain terminal. XERR goes low when LOD or TEF is detected. XLAT 3 32 I Level triggered latch signal. When XLAT is high, the TLC59401 writes data from the input shift register to either GS register (MODE is low) or DC register (MODE is high). When XLAT is low, the data in the GS or DC registers are held constant and do not change. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC59401 7 TLC59401 SBVS137 – DECEMBER 2009 www.ti.com PARAMETER MEASUREMENT INFORMATION PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS Resistor values are equivalent resistance and not tested. INPUT EQUIVALENT CIRCUIT (BLANK, XLAT, SCLK, SIN, GSCLK, TEST) OUTPUT EQUIVALENT CIRCUIT (SOUT) VCC 23 400 INPUT SOUT 23 GND GND INPUT EQUIVALENT CIRCUIT (IREF) OUTPUT EQUIVALENT CIRCUIT (XERR) VCC _ 400 INPUT 23 Amp XERR + 100 GND GND INPUT EQUIVALENT CIRCUIT (VCC) OUTPUT EQUIVALENT CIRCUIT (OUT) OUT INPUT GND GND INPUT EQUIVALENT CIRCUIT (MODE) INPUT GND Figure 2. Input and Output Equivalent Circuits 8 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC59401 TLC59401 www.ti.com SBVS137 – DECEMBER 2009 PARAMETER MEASUREMENT INFORMATION (continued) t wh0 , t wIO, twh1, twl1, tsu0 t su4, th4 V(LED) = 4 V SOUT Test Point RL = 51 CL = 15 pF OUTn Test Point CL = 15 pF IOLC, IOLC3, IOLC4 V(LED) = 1 V OUT0 VCC = 0 V ~ 7 V OUTn + _ OUT15 IREF Test Point RIREF = 640 Figure 3. Parameter Measurement Circuits Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC59401 9 TLC59401 SBVS137 – DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS REFERENCE RESISTOR vs OUTPUT CURRENT POWER DISSIPATION RATE vs FREE-AIR TEMPERATURE 4k 10 k TLC59401PWP PowerPAD Soldered 7.68 kW 1.92 kW 1k 0.96 kW 0.64 kW 0.48 kW 0.38 kW Power Dissipation Rate - mW Reference Resistor, R(IREF) - W TLC59401RHB 0.32 kW 100 0 20 40 60 80 100 3k 2k TLC59401PWP PowerPAD Unsoldered 1k 0 120 -40 IO - Output Current - mA -20 0 40 20 Figure 4. Figure 5. OUTPUT CURRENT vs OUTPUT VOLTAGE OUTPUT CURRENT vs OUTPUT VOLTAGE 140 65 TA = +25°C, VCC = 5 V IO = 120 mA 80 100 IO = 60 mA, VCC = 5 V 64 120 TA = +85°C 63 IO = 100 mA 100 IO - Output Current - mA IO - Output Current - mA 60 TA - Free-Air Temperature - °C IO = 80 mA 80 IO = 60 mA 60 IO = 40 mA 40 62 61 TA = +25°C 60 TA = -40°C 59 58 IO = 20 mA 57 IO = 5 mA 56 20 0 55 0 0.5 1.0 1.5 2.0 2.5 3.0 0 VO - Output Voltage - V 1.0 1.5 2.0 2.5 3.0 VO - Output Voltage - V Figure 6. 10 0.5 Figure 7. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC59401 TLC59401 www.ti.com SBVS137 – DECEMBER 2009 TYPICAL CHARACTERISTICS (continued) CONSTANT OUTPUT CURRENT, ΔIOLC vs AMBIENT TEMPERATURE CONSTANT OUTPUT CURRENT, ΔIOLC vs OUTPUT CURRENT 8 8 TA = +25°C, VCC = 5 V IO = 60 mA 6 D IOLC - Constant Output Current - % D IOLC - Constant Output Current - % 6 4 VCC = 3.3 V 2 0 -2 VCC = 5 V -4 4 2 0 -2 -4 -6 -6 -8 -40 -8 0 -20 20 40 60 80 0 100 20 60 80 Figure 8. Figure 9. OUTPUT CURRENT vs DOT CORRECTION LINEARITY (ABS Value) OUTPUT CURRENT vs DOT CORRECTION LINEARITY (ABS Value) 140 70 TA = +25°C, VCC = 5 V IO = 60 mA, VCC = 5 V IO = 120 mA 120 TA = +25°C 60 100 IO - Output Current - mA IO - Output Current - mA 40 IO - Output Current - mA TA - Ambient Temperature - °C IO = 80 mA 80 IO = 60 mA 60 40 IO = 30 mA 20 50 TA = +85°C TA = -40°C 40 30 20 10 IO = 5 mA 0 0 0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70 Dot Correction Data - dec Dot Correction Data - dec Figure 10. Figure 11. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC59401 11 TLC59401 SBVS137 – DECEMBER 2009 www.ti.com PRINCIPLES OF OPERATION SERIAL INTERFACE The TLC59401 has a flexible serial interface, which can be connected to microcontrollers or digital signal processors in various ways. Only three pins are needed to input data into the device. The rising edge of SCLK signal shifts the data from the SIN pin to the internal register. After all data are clocked in, a high-level pulse of XLAT signal latches the serial data to the internal registers. The internal registers are level-triggered latches of XLAT signal. All data are clocked in MSB first. The length of serial data is 96 bit or 192 bit, depending on the programming mode. Grayscale data and dot correction data can be entered during a grayscale cycle. Although new grayscale data can be clocked in during a grayscale cycle, the XLAT signal should only latch the grayscale data at the end of the grayscale cycle. Latching in new grayscale data immediately overwrites the existing grayscale data. Figure 12 shows the serial data input timing chart. More than two TLC59401s can be connected in series by connecting an SOUT pin from one device to the SIN pin of the next device. An example of cascading two TLC59401s is shown in Figure 13 and the timing chart is shown in Figure 14. The SOUT pin can also be connected to the controller to receive status information from TLC59401, as shown in Figure 22. MODE DC Data Input Mode GS Data Input Mode th3 tsu3 twh2 XLAT 1st GS Data Input Cycle SIN DC MSB DC LSB SCLK GS1 LSB tsu2 th2 GS2 MSB GS2 LSB th1 tsu1 1 96 1 2nd GS Data Input Cycle GS1 MSB 192 GS3 MSB tsu0 twh0 193 th0 193 192 1 tpd0 twl0 - SOUT DC MSB - GS1 MSB - 1 SID1 SID1 MSB MSB-1 SID2 SID2 MSB MSB-1 SID1 GS2 LSB MSB twh3 BLANK First GS Data Output Cycle tsu5 GSCLK Second GS Data Output Cycle 1 tpd4 1 4096 tpd3 tpd1 tpd3 + td td tpd1 + td twl1 Tgsclk tpd3 OUT0 (current) twh1 tsu4 th4 touton OUT1 (current) 15 x td tpd1 + 15 x td OUT15 (current) tpd2 XERR Figure 12. Serial Data Input Timing Chart SIN(a) SIN SOUT TLC59401 (a) SIN SOUT SOUT(b ) TLC59401 (b) SCLK, XLAT, BLANK, GSCLK, MODE , , Figure 13. Cascading Two TLC59401 Devices 12 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC59401 TLC59401 www.ti.com SBVS137 – DECEMBER 2009 MODE XLAT SIN(a) SCLK DCb MSB DCa LSB GSb1 MSB 192 1 1 GSa1 LSB 384 - 385 GSa2 LSB GSb3 MSB 385 384 1 1 192X2 96X2 SOUT(b) GSb2 MSB DCb MSB - GSb1 MSB - SIDb1 SIDb1 MSB MSB-1 SIDa1 LSB SIDb2 SIDb2 MSB MSB-1 GSb2 MSB BLANK 1 GSCLK 1 4096 OUT0 (current) OUT1 (current) OUT15 (current) XERR Figure 14. Timing Chart for Two Cascaded TLC59401 Devices ERROR INFORMATION OUTPUT The open-drain output XERR is used to report both of the TLC59401 error flags, TEF and LOD. During normal operation, the internal transistor connected to the XERR pin is turned off. The voltage on XERR is pulled up to VCC through an external pull-up resistor. If TEF or LOD is detected, the internal transistor is turned on, and XERR is pulled to GND. Because XERR is an open-drain output, multiple ICs can be ORed together and pulled up to VCC with a single pull-up resistor. This capability reduces the number of signals needed to report a system error (see Figure 22). To differentiate the LOD and TEF signal from the XERR pin, LOD can be masked out with BLANK pulled high. Table 2. XERR Truth Table ERROR CONDITION ERROR INFORMATION TEMPERATURE OUTn VOLTAGE TEF LOD TJ < T(TEF) Don't care Low X TJ > T(TEF) Don't care High X OUTn > V(LED) Low Low OUTn < V(LED) Low High OUTn > V(LED) High Low OUTn < V(LED) High High TJ < T(TEF) TJ > T(TEF) SIGNALS BLANK High XERR High Low High Low Low Low Low Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC59401 13 TLC59401 SBVS137 – DECEMBER 2009 www.ti.com TEF: THERMAL ERROR FLAG The TLC59401 provides a temperature error flag (TEF) circuit to indicate an over-temperature condition of the IC. If the junction temperature exceeds the threshold temperature (+160°C typical), TEF goes high and the XERR pin goes to a low level. When the junction temperature becomes lower than the threshold temperature, TEF goes low and the XERR pin becomes high impedance. The TEF status can also be read out from the TLC59401 status register. LOD: LED OPEN DETECTION The TLC59401 has an LED-open detection circuit that detects broken or disconnected LEDs. The LED open detector pulls the XERR pin to GND when an open LED is detected. XERR and the corresponding error bit in the Status Information Data is only active under the following open LED conditions: 1. OUTn is on and the time tpd2 (1 μs typical) has passed. 2. The voltage of OUTn is < 0.3V (typical) The LOD status of each output can be also read out from the SOUT pin. See the Status Information Output section for details. The LOD error bits are latched into the Status Information Data when XLAT returns to a low state after a high state. Therefore, the XLAT pin must be pulsed high, then low while XERR is active in order to latch the LOD error into the Status Information Data for subsequent reading via the serial shift register. DELAY BETWEEN OUTPUTS The TLC59401 has graduated delay circuits between outputs. These circuits can be found in the constant-current driver block of the device (see Figure 1). The fixed-delay time is 20 ns (typical), OUT0 has no delay, OUT1 has 20 ns delay, and OUT2 has 40 ns delay, etc. The maximum delay is 300 ns from OUT0 to OUT15. The delay works during switch on and switch off of each output channel. These delays prevent large inrush currents which reduces the bypass capacitors when the outputs turn on. OUTPUT ENABLE All OUTn channels of the TLC59401 can be switched off with one signal. When BLANK is set high, all OUTn channels are disabled, regardless of logic operations of the device. The grayscale counter is also reset. When BLANK is set low, all OUTn channels work under normal conditions. If BLANK goes low and then back high again in less than 300 ns, all outputs programmed to turn on do so for either the programmed number of grayscale clocks or the length of time that the BLANK signal was low, whichever is lower. For example, if all outputs are programmed to turn on for 1 ms, but the BLANK signal is only low for 200 ns, all outputs turn on for 200 ns even though some outputs are turning on after the BLANK signal has already gone high. Table 3. BLANK Signal Truth Table 14 BLANK OUT0 - OUT15 Low Normal condition High Disabled Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC59401 TLC59401 www.ti.com SBVS137 – DECEMBER 2009 SETTING MAXIMUM CHANNEL CURRENT The maximum output current per channel is programmed by a single resistor, R(IREF), which is placed between IREF pin and GND pin. The voltage on IREF is set by an internal band gap V(IREF) with a typical value of 1.24 V. The maximum channel current is equivalent to the current flowing through R(IREF) multiplied by a factor of 31.5. The maximum output current can be calculated by Equation 6: V (IREF) I max + 31.5 R (IREF) (6) where: V(IREF) = 1.24 V R(IREF) = User-selected external resistor. Imax must be set between 5 mA and 120 mA. The output current may be unstable if Imax is set lower than 5 mA. Output currents lower than 5 mA can be achieved by setting Imax to 5 mA or higher and then using dot correction. See Figure 4 for the maximum output current IO versus R(IREF). R(IREF) is the value of the resistor between IREF terminal to GND, and IO is the constant output current of OUT0 to OUT15. A variable power supply may be connected to the IREF pin through a resistor to change the maximum output current per channel. The maximum output current per channel is 31.5 times the current flowing out of the IREF pin. POWER DISSIPATION CALCULATION The device power dissipation must be below the power dissipation rate of the device package to ensure correct operation. Equation 7 calculates the power dissipation of device: P D ǒ + V CC I Ǔ ) ǒVOUT CC I MAX N DCn 63 d PWM Ǔ (7) where: VCC: device supply voltage ICC: device supply current VOUT: TLC59401 OUTn voltage when driving LED current IMAX: LED current adjusted by R(IREF) Resistor DCn: maximum dot correction value for OUTn N: number of OUTn driving LED at the same time dPWM: duty cycle defined by BLANK pin or GS PWM value OPERATING MODES The TLC59401 has two operating modes defined by MODE as shown in Table 4. The GS and DC registers are set to random values that are not known immediately after power on. The GS and DC values must be programmed before turning on the outputs. Please note that when initially setting GS and DC data after power on, the GS data must be set before the DC data is set. Failure to set GS data before DC data may result in losing the first bit of GS data. XLAT must be low when the MODE pin goes high-to-low or low-to-high to change back and forth between GS mode and DC mode. Table 4. TLC59401 Operating Modes Truth Table MODE INPUT SHIFT REGISTER OPERATING MODE GND 192 bit Grayscale PWM Mode VCC 96 bit Dot Correction Data Input Mode Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC59401 15 TLC59401 SBVS137 – DECEMBER 2009 www.ti.com SETTING DOT CORRECTION The TLC59401 has the capability to fine-adjust the output current of each channel (OUT0 to OUT15) independently. This feature is also called dot correction. This feature is used to adjust the brightness deviations of LEDs connected to the output channels OUT0 to OUT15. Each of the 16 channels can be programmed with a 6-bit word. The channel output can be adjusted in 64 steps from 0% to 100% of the maximum output current Imax. The TEST pin must be connected to VCC to ensure proper operation of the dot correction circuitry. Equation 8 determines the output current for each output n: I + I max DCn OUTn 63 (8) where: Imax = the maximum programmable output current for each output. DCn = the programmed dot correction value for output n (DCn = 0 to 63). n = 0 to 15 Figure 15 shows the dot correction data packet format which consists of 6 bits x 16 channel, total 96 bits. The format is Big-Endian format. In this format, the MSB is transmitted first, followed by the MSB-1, etc. The DC 15.5 in Figure 15 stands for the fifth-most significant bit for output 15. MSB LSB 0 5 6 89 90 95 DC 15.5 DC 15.0 DC 14.5 DC 1.0 DC 0.5 DC 0.0 DC OUT15 DC OUT0 DC OUT14 − DC OUT1 Figure 15. Dot Correction Data Packet Format When MODE is set to VCC, the TLC59401 enters the dot correction data input mode. The length of the input shift register becomes 96 bits. After all serial data are shifted in, the TLC59401 writes the data in the input shift register to the DC register when XLAT is high, and holds the data in the DC register when XLAT is low. The DC register is a level-triggered latch of the XLAT signal. Because XLAT is a level-triggered signal, SCLK and SIN must not be changed while XLAT is high. After XLAT goes low, data in the DC register are latched and do not change. The BLANK signal does not need to be high to latch in new data. When XLAT goes high, the new dot-correction data immediately become valid and change the output currents if BLANK is low. XLAT has a setup time (tsu1) and a hold time (th1) to SCLK, as shown in Figure 12. 16 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC59401 TLC59401 www.ti.com SBVS137 – DECEMBER 2009 To input data into the dot correction register, MODE must be set to VCC. The internal input shift register is then set to 96-bit width. After all serial data are clocked in, a rising edge of XLAT is used to latch the data into the dot correction register. Figure 16 shows the dc data input timing chart. DC Mode Data Input Cycle n DC Mode Data Input Cycle n+1 VCC MODE SIN DC n−1 LSB DC n MSB DC n MSB−1 DC n MSB−2 DC n LSB+1 DC n LSB DC n+1 MSB DC n+1 MSB−1 twh0 SCLK 1 2 3 95 96 1 2 twl0 SOUT DC n−1 MSB DC n−1 MSB−1 DC n−1 MSB−2 DC n−1 LSB+1 DC n−1 LSB tsu1 DC n MSB DC n MSB−1 DC n MSB−2 twh2 th1 XLAT Figure 16. Dot Correction Data Input Timing Chart When the IC is powered on, the data in the input shift register and DC register are not set to any default values. Therefore, DC data must be written to the DC register before turning on the constant-current output. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC59401 17 TLC59401 SBVS137 – DECEMBER 2009 www.ti.com SETTING GRAYSCALE The TLC59401 can adjust the brightness of each channel OUTn using a PWM control scheme. The use of 12 bits per channel results in 4096 different brightness steps, from 0% to 100% brightness. Equation 9 determines the brightness level for each output n: Brightness in % + GSn 100 4095 (9) where: GSn = the programmed grayscale value for output n (GSn = 0 to 4095) n = 0 to 15 Grayscale data for all OUTn The input shift register enters grayscale data into the grayscale register for all channels simultaneously. The complete grayscale data format consists of 16 × 12 bit words, which forms a 192-bit wide data packet (see Figure 17). The data packet must be clocked in MSB first. MSB 0 11 12 179 180 LSB 191 GS 15.11 GS 15.0 GS 14.11 GS 1.0 GS 0.11 GS 0.0 GS OUT15 GS OUT14 − GS OUT1 GS OUT0 Figure 17. Grayscale Data Packet Format When MODE is set to GND, the TLC59401 enters grayscale data input mode. The device switches the input shift register to 192-bit width. After all data are clocked in, a rising edge of the XLAT signal latches the data into the grayscale register (see Figure 18). New grayscale data immediately become valid at the rising edge of the XLAT signal; therefore, new grayscale data should be latched at the end of a grayscale cycle when BLANK is high. The first GS data input cycle after dot correction requires an additional SCLK pulse after the XLAT signal to complete the grayscale update cycle. All GS data in the input shift register are replaced with status information data (SID) after updating the grayscale register. DC Mode Data Input Cycle Following GS Mode Data Input Cycle First GS Mode Data Input Cycle After DC Data Input Cycle MODE t h3 t h3 t su3 XLAT t wh2 SIN GS MSB DC LSB GS n + 1 LSB t h1 t h2 SCLK GS + 1 MSB GS LSB t su1 t su2 1 96 192 193 1 192 t pd0 n SOUT DC LSB DC MSB X X GS MSB SID MSB SID MSB−1 SID LSB SID n + 1 MSB Figure 18. Grayscale Data Input Timing Chart When the IC is powered on, the data in the input shift register and GS register are not set to any default values. Therefore, GS data must be written to the GS register before turning on the constant-current output. 18 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC59401 TLC59401 www.ti.com SBVS137 – DECEMBER 2009 STATUS INFORMATION OUTPUT The TLC59401 has a status information register, which can be accessed in grayscale mode (MODE = GND). After the XLAT signal latches the data into the GS register, the input shift register data are replaced with the status information data (SID) of the device (see Figure 18). LOD, TEF, and dot-correction register data can be read out at the SOUT pin. The status information data packet is 192 bits wide. Bits 0 to 15 contain the LOD status of each channel. Bit 16 contains the TEF status. Bits 24 to 119 contain the data of the dot-correction register. The remaining bits are reserved. The complete status information data packet is shown in Figure 19. SOUT outputs the MSB of the SID at the same time the SID are stored in the SID register, as shown in Figure 20. The next SCLK pulse, which is the clock for receiving the MSB of the next grayscale data, transmits MSB-1 of the SID. If the output voltage is less than 0.3 V (typical) when the output sink current turns on, the LOD status flag becomes active. The LOD status flag is an internal signal that pulls the XERR pin low when the LOD status flag becomes active. The delay time, tpd2 (1 μs maximum), is the period from the time of turning on the output sink current to the time the LOD status flag becomes valid. The timing for each channel LOD status to become valid is shifted by the 30-ns (maximum), channel-to-channel turn-on time. After the first GSCLK goes high, OUT0 LOD status is valid; tpd3 + tpd2 = 60 ns + 1 μs = 1.06 μs. OUT1 LOD status is valid; tpd3 + td + tpd2 = 60 ns + 30 ns + 1 μs = 1.09 μs. OUT2 LOD status is valid; tpd3 + (2 × td) + tpd2 = 1.12 μs, and so on. It takes 1.51 μs maximum (tpd3 + (15 × td) + tpd2) from the first GSCLK rising edge until all LOD become valid; tsuLOD must be greater than 1.51 μs (see Figure 20) to ensure that all LOD data are valid. MSB LSB 0 15 16 LOD 15 LOD 0 TEF LOD Data 23 X X TEF 24 DC 15.5 119 120 191 DC 0.0 X X DC Values Reserved Figure 19. Status Information Data Packet Format Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC59401 19 TLC59401 SBVS137 – DECEMBER 2009 www.ti.com MODE GS Data Input Mode tsuLOD > tpd3 + td ´ 15 + tpd2 tsuLOD XLAT First GS Data Input Cycle Second GS Data Input Cycle SIN GS1 MSB GS1 LSB SCLK 1 192 SOUT - - GS2 MSB 193 GS1 MSB GS2 LSB 192 1 SID1 MSB SID1 MSB-1 SID1 LSB GS2 MSB (1st GS Data Output Cycle) BLANK GSCLK 4096 1 tpd3 OUT0 (current) td OUT1 (current) 15 x td OUT15 (current) tpd2 XERR tpd3 + 15 x td + tpd2 Figure 20. Readout Status Information Data (SID) Timing Chart The LOD status of each output can be read out from the SOUT pin. The LOD error bits are latched into the Status Information Data when XLAT returns to a low after a high. Therefore, the XLAT pin must be pulsed high then low while XERR is active in order to latch the LOD error into the Status Information Data for subsequent reading via the serial shift register. 20 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC59401 TLC59401 www.ti.com SBVS137 – DECEMBER 2009 GRAYSCALE PWM OPERATION The grayscale PWM cycle starts with the falling edge of BLANK. The first GSCLK pulse after BLANK goes low increases the grayscale counter by one and switches on all OUTn with a grayscale value not equal to zero. Each following rising edge of GSCLK increases the grayscale counter by one. The TLC59401 compares the grayscale value of each output OUTn with the grayscale counter value. All OUTn with grayscale values equal to the counter values are switched off. A high BLANK signal after 4096 GSCLK pulses resets the grayscale counter to zero and completes the grayscale PWM cycle ,as Figure 21 shows. When the counter reaches a count of FFFh, the counter stops counting and all outputs turn off. Pulling BLANK high before the counter reaches FFFh immediately resets the counter to zero. If there are any unconnected outputs (OUTn), including LEDs in a failed short or failed open condition, the GS data corresponding to the unconnected output should be set to '0' before turning on the LEDs. Otherwise, the VCC supply current (ICC) increases while the constant-current output is on. GS PWM Cycle n BLANK t wl1 t wh1 t h4 GSCLK 1 OUT0 (Current) OUT1 (Current) t pd1 t pd1 + td GS PWM Cycle n+1 2 t pd3 4096 3 t wl1 t wh3 t su4 1 t pd3 nxt d t pd3+ n x t d t pd1 + 15 x td OUT15 (Current) t pd2 XERR Figure 21. Grayscale PWM Cycle Timing Chart Output On-Time The amount of time that each output is turned on is a function of the grayscale clock frequency and the programmed grayscale PWM value. The on-time of each output can be calculated using Equation 10. GSn T _ on n = + t on _ err f( GSCLK ) (10) where: T_onn is the time that OUTn turns on and sinks current GSn is the OUTn programmed grayscale PWM value between 0 and 4095 ton_err is the output on-time error defined in the Switching Characteristics Table Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC59401 21 TLC59401 SBVS137 – DECEMBER 2009 www.ti.com When using Equation 10 with very high GSCLK frequencies and very low grayscale PWM values, the resulting T_on-time may be negative. If T_on is negative, the output does not turn on. For example, using f(GSCLK) = 30 MHz, GSn = 1, and the typical ton_err = 50 ns, Equation 10 calculates that OUTn turns on for –16.6 ns. This output may not turn on under these conditions. Increasing the PWM value or reducing the GSCLK clock frequency ensures turn-on. SERIAL DATA TRANSFER RATE Figure 22 shows a cascading connection of n TLC59401 devices connected to a controller, building a basic module of an LED display system. There is no TLC59401 limitation to the maximum number of ICs that can be cascaded. The maximum number of cascading TLC59401 devices depends on the application system. Equation 11 calculates the minimum frequency needed: f + 4096 f (GSCLK) (update) f (SCLK) + 193 f (update) n (11) where: f(GSCLK): minimum frequency needed for GSCLK f(SCLK): minimum frequency needed for SCLK and SIN f(update): update rate of whole cascading system n: number cascaded of TLC59401 device APPLICATION EXAMPLE VCC V(LED) V(LED) V(LED) V(LED) 100 k OUT0 SIN XERR XERR SCLK SCLK XLAT GSCLK MODE BLANK SOUT OUT15 SIN SOUT XERR VCC VCC SCLK 100 nF GSCLK IREF BLANK IC 0 TLC59401 IREF MODE VCC TEST 100 nF XLAT TLC59401 MODE VCC OUT0 SOUT XLAT GSCLK Controller OUT15 SIN BLANK TEST IC n 6 Figure 22. Cascading Devices 22 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC59401 PACKAGE OPTION ADDENDUM www.ti.com 23-Dec-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLC59401PWP ACTIVE HTSSOP PWP 28 TLC59401PWPR ACTIVE HTSSOP PWP TLC59401RHBR ACTIVE QFN TLC59401RHBT ACTIVE QFN 50 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR RHB 32 250 CU NIPDAU Level-2-260C-1 YEAR Green (RoHS & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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