TI TLV571IPW

TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
features
applications
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Fast Throughput Rate: 1.25 MSPS at 5 V,
625 KSPS at 3 V
Wide Analog Input: 0 V to AVDD
Differential Nonlinearity Error: < ± 0.5 LSB
Integral Nonlinearity Error: < ± 0.5 LSB
Single 2.7-V to 5.5-V Supply Operation
Low Power: 12 mW at 3 V and 35 mW at 5 V
Auto Power Down of 1 mA Max
Software Power Down: 10 µA Max
Internal OSC
Hardware Configurable
DSP and Microcontroller Compatible
Parallel Interface
Binary/Twos Complement Output
Hardware Controlled Extended Sampling
Hardware or Software Start of Conversion
Mass Storage and HDD
Automotive
Digital Servos
Process Control
General-Purpose DSP
Image Sensor Processing
DW OR PW PACKAGE
(TOP VIEW)
CS
WR
RD
CLK
DGND
DVDD
INT/EOC
DGND
DGND
D0
D1
D2
description
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
NC
AIN
AVDD
AGND
REFM
REFP
CSTART
A1/D7
A0/D6
D5
D4
D3
The TLV571 is an 8-bit data acquisition system
NC – No internal connection
that combines a high-speed 8-bit ADC and a
parallel interface. The device contains two on-chip control registers allowing control of software conversion start
and power down via the bidirectional parallel port. The control registers can be set to a default mode using a
dummy RD while WR is tied low allowing the registers to be hardware configurable.
The TLV571 operates from a single 2.7-V to 5.5-V power supply. It accepts an analog input range from 0 V to
AVDD and digitizes the input at a maximum 1.25 MSPS throughput rate at 5 V. The power dissipations are only
12 mW with a 3-V supply or 35 mW with a 5-V supply. The device features an auto power-down mode that
automatically powers down to 1 mA 50 ns after conversion is performed. In software power-down mode, the
ADC is further powered down to only 10 µA.
Very high throughput rate, simple parallel interface, and low power consumption make the TLV571 an ideal
choice for high-speed digital signal processing.
AVAILABLE OPTIONS
PACKAGE
TA
24 TSSOP
(PW)
24 SOIC
(DW)
– 40°C to 85°C
TLV571IPW
TLV571IDW
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
functional block diagram
REFP
AVDD AIN
REFM
8-BIT
SAR ADC
Internal
Clock
DVDD
Three
State
Latch
D0 – D5
D6/A0
D7/A1
MUX
CLK
CS
RD
WR
CSTART
Input Registers
and Control Logic
AGND
INT/EOC
DGND
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AGND
21
AIN
23
AVDD
22
A0/D6
16
I/O
Bidirectional 3-state data bus. D6/A0 along with D7/A1 is used as address lines to access CR0 and CR1 for
initialization.
A1/D7
17
I/O
Bidirectional 3-state data bus. D7/A1 along with D6/A0 is used as address lines to access CR0 and CR1 for
initialization.
CLK
4
I
External clock input
CS
1
I
Chip select. A logic low on CS enables the TLV571.
CSTART
18
I
Hardware sample and conversion start input. The falling edge of CSTART starts sampling and the rising edge
of CSTART starts conversion.
DGND
5, 8, 9
DVDD
6
Analog ground
I
ADC analog input
Analog supply voltage, 2.7 V to 5.5 V
Digital ground
Digital supply voltage, 2.7 V to 5.5 V
D0 – D5
10 –15
I/O
Bidirectional 3-state data bus
INT/EOC
7
O
End-of-conversion/interrupt
NC
24
RD
3
I
Read data. A falling edge on RD enables a read operation on the data bus when CS is low.
REFM
20
I
Lower reference voltage (nominally ground). REFM must be supplied or REFM pin must be grounded.
REFP
19
I
Upper reference voltage (nominally AVDD). The maximum input voltage range is determined by the difference
between the voltage applied to REFP and REFM.
WR
2
I
Write data. A rising edge on the WR latches in configuration data when CS is low. When using software
conversion start, a rising edge on WR also initiates an internal sampling start pulse. When WR is tied to ground,
the ADC in nonprogrammable (hardware configuration mode).
2
Not connected
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TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
detailed description
analog-to-digital SAR converter
Ain
Charge
Redistribution
DAC
_
SAR
Register
+
REFM
ADC Code
Control
Logic
Figure 1
The TLV571 is a successive-approximation ADC utilizing a charge redistribution DAC. Figure 1 shows a
simplified version of the ADC.
The sampling capacitor acquires the signal on Ain during the sampling period. When the conversion process
starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is
balanced, the conversion is complete and the ADC output code is generated.
sampling frequency, fs
The TLV571 requires 16 CLKs for each conversion, therefore the equivalent maximum sampling frequency
achievable with a given CLK frequency is:
fs(max) = (1/16) fCLK
The TLV571 is software configurable. The first two MSB bits, D(7,6) are used to address which register to set.
The remaining six bits are used as control data bits. There are two control registers, CR0 and CR1, that are user
configurable. All of the register bits are written to the control register during write cycles. A description of the
control registers is shown in Figure 2.
POST OFFICE BOX 655303
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3
TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
detailed description (continued)
control registers
A1
A0
A(1:0)=00
D5
D4
D2
D1
D0
D2
SWPWDN
D1
Don’t Care
D0
Don’t Care
Don’t Care
Don’t Care
Control Register One (CR1)
D5
D4
D1
D3
D2
Reserved
OSCSPD 0 Reserved 0 Reserved OUTCODE
D0
Reserved
Control Register Zero (CR0)
D5
D4
D3
STARTSEL PROGEOC CLKSEL
0:
0:
HARDWARE INT
START
(CSTART)
1:
EOC
1:
SOFTWARE
START
A(1:0)=01
D3
0:
Reserved
Bit
Always
Write 0
0:
INT. OSC.
SLOW
1:
INT. OSC.
FAST
0:
Internal
Clock
0:
NORMAL
1:
Powerdown
1:
External
Clock
0:
Reserved
Bit
Always
Write 0
0:
Reserved
Bit,
Always
Write 0
0:
Binary
1:
2’s
Complement
0:
Reserved
Bit,
Always
Write 0
Figure 2. Input Data Format
hardware configuration option
The TLV571 can configure itself. This option is enabled when the WR pin is tied to ground and a dummy RD
signal is applied. The ADC is now fully configured. Zeros or default values are applied to both control registers.
The ADC is configured ideally for 3-V operation, which means the internal OSC is set at 10 MHz and hardware
start of conversion using CSTART.
ADC conversion modes
The TLV571 provides two start of conversion modes. Table 1 explains these modes in more detail.
4
POST OFFICE BOX 655303
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TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
detailed description (continued)
Table 1. Conversion Modes
START OF
CONVERSION
OPERATION
COMMENTS – FOR INPUT
Hardware start
(CSTART)
CR0.D5 = 0
•
•
•
•
•
Software start
CR0.D5 = 1
• Repeated conversions from AIN
With external clock, WR and RD rising
• WR rising edge to start sampling initially. Thereafter, sampling occurs at the edge must be a minimum 5 ns before
or after CLK rising edge.
rising edge of RD.
• Conversion begins after 6 clocks after sampling has begun. Thereafter, if in INT
mode, one INT pulse generated after each conversion
• If in EOC mode, EOC will go high to low at start of conversion and return high at
end of conversion.
Repeated conversions from AIN
CSTART rising edge must be applied
CSTART falling edge to start sampling
a minimum of 5 ns before or after CLK
rising edge.
CSTART rising edge to start conversion
If in INT mode, one INT pulse generated after each conversion
If in EOC mode, EOC will go high to low at start of conversion, and return high
at end of conversion.
configure the device
The device can be configured by writing to control registers CR0 and CR1.
Table 2. TLV571 Programming Examples
REGISTER
INDEX
D5
D4
D3
D2
D1
D0
COMMENT
0
0
0
0
0
0
0
Normal, INT OSC
1
0
0
0
0
0
0
Binary
0
0
0
1
1
1
0
0
Power down, EXT OSC
0
1
0
0
0
0
1
0
2’s complement output
D7
D6
CR0
0
CR1
0
CR0
CR1
EXAMPLE1
EXAMPLE2
power down
The TLV571 offers two power down modes, auto power down and software power down. This device will
automatically proceed to auto power down mode if RD is not present one clock after conversion. Software power
down is controlled directly by the user by pulling CS to DVDD.
Table 3. Power Down Modes
AUTO POWER DOWN
SOFTWARE POWER DOWN
(CS = DVDD)
1 mA
10 µA
Comparator
Power down
Power down
Clock buffer
Power down
Power down
Control registers
Saved
Saved
Minimum power down time
1 CLK
2 CLK
Minimum resume time
1 CLK
2 CLK
PARAMETERS/MODES
Maximum power down dissipation current
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TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
detailed description (continued)
reference voltage input
The TLV571 has two reference input pins: REFP and REFM. The voltage levels applied to these pins establish
the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively. The
values of REFP, REFM, and the analog input should not exceed the positive supply or be less than GND
consistent with the specified absolute maximum ratings. The digital output is at full scale when the input signal
is equal to or higher than REFP and is at zero when the input signal is equal to or lower than REFM.
sampling/conversion
All sampling, conversion, and data output in the device are started by a trigger. This could be the RD, WR, or
CSTART signal depending on the mode of conversion and configuration. The rising edge of RD, WR, and
CSTART signal are extremely important, since they are used to start the conversion. These edges need to stay
close to the rising edge of the external clock (if it is used as CLK). The minimum setup and hold time with respect
to the rising edge of the external clock should be 5 ns minimum. When the internal clock is used, this is not an
issue since these two edges will start the internal clock automatically. Therefore, the setup time is always met.
Software controlled sampling lasts 6 clock cycles. This is done via the CLK input or the internal oscillator if
enabled. The input clock frequency can be 1 MHz to 20 MHz, translating into a sampling time from 0.6 µs to
0.3 µs. The internal oscillator frequency is 9 MHz minimum (ocillator frequency is between 9 MHz to 22 MHz),
translating into a sampling time from 0.6 µs to 0.3 µs. Conversion begins immediately after sampling and lasts
10 clock cycles. This is again done using the external clock input (1 MHz–20 MHz) or the internal oscillator
(9 MHz minimum) if enabled. Hardware controlled sampling, via CSTART, begins on falling CSTART lasts the
length of the active CSTART signal. This allows more control over the sampling time, which is useful when
sampling sources with large output impedances. On rising CSTART, conversion begins. Conversion in
hardware controlled mode also lasts 10 clock cycles. This is done using the external clock input (1 MHz–20 MHz)
or the internal oscillator (9 MHz minimum) as is the case in software controlled mode.
ExtClk
th(WRL_EXTCLKH) ≥5 ns
tsu(WRH_EXTCLKH) ≥5 ns
WR
OR
th(RDL_EXTCLKH) ≥5 ns
tsu(RDH_EXTCLKH) ≥5 ns
RD
OR
th(CSTARTL_EXTCLKH) ≥5 ns
tsu(CSTARTH_EXTCLKH)
≥5 ns
td(EXTCLK_CSTARTL) ≥5 ns
CSTART
NOTE: tsu = setup time, th = hold time
Figure 3. Trigger Timing – Software Start Mode Using External Clock
6
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TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
start of conversion mechanism
There are two ways to convert data: hardware and software. In the hardware conversion mode the ADC begins
sampling at the falling edge of CSTART and begins conversion at the rising edge of CSTART. Software start
mode ADC samples for 6 clocks, then conversion occurs for ten clocks. The total sampling and conversion
process lasts only 16 clocks in this case. If RD is not detected during the next clock cycle, the ADC automatically
proceeds to a power-down state. Data is valid on the rising edge of INT in both conversion modes.
hardware CSTART conversion
external clock
With CS low and WR low, data is written into the ADC. The sampling begins at the falling edge of CSTART and
conversion begins at the rising edge of CSTART. At the end of conversion, EOC goes from low to high, telling
the host that conversion is ready to be read out. The external clock is active and is used as the reference at all
times. With this mode, it is required that CSTART is not applied at the rising edge of the clock (see Figure 4).
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7
t su(CSL_WRL)
t h(WRH_CSH)
t su(CSL_RDL)
t su(CSL_RDL)
CS
WR
t d(CSH_CSTARTL)
t h(RDH_CSH)
tc
(10 CLKs)
tc
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
t (sample)
t(sample)
CSTART
RD
t su(DAV_WRH)
t h(WRH_DAV)
D[0:7]
Config
Data
t dis(RDH_DAV)
ADC
ADC
t en(RDL_DAV)
t en(RDL_DAV)
INT
OR
EOC
Auto Powerdown
Figure 4. Input Conversion – Hardware CSTART, External Clock
TLV571
2.7 V to 5.5 V, 1-CHANNEL, 8-BIT
RARALLEL ANALOG-TO-DIGITAL CONVERTER
CLK
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
8
start of conversion mechanism (continued)
internal clock
With CS low and WR low, data is written into the ADC. The sampling begins at the falling edge of CSTART, and conversion begins at the rising
edge of CSTART. The internal clock turns on at the rising edge of CSTART. The internal clock is disabled after each conversion.
t su(CSL_WRL)
t h(WRH_CSH)
t su(CSL_RDL)
t su(CSL_RDL)
CS
t d(CSH_CSTARTL)
WR
t
t h(RDH_CSH)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
t(sample)
(STARTOSC)
tc
CSTART
0
1
9
10
INTCLK
RD
t su(DAV_WRH)
D[0:7]
t dis(RDH_DAV)
h(WRH_DAV)
Config
Data
ADC
Data
t en(RDL_DAV)
ADC
Data
t en(RDL_DAV)
INT
tc
OR
EOC
Auto Powerdown
Figure 5. Input Conversion – Hardware CSTART, Internal Clock
Auto Powerdown
9
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
t
TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT
PARALLEL ANALOG-TO-DIGITAL CONVERTER
t (STARTOSC)
With CS low and WR low, data is written into the ADC. Sampling begins at the rising edge of WR. The conversion process begins 6 clocks
after sampling begins. At the end of conversion, the INT goes low telling the host that conversion is ready to be read out. EOC B low during
the conversion. The external clock is active and used as the reference at all times. With this mode, WR and RD should not be applied at the
rising edge of the clock (see Figure 3).
0
1
5
6
7
15
16
0
4
5
15
CLK
t su(CSL_WRL)
t su(CSL_RDL)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
t h(WRH_CSH)
t
t su(CSL_RDL)
h(RDH_CSH)
CS
WR
RD
tc
t(sample)
t su(DAV_WRH)
t(sample)
t h(WRH_DAV)
D[0:7]
Config
Data
tc
t dis(RDH_DAV)
ADC Data
ADC Data
t en(RDL_DAV)
t en(RDL_DAV)
INT
OR
EOC
Auto Powerdown
Figure 6. Input Conversion – Software Start, External Clock
TLV571
2.7 V to 5.5 V, 1-CHANNEL, 8-BIT
RARALLEL ANALOG-TO-DIGITAL CONVERTER
external clock
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
10
software START conversion
software START conversion (continued)
internal clock
With CS low and WR low, data is written into the ADC. Sampling begins at the rising edge of WR. Conversion begins 6 clocks after sampling
begins. The internal clock begins at the rising edge of WR. The internal clock is disabled after each conversion. Subsequent sampling begins
at the rising edge of RD.
t su(CSL_RDL)
t su(CSL_WRL)
t h(RDH_CSH)
CS
t
h(WRH_CSH)
WR
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
RD
t
t (STARTOSC)
(STARTOSC)
0
4
5
6
15
0
4
5
15
t(sample)
t(sample)
t su(DAV_WRH)
D[0:7]
Config
Data
h(WRH_DAV)
t
tc
dis(RDH_DAV)
tc
ADC
Data
ADC
t en(RDL_DAV)
INT
OR
EOC
Auto Powerdown
Figure 7. Input Conversion – Software Start, Internal Clock
Auto Powerdown
11
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
t
TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT
PARALLEL ANALOG-TO-DIGITAL CONVERTER
INTCLK
TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
software START conversion (continued)
system clock source
The TLV571 internally derives multiple clocks from the SYSCLK for different tasks. SYSCLK is used for most
conversion subtasks. The source of SYSCLK is programmable via control register zero, bit 3. The source of
SYSCLK is changed at the rising edge of WR of the cycle when CR0.D3 is programmed.
internal clock (CR0.D3 = 0, SYSCLK = internal OSC)
The TLV571 has a built-in 10 MHz OSC. When the internal OSC is selected as the source of SYSCLK, the
internal clock starts with a delay (one half of the OSC period max) after the falling edge of the conversion trigger
(either WR, RD, or CSTART). The OSC speed can be set to 10 ± 1 MHz or 20 ± 2 MHz by setting register bit
CR1.D4.
external clock (CR0.D3 = 1, SYSCLK = external clock)
The TLV571 is designed to accept an external clock input (CMOS/TTL logic) with frequencies from 1 MHz to
20 MHz.
host processor interface
The TLV571 provides a generic high-speed parallel interface that is compatible with high-performance DSPs
and general-purpose microprocessors. The interface includes D(0–7), INT/EOC, RD, and WR.
output format
The data output format is unipolar (code 0 to 255). The output code format can be either binary or twos
complement by setting register bit CR1.D1.
power up and initialization
After power up, CS must be low to begin an I/O cycle. INT/EOC is initially high. The TLV571 requires two write
cycles to configure the two control registers. The first conversion after the device has returned from the power
down state may be invalid and should be disregarded.
definitions of specifications and terminology
integral nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.
The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level
1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to
the true straight line between these two points.
differential nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.
A differential nonlinearity error of less than ±1 LSB ensures no missing codes.
zero offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.
gain error
The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition
should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual
difference between first and last code transitions and the ideal difference between first and last code transitions.
12
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TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
software START conversion (continued)
signal-to-noise ratio + distortion (SINAD)
Signal-to-noise ratio + disortion is the ratio of the rms value of the measured input signal to the rms sum of all
other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
effective number of bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
N = (SINAD – 1.76)/6.02
it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, the effective
number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its
measured SINAD.
total harmonic distortion (THD)
Total harmonic distortion is the ratio of the rms sum of the first six harmonic components to the rms value of the
measured input signal and is expressed as a percentage or in decibels.
spurious free dynamic range (SFDR)
Spurious free dynamic range is the difference in dB between the rms amplitude of the input signal and the peak
spurious signal.
DSP interface
The TLV571 is a 8-bit single input channel analog-to-digital converter with throughput up to 1.25 MSPS at 5 V
and up to 625 KSPS at 3 V. To achieve 1.25 MSPS throughput, the ADC must be clocked at 20 MHz. Likewise
to achieve 625 KSPS throughout, the ADC must be clocked at 10 MHz. The TLV571 can be easily interfaced
to microcontrollers, ASICs, and DSPs. Figure 8 shows the pin connections to interface the TLV571 to the
TMS320C6x DSP.
TMS320C6X
A0–A15
TLV571
EN
Address
Decoder
AIN
CS
REF
HW
WR
HR
RD
EOC
INTx
REFP
REFM
D0– D7
D0– D15
Figure 8. TMS320C6x DSP Interface
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13
TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
grounding and decoupling considerations
General practices should apply to the PCB design to limit high frequency transients and noise that are fed back
into the supply and reference lines. This requires that the supply and reference pins be sufficiently bypassed.
In most cases 0.1-µF ceramic chip capacitors are adequate to keep the impedance low over a wide frequency
range. Since their effectiveness depends largely on the proximity to the individual supply pin, they should be
placed as close to the supply pins as possible.
To reduce high frequency and noise coupling, it is highly recommended that digital and analog grounds be
shorted immediately outside the package. This can be accomplished by running a low impedance line between
DGND and AGND under the package.
DVDD
AVDD
TLV571
AVDD
100 nF
DVDD
100 nF
DGND
AGND
VREFP
REFP
100 nF
VREFM
REFM
Figure 9. Placement for Decoupling Capacitors
power supply ground layout
Printed-circuit boards that use separate analog and digital ground planes offer the best system performance.
Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected
together at the low-impedance power-supply source. The best ground connection may be achieved by
connecting the ADC AGND terminal to the system analog ground plane making sure that analog ground
currents are well managed.
Driving Source†
TLV571
Rs
VS
VI
AIN
Ri(ADC)
VC
Ci
15 pF
VI = Input Voltage at AIN
VS = External Driving Source Voltage
Rs = Source Resistance
Ri(ADC)= Input Resistance of ADC
Ci = Input Capacitance
VC = Capacitance Charging Voltage
† Driving source requirements:
• Noise and distortion for the source must be equivalent to the resolution of the converter.
• Rs must be real at the input frequency.
Figure 10. Equivalent Input Circuit Including the Driving Source
14
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TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
simplified analog input analysis
Using the equivalent circuit in Figure 10, the time required to charge the analog input capacitance from 0 to VS
within 1/2 LSB, tch(1/2 LSB), can be derived as follows.
ǒ
Ǔ
The capacitance charging voltage is given by:
V
C(t)
+ VS 1–e–tchńRtCi
Where
(1)
Rt = Rs + Ri
Ri = Ri(ADC)
tch = Charge time
The input impedance Ri is 718 Ω at 5 V, and is higher (~ 1.25 kΩ) at 2.7 V. The final voltage to 1/2 LSB is given
by:
(2)
VC (1/2 LSB) = VS – (VS /512)
ǒ
Ǔ
Equating equation 1 to equation 2 and solving for cycle time tc gives:
V
S
ǒ
Ǔ
* VSń512 + VS 1–e–tchńRtCi
and time to change to 1/2 LSB (minimum sampling time) is:
(3)
tch (1/2 LSB) = Rt × Ci × ln(512)
Where
ln(512) = 6.238
Therefore, with the values given, the time for the analog input signal to settle is:
tch (1/2 LSB) = (Rs + 718 Ω) × 15 pF × ln(512)
(4)
This time must be less than the converter sample time shown in the timing diagrams. Which is 6x SCLK.
tch (1/2 LSB) ≤ 6x 1/f(SCLK)
(5)
Therefore the maximum SCLK frequency is:
Max(f(SCLK) ) = 6 / tch (1/2 LSB) = 6/(ln(512) × Rt × Ci )
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
(6)
15
TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, GND to VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 6.5 V
Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to AVDD + 0.3 V
Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVDD + 0.3 V
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to DVDD + 0.3 V
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 150°C
Operating free-air temperature range, TA, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
power supplies
MIN
MAX
UNIT
Analog supply voltage, AVDD
2.7
5.5
V
Digital supply voltage, DVDD
2.7
5.5
V
NOTE 1: Abs (AVDD – DVDD) < 0.5 V
analog inputs
Analog input voltage, AIN
MIN
MAX
UNIT
AGND
VREFP
V
digital inputs
MIN
NOM
2.1
2.4
MAX
UNIT
High-level input voltage, VIH
DVDD = 2.7 V to 5.5 V
Low level input voltage, VIL
DVDD = 2.7 V to 5.5 V
0.8
V
DVDD = 4.5 V to 5.5 V
20
MHz
DVDD = 2.7 V to 3.3 V
10
MHz
Input CLK frequency
Pulse duration
duration, CLK high
high, tw(CLKH)
(CLKH)
Pulse duration
duration, CLK low
low, tw(CLKL)
V
DVDD = 4.5 V to 5.5 V, fCLK = 20 MHz
23
ns
DVDD = 2.7 V to 3.3 V, fCLK = 10 MHz
46
ns
DVDD = 4.5 V to 5.5 V, fCLK = 20 MHz
23
ns
DVDD = 2.7 V to 3.3 V, fCLK = 10 MHz
46
ns
Rise time, I/O and control, CLK, CS
50 pF output load
4
Fall time, I/O and control, CLK, CS
50 pF output load
4
ns
reference specifications
MIN
External reference voltage
VREFP
AVDD = 3 V
AVDD = 5 V
VREFM
AVDD = 3 V
AVDD = 5 V
VREFP – VREFM
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MAX
UNIT
AVDD
AVDD
V
2.5
AGND
1
V
AGND
2
V
2
AVDD–AGND
V
2
NOM
V
TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted)
digital specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Logic inputs
IIH
IIL
High-level input current
DVDD = 5 V, DVDD = 3 V, Input = DVDD
–1
1
µA
Low-level input current
DVDD = 5 V, DVDD = 3 V, Input = 0 V
–1
1
µA
Ci
Input capacitance
15
pF
10
Logic outputs
VOH
VOL
High-level output voltage
Low-level output voltage
IOH = 50 µA to 0.5 mA
IOL = 50 µA to 0.5 mA
IOZ
IOL
High-impedance-state output current
DVDD = 5 V, DVDD = 3 V, Input = DVDD
Low-impedance-state output current
DVDD = 5 V, DVDD = 3 V, Input = 0 V
Co
Output capacitance
DVDD– 0.4
V
0.4
V
1
µA
–1
µA
5
Internal clock
pF
3 V, AVDD = DVDD
9
10
11
5 V, AVDD = DVDD
18
20
22
MHz
dc specifications
PARAMETER
TEST CONDITIONS
MIN
Resolution
TYP
MAX
8
UNIT
Bits
Accuracy
Integral nonlinearity, INL
Best fit
Differential nonlinearity, DNL
± 0.3
±0.5
LSB
± 0.3
±0.5
LSB
Missing codes
EO
EG
0
Offset error
± 0.15%
± 0.3%
FSR
Gain error
± 0.2%
± 0.4%
FSR
Analog input
Ci
Input capacitance
Ilkg
Input leakage current
Voltage reference input
ri
Input resistance
Ci
Input capacitance
AIN, AVDD = 3 V, AVDD = 5 V
15
pF
MUX input, AVDD = 3 V, AVDD = 5 V
25
pF
±1
VAIN = 0 to AVDD
2
µA
kΩ
300
pF
Power supply
PD
IPD
Operating supply current,
current IDD + IREF
AVDD = DVDD = 3 V, fCLK = 10 MHz
AVDD = DVDD = 5 V, fCLK = 20 MHz
Power dissipation
AVDD+DVDD = 3 V
AVDD+DVDD = 5 V
Software
IDD + IREF
AVDD = 3 V
AVDD = 5 V
Auto
IDD + IREF
AVDD = 3 V
AVDD = 5 V
Supply current in power-down
power down mode
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
4
5.5
mA
7
8.5
mA
12
17
mW
35
43
mW
1
8
µA
2
10
µA
0.5
1
mA
0.5
1
mA
17
TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted) (continued)
ac specifications, AVDD = DVDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fI = 100 kHz,,
80% of FS
fs = 1.25 MSPS, AVDD = 5 V
fs = 625 KSPS, AVDD = 3 V
47
49
dB
47
49
dB
fI = 100 kHz,,
80% of FS
fs = 1.25 MSPS, AVDD = 5 V
fs = 625 KSPS, AVDD = 3 V
47
49
dB
distortion THD
Total harmonic distortion,
fI = 100 kHz,,
80% of FS
fs = 1.25 MSPS, AVDD = 5 V
fs = 625 KSPS, AVDD = 3 V
Effective number of bits,
bits ENOB
fI = 100 kHz,,
80% of FS
fs = 1.25 MSPS, AVDD = 5 V
fs = 625 KSPS, AVDD = 3 V
range SFDR
Spurious free dynamic range,
fI = 100 kHz,,
80% of FS
fs = 1.25 MSPS, AVDD = 5 V
fs = 625 KSPS, AVDD = 3 V
Signal to noise ratio,
Signal-to-noise
ratio SNR
Signal to noise ratio + distortion,
Signal-to-noise
distortion SINAD
47
49
dB
–64
–52
dB
–62
–52
dB
7.5
7.9
Bits
7.5
7.9
Bits
–65
–51
dB
–64
–51
dB
Analog input
Full power bandwidth
Full-power
Small-signal bandwidth
Sampling
Sam
ling rate
rate, fs
18
–1 dB
Full-scale 0 dB input sine wave
–3 dB
Full-scale 0 dB input sine wave
–1 dB
–20 dB input sine wave
–3 dB
–20 dB input sine wave
12
15
18
MHz
30
MHz
20
MHz
35
MHz
AVDD = 4.5 V to 5.5 V
0.0625
1.25
MSPS
AVDD = 2.7 V to 3.3 V
0.0625
0.625
MSPS
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
timing requirements, AVDD = DVDD = 5 V (unless otherwise noted)
PARAMETER
tc(CLK)
Input
In
ut clock Cycle time
t(sample)
Reset and sampling time
tc
TEST CONDITIONS
MIN
DVDD = 4.5 V to 5.5 V
50
TYP
MAX
UNIT
ns
DVDD = 2.7 V to 3.3 V
100
ns
6
SYSCLK
Cycles
Total conversion time
10
SYSCLK
Cycles
twL(EOC)
Pulse width, end of conversion, EOC
10
SYSCLK
Cycles
twL(INT)
Pulse width, interrupt
1
SYSCLK
Cycles
t(STARTOSC)
Start-up time, internal oscillator
td(CSH_ CSTARTL)
Delay time, CS high to CSTART low
100
ns
10
ns
DVDD = 5 V at 50 pF
20
ns
DVDD = 3 V at 50 pF
40
ns
DVDD = 5 V at 50 pF
5
ns
DVDD = 3 V at 50 pF
10
ns
ten(RDL_DAV)
en(RDL DAV)
Enable time,
time data out
tdis(RDH_DAV)
dis(RDH DAV)
Disable time
time, data out
tsu(CSL_WRL)
Setup time, CS to WR
5
th(WRH_CSH)
Hold time, CS to WR
5
ns
ns
tw(WR)
Pulse width, write
1
Clock
Period
tw(RD)
Pulse width, read
1
Clock
Period
tsu(DAV_WRH)
Setup time, data valid to WR
10
ns
th(WRH_DAV)
Hold time, data valid to WR
5
tsu(CSL_RDL)
Setup time, CS to RD
5
ns
th(RDH_CSH)
Hold time, CS to RD
5
ns
th(WRL_EXTXLKH)
Hold time WR to clock high
5
ns
th(RDL_EXTCLKH)
Hold time RD to clock high
5
ns
th(CSTARTL_EXTCLKH)
Hold time CSTART to clock high
5
ns
tsu(WRH_EXTCLKH)
Setup time WR high to clock high
5
ns
tsu(RDH_EXTCLKH)
Setup time RD high to clock high
5
ns
tsu(CSTARTH_EXTCLKH)
Setup time CSTART high to clock high
5
ns
5
ns
td(EXTCLK_CSTARTL)
Delay time clock low to CSTART low
NOTE: Specifications subject to change without notice.
Data valid is denoted as DAV.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
ns
19
TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
TYPICAL CHARACTERISTICS
I CC – Supply Current – mA
SUPPLY CURRENT
vs
FREE AIR TEMPERATURE
8.0
7.5
AVDD = DVDD = 5 V, 20 MHz
7.0
6.5
6.0
5.5
5.0
4.5
4.0
AVDD = DVDD = 3 V, 10 MHz
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80
TA – Free Air Temperature – °C
Figure 11
ANALOG INPUT BANDWIDTH
vs
FREQUENCY
SUPPLY CURRENT
vs
CLOCK FREQUENCY
1
7
0
AVDD = DVDD = 5 V
Analog Input Bandwidth – dB
I CC – Supply Current – mA
6
5
4
3
AVDD = DVDD = 3 V
2
–1
–2
–3
–4
AVDD = DVDD = 5 V,
AIN = 90% of FS,
REF = 5 V,
1
–5
0
0
2
4
6
8
10
12
14
16
18
20
TA = 25°C
–6
0.1
Figure 12
Figure 13
POST OFFICE BOX 655303
10
f – Frequency – MHz
fclock – Clock Frequency – MHz
20
1
• DALLAS, TEXAS 75265
100
TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
TYPICAL CHARACTERISTICS
DNL – Differential Nonlinearity – LSB
DIFFERENTIAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
0.15
AVDD = DVDD = 3 V,
External Ref = 3 V,
CLK = 10 MHz,
TA = 25°C
0.10
0.05
–0.00
–0.05
–0.10
–0.15
0
64
128
192
256
Digital Output Code
Figure 14
INL – Integral Nonlinearity – LSB
INTEGRAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.00
AVDD = DVDD = 3 V,
External Ref = 3 V,
CLK = 10 MHz,
TA = 25°C
–0.02
–0.04
–0.06
0
64
128
192
256
Digital Output Code
Figure 15
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
DNL – Differential Nonlinearity – LSB
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
0.12
AVDD = DVDD = 5 V,
External Ref = 5 V,
CLK = 20 MHz,
TA = 25°C
0.10
0.08
0.06
0.04
0.02
0.00
–0.02
–0.04
–0.06
–0.08
0
64
128
192
256
192
256
Digital Output Code
Figure 16
INL – Integral Nonlinearity – LSB
INTEGRAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.00
–0.02
–0.04
–0.06
–0.08
AVDD = DVDD = 5 V,
External Ref = 5 V,
CLK = 20 MHz,
TA = 25°C
0
64
128
Digital Output Code
Figure 17
22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
TYPICAL CHARACTERISTICS
EFFECTIVE NUMBER OF BITS
vs
FREQUENCY
ENOB – Effective Number of Bits – BITS
10
AVDD = DVDD = 3 V,
External Ref = 3 V
9
8
7
6
5
0
100
200
f – Frequency – kHz
300
Figure 18
EFFECTIVE NUMBER OF BITS
vs
FREQUENCY
ENOB – Effective Number of Bits – BITS
10
AVDD = DVDD = 5 V,
External Ref = 5 V
9
8
7
6
5
0
200
400
600
f – Frequency – kHz
Figure 19
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
TYPICAL CHARACTERISTICS
FAST FOURIER TRANSFORM
vs
FREQUENCY
20
AIN = 200 KHz
Magnitude – dB
0
–20
CLK = 10 MHz
–40
AVDD = DVDD = 3 V
External Ref = 3 V
–60
–80
–100
–120
–140
0
100000
200000
300000
f – Frequency – Hz
Figure 20
FAST FOURIER TRANSFORM
vs
FREQUENCY
20
AIN = 200 KHz
Magnitude – dB
0
–20
CLK = 20 MHz
–40
AVDD = DVDD = 5 V
External Ref = 5 V
–60
–80
–100
–120
–140
0
200000
400000
f – Frequency – Hz
Figure 21
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
600000
TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
MECHANICAL DATA
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PINS SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
16
0.010 (0,25) M
9
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.293 (7,45)
Gage Plane
0.010 (0,25)
1
8
0°– 8°
A
0.050 (1,27)
0.016 (0,40)
Seating Plane
0.104 (2,65) MAX
0.012 (0,30)
0.004 (0,10)
PINS **
0.004 (0,10)
16
20
24
28
A MAX
0.410
(10,41)
0.510
(12,95)
0.610
(15,49)
0.710
(18,03)
A MIN
0.400
(10,16)
0.500
(12,70)
0.600
(15,24)
0.700
(17,78)
DIM
4040000 / C 07/96
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MS-013
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• DALLAS, TEXAS 75265
25
TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
26
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TLV571IDW
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV571IDWG4
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV571IDWR
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV571IDWRG4
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV571IPW
ACTIVE
TSSOP
PW
24
60
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TLV571IPWG4
ACTIVE
TSSOP
PW
24
60
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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Addendum-Page 1
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