UC1823 UC2823 UC3823 High Speed PWM Controller FEATURES DESCRIPTION • Compatible with Voltage or Current-Mode Topologies • Practical Operation @ Switching Frequencies to 1.0MHz • 50ns Propagation Delay to Output • High Current Totem Pole Output (1.5A peak) The UC1823 family of PWM control ICs is optimized for high frequency switched mode power supply applications. Particular care was given to minimizing propagation delays through the comparators and logic circuitry while maximizing bandwidth and slew rate of the error amplifier. This controller is designed for use in either current-mode or voltage-mode systems with the capability for input voltage feed-forward. • Wide Bandwidth Error Amplifier • Fully Latched Logic with Double Pulse Suppression • Pulse-by-Pulse Current Limiting • Soft Start/Max. Duty Cycle Control • Under-Voltage Lockout with Hysteresis • Low Start Up Current (1.1mA) • Trimmed Bandgap Reference (5.1V ±1%) Protection circuitry includes a current limit comparator, a TTL compatible shutdown port, and a soft start pin which will double as a maximum duty cycle clamp. The logic is fully latched to provide jitter free operation and prohibit multiple pulses at the output. An under-voltage lockout section with 800mV of hysteresis assures low start up current. During under-voltage lockout, the output is high impedance. The current limit reference (pin 11) is a DC input voltage to the current limit comparator. Consult specifications for details. These devices feature a totem pole output designed to source and sink high peak currents from capacitive loads, such as the gate of a power MOSFET. The on state is defined as a high level. ABSOLUTE MAXIMUM RATINGS Supply Voltage (Pins 15, 13) . . . . . . . . . . . . . . . . . . . . . . . . 30V Output Current, Source or Sink (Pin14) DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A Pulse (0.5µs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0A Analog Inputs (Pins 1, 2, 7, 8, 9, 11) . . . . . . . . . . . -0.3V to +6V Clock Output Current (Pin 4) . . . . . . . . . . . . . . . . . . . . . . . -5mA Error Amplifier Output Current (Pin 3) . . . . . . . . . . . . . . . . 5mA Soft Start Sink Current (Pin 8) . . . . . . . . . . . . . . . . . . . . . 20mA Oscillator Charging Current (Pin 5) . . . . . . . . . . . . . . . . . . -5mA Power Dissipation at TA = 60 °C . . . . . . . . . . . . . . . . . . . . . 1W Storage Temperature Range . . . . . . . . . . . . . . -65°C to +150°C Lead Temperature (Soldering, 10 seconds) . . . . . . . . . . 300°C Note: All voltages are with respect to ground, Pin 10. Currents are positive into the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages. BLOCK DIAGRAM 3/97 1 UC1823 UC2823 UC3823 CONNECTION DIAGRAMS DIL-16, SOIC-16 (TOP VIEW) J or N, DW Package PLCC-20, LCC-20 (TOP VIEW) Q, L Package PACKAGE PIN FUNCTION FUNCTION PIN N/C Inv. N.I. E/A Out Clock N/C RT CT Ramp Soft start N/C ILIM/S.D. Ground ILIM REF PWR Gnd N/C VC OUT VCC VREF 5.1V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ELECTRICAL CHARACTERISTICS: Unless otherwise noted, these specifications apply for RT = 3.65k, CT = 1nF, VCC = 15V, 0°C < TA < +70°C for the UC3823, -25°C < TA < +85°C for the UC2823, and -55°C < TA < +125°C for the UC1823, TA = TJ. PARAMETER UC1823 UC2823 TEST CONDITIONS UC3823 UNITS MIN TYP MAX MIN TYP MAX 5.05 5.10 5.15 5.00 5.10 5.20 Reference Section Output Voltage TJ = 25°C, lO = 1mA Line Regulation 10 < VCC < 30V 2 20 2 20 mV Load Regulation 1 < IO < 10mA 5 20 5 20 mV Temperature Stability* TMIN < TA < TMAX 0.4 mV/°C Total Output Variation* Line, Load, Temp. 0.2 5.00 0.4 5.20 Output Noise Voltage* 10Hz < f < 10kHz 50 Long Term Stability* TJ = 125°C, 1000 hrs. 5 25 Short Circuit Current VREF=0V -15 -50 -100 360 400 440 0.2 2 0.2 4.95 V 5.25 µV 50 5 25 mV -15 -50 -100 mA 360 400 440 kHz 0.2 2 % 460 kHz 2.9 V Oscillator Section Initial Accuracy* TJ=25°C Voltage Stability* 10 < VCC < 30V Temperature Stability* TMIN <TA < TMAX Total Variation* Line, Temp. 5 340 Clock Out High 3.9 Clock Out Low 5 460 4.5 2.3 340 3.9 2.9 % 4.5 2.3 V Ramp Peak* 2.6 2.8 3.0 2.6 2.8 3.0 V Ramp Valley* 0.7 1.0 1.25 0.7 1.0 1.25 V Ramp Valley to Peak* 1.6 1.8 2.0 1.6 1.8 2.0 V * These parameters are guaranteed by design but not 100% tested in production. 2 UC1823 UC2823 UC3823 ELECTRICAL CHARACTERISTICS: Unless otherwise noted, these specifications apply for RT = 3.65k, CT = 1nF, VCC = 15V, 0°C < TA < +70°C for the UC3823, -25°C < TA < +85°C for the UC2823, and -55°C < TA < +125°C for the UC1823, TA = TJ. PARAMETER UC1823 UC2823 TEST CONDITIONS MIN TYP UC3823 MAX MIN TYP UNITS MAX Error Amplifier Section Input Offset Voltage 10 Input Bias Current Input Offset Current Open Loop Gain 1 < VO < 4V 60 CMRR 1.5 < VCM < 5.5V PSRR 10 < VCC < 30V 0.6 3 0.1 1 95 60 75 95 85 110 15 mV 0.6 3 µA 0.1 1 µA 95 dB 75 95 dB 85 110 dB Output Sink Current VPIN 3 =1V 1 2.5 1 2.5 mA Output Source Current VPIN 3 = 4V -0.5 -1.3 -0.5 -1.3 mA Output High Voltage IPIN 3 = −0.5mA 4.0 4.7 5.0 4.0 4.7 5.0 V Output Low Voltage IPIN 3 = 1mA 0 0.5 1.0 0 0.5 1.0 V Unity Gain Bandwidth* 3 5.5 3 5.5 MHz Slew Rate* 6 12 6 12 V/µS PWM Comparator Section Pin 7 Bias Current VPIN 7 = 0V -1 Duty Cycle Range Pin 3 Zero D.C. Threshold 0 VPIN 7 = 0V 1.1 Delay to Output* -5 80 1.25 -1 0 1.1 50 80 9 20 -5 µA 85 % 1.25 V 50 80 9 20 ns Soft-Start Section Charge Current VPIN 8 = 0.5V 3 Discharge Current VPIN 8 = 1V 1 3 1 µA mA Current Limit/Shutdown Section Pin 9 Bias Current 0 < VPIN 9 < 4V Current Limit Offset VPIN 11 = 1.1V ±10 15 Current Limit Common Mode Range (VPIN 11) 1.0 Shutdown Threshold 1.25 µA 15 mV 1.25 V 1.40 1.55 V 80 50 80 ns 0.25 0.40 0.25 0.40 V 1.2 2.2 1.2 2.2 V 1.25 1.0 1.40 1.55 1.25 50 IOUT = 20mA IOUT = 200mA Delay to Output* ±10 Output Section Output Low Level Output High Level IOUT = −20mA 13.0 13.5 13.0 13.5 V IOUT = −200mA 12.0 13.0 12.0 13.0 V Collector Leakage VC = 30V 100 500 100 500 µA Rise/Fall Time* CL = 1nF 30 60 30 60 ns Under-Voltage Lockout Section Start Threshold 8.8 9.2 9.6 8.8 9.2 9.6 V UVLO Hysteresis 0.4 0.8 1.2 0.4 0.8 1.2 V Supply Current Start Up Current VCC = 8V 1.1 2.5 1.1 2.5 mA ICC VPIN 1, VPIN 7, VPIN 9 =0V, VPIN 2 = 1V 22 33 22 33 mA * These parameters are guaranteed by design but not 100% tested in production. 3 UC1823 UC2823 UC3823 UC1823 PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS High speed circuits demand careful attention to layout and component placement. To assure proper performance of the UC1823, follow these rules. 1) Use a ground plane. 2) Damp or clamp parasitic inductive kick energy from the gate of driven MOSFET. Don’t allow the output pins to ring below ground. A series gate resistor or a shunt 1 Amp Schottky diode at the output pin will serve this purpose. 3) Bypass VCC, VC, and VREF. Use 0.1µF monolithic ceramic capacitors with low equivalent series inductance. Allow less than 1 cm of total lead length for each capacitor between the bypassed pin and the ground plane. 4) Treat the timing capacitor, CT, like a bypass capacitor. ERROR AMPLIFIER CIRCUIT Simplified Schematic Unity Gain Slew Rate Open Loop Frequency Response PWM APPLICATIONS Conventional (Voltage Mode) Current-Mode * A small filter may be required to suppress switch 4 UC1823 UC2823 UC3823 OSCILLATOR CIRCUIT SYNCHRONIZED OPERATION Two Units in Close Proximity Generalized Synchronization 5 UC1823 UC2823 UC3823 CONSTANT VOLT-SECOND CLAMP CIRCUIT The circuit shown here will achieve a constant volt-second product clamp over varying input voltages. The ramp generator components, RT and CR are chosen so that the ramp at Pin 9 crosses the 1V threshold at the same time the desired maximum volt-second product is reached. The delay through the inverter must be such that the ramp capacitor can be completely discharged during the minimum deadtime. OUTPUT SECTION FEED FORWARD TECHNIQUE FOR OFF-LINE VOLTAGE MODE APPLICATION UNITRODE CORPORATION 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. 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