TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30 www.ti.com SLVSAC2A – AUGUST 2010 – REVISED DECEMBER 2010 2, 4-CHANNEL PROTECTION SOLUTION FOR SUPER-SPEED (6 GBPS) USB 3.0 INTERFACE Check for Samples: TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30 FEATURES 1 • • • • • • • • • Single and Dual-Pair Differential Lines to Protect the Differential Data and Clock Lines of the USB3.0, eSATA, or LVD Interface Flow-Through Pin Mapping for the High-Speed Lines Ensures near Zero Additional Skew Due to Board Layout While Placing Protection Chip Near the Connector Supports Data Rates in Excess of 6 Gbps ESD Protection Meets or Exceeds IEC61000-4-2 (Level 4) Low Capacitance 0.05pF (IO to IO) 1 Ω Dynamic Resistance 5-A Peak Pulse Current (per 8/20 ms Pulse) Industrial Temperature Range: –40°C to 85°C Space-Saving DRT, DQA Packages APPLICATIONS • • • • • DRT PACKAGE (TOP VIEW) D+ 1 3 D– GND 2 DQA PACKAGE (TOP VIEW) D1+ 1 10 N.C. D1– 2 9 N.C. GND 3 8 GND D2+ 4 7 N.C. D2– 5 6 N.C. Notebooks Set-Top Boxes DVD Players Media Players Portable Computers DESCRIPTION/ORDERING INFORMATION The TPD2EUSB30, TPD2EUSB30A, and TPD4EUSB30 provide 2 and 4 channel ESD and surge protection solutions in space saving, flow-through packages. These devices have been designed to protect sensitive components which are connected to ultra high-speed data and transmission lines. These devices also offer 5 A (8/20 ms) peak pulse current ratings per IEC 61000-4-5 (lightning) specification. The monolithic silicon technology allows matching between the differential signal pairs. The differential 0.05-pF capacitance ensures that the signal distortion due to added ESD clamp remains minimal at high-speed differential data transmission. The TPD2EUSB30A offers low 4.5V dc break-down voltage. The low capacitance and break-down voltage, coupled low dynamic resistance, make the TPD2EUSB30A a superior ESD/ surge protection device for high-speed differential IOs based off ultra-low voltage process nodes. The TPD2EUSB30 and TPD2EUSB30A are offered in space saving DRT (1 mm × 1 mm) package. The TPD4EUSB30 is offered in space saving DQA (1 mm × 2.5 mm) package. These devices are characterized for operation over ambient air temperature range of –40°C to 85°C. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30 SLVSAC2A – AUGUST 2010 – REVISED DECEMBER 2010 www.ti.com ORDERING INFORMATION PACKAGE (1) TA –40°C to 85°C (1) (2) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING SOT – DRT Tape and reel TPD2EUSB30DRTR 5PX SOT – DRT Tape and reel TPD2EUSB30ADRTR 5SX SON – DQA Tape and reel TPD4EUSB30DQAR 66R Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. CIRCUIT DIAGRAMS TPD4EUSB30 Circuit D1+ D2+ D1D2- GND TPD2EUSB30/A Circuit D– D+ GND TERMINAL FUNCTIONS TERMINAL DRT PIN NO. DQA PIN NO. Dx+, Dx– 1, 2 1,2, 4, 5 ESD port GND 3 3, 8 GND N.C. 2 TYPE NAME 6, 7, 9, 10 Submit Documentation Feedback DESCRIPTION High-speed ESD clamp, provides ESD protection to the high-speed differential data lines Ground Not normally connected Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30 TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30 www.ti.com SLVSAC2A – AUGUST 2010 – REVISED DECEMBER 2010 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) IO voltage tolerance D+, D– pins MIN MAX 0 6 UNIT TA Operating free-air temperature range –40 85 Tstg Storage temperature range –65 125 °C ESD protection (1) °C IEC 61000-4-2 Contact Discharge D+, D– pins ±8 kV IEC 61000-4-2 Air-Gap Discharge (TPD2EUSB30/A) D+, D– pins ±8 kV IEC 61000-4-2 Air-Gap Discharge (TPD4EUSB30) D+, D– pins ±9 kV Peak pulse current (tp = 8/20 ms) D+, D– pins 5 A Peak pulse power (tp = 8/20 ms) D+, D– pins 45 W Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Reverse stand-off voltage, TPD2EUSB30, TPD4EUSB30 D+,D– pins to ground 5.5 V Reverse stand-off voltage, TPD2EUSB30A D+,D– pins to ground 3.6 V Vclamp Clamp voltage D+,D– pins to ground, IIO = 1 A 8 V IIO Current from IO port to supply pins VIO = 2.5 V, ID = 8 mA 0.01 0.1 mA VD Diode forward voltage D+,D– pins, lower clamp diode, VIO = 2.5 V, ID = 8 mA 0.8 0.95 V Rdyn Dynamic resistance D+,D– pins I=1A CIO-IO Capacitance IO to IO D+,D– pins VIO = 2.5 V VRWM 0.6 D+,D– pins (DRT) CIO-GND Capacitance IO to GND VBR D1+, D1-, D2+, D2- (DQA ) VIO = 2.5 V 0.05 pF 0.8 IIO = 1 mA Copyright © 2010, Texas Instruments Incorporated Ω 0.7 Break-down voltage, TPD2EUSB30, IIO = 1 mA TPD4EUSB30 Break-down voltage, TPD2EUSB30A 1 7 V 4.5 V Submit Documentation Feedback Product Folder Link(s): TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30 pF 3 TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30 SLVSAC2A – AUGUST 2010 – REVISED DECEMBER 2010 www.ti.com TYPICAL OPERATING CHARACTERISTICS 1.20E-12 10 TA = 25°C 5 1.10E-12 9.00E-13 Leakage Current (pA) Capacitnace (Farads) 0 1.00E-12 DQA Package 8.00E-13 DRT Package 7.00E-13 –5 –10 –15 D– –20 D+ –25 –30 6.00E-13 5.00E-13 0.0 VIO = 2.5 V –35 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 –40 Figure 1. IO Capacitance vs IO Voltage 11 55 10 5.0 50 4.5 45 4.0 40 3.5 35 3.0 30 25 Current (A) 2.0 20 1.5 15 1.0 10 Power (W) 9 8 Current (A) IPP (A) 60 PPP (W) Measured at one IO, the other IO open 2.5 5 10 15 20 25 30 Time (ms) 35 40 45 6 5 3 2 1 0 0.0 7 4 5 0.5 0 50 0 0 100 20 90 10 80 0 70 -10 60 -20 50 40 30 -70 0 -80 -10 -90 -20 -100 125 150 175 Figure 5. IEC Clamping Waveforms (8 kV Contact) 4 Submit Documentation Feedback 20 Voltage (V) 25 30 35 40 -50 -60 75 100 Time (ns) 15 -40 10 50 10 -30 20 25 5 Figure 4. D+,D– Transmission Line Pulser Plot for TPD2EUSB30 (100 ns Pulse, 10 ns Rise Time) Amplitude (V) Amplitude (V) Figure 3. Peak Pulse Waveforms 0 85 Figure 2. Leakage Current vs Temperature 6.0 5.5 55 25 Temperature (°C) –40 Voltage (V) 200 0 25 50 75 100 Time (ns) 125 150 175 200 Figure 6. IEC Clamping Waveforms (–8 kV Contact) Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30 TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30 www.ti.com SLVSAC2A – AUGUST 2010 – REVISED DECEMBER 2010 APPLICATION INFORMATION Layout Guide with TPDxEUSB30/A Refer to Figure 7, the TPD2EUSB30/A are offered in space saving DRT package. The DRT is a 1mm* 1mm package with flow-through pin-mapping for the high-speed differential lines. The TPD4EUSB30 is offered in space saving DQA package. The DQA is a 1mm* 2.5mm package with flow-through pin-mapping for the high-speed differential lines. It is recommended to place the package right next to the USB 3.0 connector. The GND pin should connected to GND plane of the board through a large VIA. If a dedicated GND plane is not present right underneath, it is recommended to route to the GND plane through a wide trace. The current associated with IEC ESD stress can be in the range of 30Amps or higher momentarily. A good, low impedance GND path ensures the system robustness against IEC ESD stress. The TPDxEUSB30/A can provide system level ESD protection to the high-speed differential ports (>6 Gbps data rate). The flow-through package offers flexibility for board routing with traces up to 15 mills wide. It allows the differential signal pairs couple together right after they touch the ESD ports of the TPDxEUSB30/A. TX+ VBUS TX- TPD2EUSB30DRTR D- USB 3.0 Host/ Controller 1-mm DGND GND 8-mm D+ D+ RX+ 1-mm GND RX- Three TPD2EUSB30 to Protect USB3.0 Class A connector (One Layer Routing) TPD4EUSB30 D1+ TX+ VBUS N.C. TXD1- N.C. GND D2+ N.C. D2- N.C. D- 2.5-mm GND USB 3.0 Host/ Controller GND 8-mm D+ RX+ GND RX- 1-mm One TPD4EUSB30 & One TPD2EUSB30 to Protect USB3.0 Class A connec tor (Two Layer Routing) Figure 7. Layout Guide with the TPDxEUSB30/A at the USB3.0 Class A Connector TPDxEUSB30/A Eye Pattern Test See Figure 9 for a demonstration of the TPDxEUSB30/A performance the lab set-up. Figure 8 shows a lab board that was designed to demonstrate the degradation of the eye pattern quality with and without the TPD2EUSB30/A in the USB 3.0 signal path. Figure 10 shows that there is only ~2 ps jitter penalty to the differential signal when the TPD2EUSB30/A device was added in the signal path. Similar setup was employed to measure eye pattern for the TPD4EUSB30. Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30 5 TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30 SLVSAC2A – AUGUST 2010 – REVISED DECEMBER 2010 www.ti.com Eye Pattern Measurement Point Pattern Generator 36” Lossy Transmission Line USB3.0 Receiver PHY Figure 8. Measurement Setup to collect the Eye Pattern on a Reference Board with TPD2EUSB30/A Eye Pattern Measurement Point Pattern Generator 36” Lossy Transmission Line TPD2EUSB30 USB3.0 Receiver PHY Figure 9. Measurement Setup to collect the Eye Pattern on a Reference Board with TPD2EUSB30/A Figure 10. Lab Setup for the Eye-Pattern Measurement with TPDxEUSB30/A 6 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30 TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30 www.ti.com SLVSAC2A – AUGUST 2010 – REVISED DECEMBER 2010 Figure 11. Output Eye Diagram Without Figure 12. Output Eye Diagram with the TPD2EUSB30/A (Figure 8 Setup, 5 Gbps Data Rate) TPD2EUSB30/A (Figure 8 Setup, 5 Gbps Data Rate) Figure 13. Output Eye Diagram Without the TPD4EUSB30 (5 Gbps Data Rate) Figure 14. Output Eye Diagram with the TPD4EUSB30 (5 Gbps Data Rate) Figure 15. TPDxEUSB30/A EVM – TPD4EUSB30 Side Figure 16. TPDxEUSB30/A EVM – TPD2EUSB30/A Side Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30 7 TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30 SLVSAC2A – AUGUST 2010 – REVISED DECEMBER 2010 www.ti.com REVISION HISTORY Changes from Original (August 2010) to Revision A • 8 Page Added TPS2EUSB30A part to document. ............................................................................................................................ 1 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30 PACKAGE OPTION ADDENDUM www.ti.com 13-Jan-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TPD2EUSB30ADRTR ACTIVE SOT DRT 3 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples TPD2EUSB30DRTR ACTIVE SOT DRT 3 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples TPD4EUSB30DQAR ACTIVE SON DQA 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Jan-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPD2EUSB30ADRTR Package Package Pins Type Drawing SOT DRT SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q3 TPD2EUSB30DRTR SOT DRT 3 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q3 TPD4EUSB30DQAR SON DQA 10 3000 180.0 8.4 1.3 2.83 0.65 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Jan-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPD2EUSB30ADRTR SOT DRT 3 3000 202.0 201.0 28.0 TPD2EUSB30DRTR SOT DRT 3 3000 202.0 201.0 28.0 TPD4EUSB30DQAR SON DQA 10 3000 202.0 201.0 28.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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