LF48212 LF48212 DEVICES INCORPORATED 12 x 12-bit Alpha Mixer 12 x 12-bit Alpha Mixer DEVICES INCORPORATED FEATURES DESCRIPTION ❑ 50 MHz Data and Computation Rate The LF48212 is a high-speed video alpha mixer capable of mixing video signals at real-time video rates. It takes two 12-bit video signals and mixes them together using an alpha mix factor. Alpha determines the weighting that each video signal receives during the mix operation. The input video data can be in either unsigned or two’s complement format, but both inputs must be in the ❑ Two’s Complement or Unsigned Operands ❑ On-board Programmable Delay Stages ❑ Programmable Output Rounding ❑ Replaces Harris HSP48212 ❑ Package Styles Available: • 68-pin PLCC, J-Lead • 64-pin PQFP same format. Independently controlled programmable delay stages are provided for the input and control signals to allow for allignment of input data if necessary. The delay stages can be programmed to have from 0 to 7 delays. The 13-bit output of the alpha mixer is registered with three-state drivers and may be rounded to 8, 10, 12, or 13-bits. LF48212 BLOCK DIAGRAM α11-0 12 BYPASS DELAY CONTROL REGISTER DEL DINA11-0 DINB11-0 12 12 15 LD 0-7 0-7 0-7 FORMAT FORMAT α 1.0 – α CLK MIXEN OE TC 4 0-7 ADJUST 4 RND1-0 0-7 FORMAT 2 13 NOTE: NUMBERS IN REGISTERS INDICATE NUMBER OF PIPELINE DELAYS. DOUT12-0 Video Imaging Products 1 08/16/2000–LDS.48212-F LF48212 DEVICES INCORPORATED SIGNAL DEFINITIONS 12 x 12-bit Alpha Mixer FIGURE 1. ALPHA MIX INPUT FORMAT Power VCC and GND 11 10 9 8 7 6 5 4 3 2 1 0 20 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8 2–9 2–10 2–11 +5 V power supply. All pins must be connected. Clock CLK — Master Clock Outputs The rising edge of CLK strobes all enabled registers except for the Delay Control Register. DOUT12-0 — Data Output DOUT12-0 is the 13-bit registered data output port. Inputs Controls DINA11-0 — Pixel Data Input A TC — Data Format Control DINA11-0 is one of the 12-bit registered data input ports. Data is latched on the rising edge of CLK. TC determines if the input data is in unsigned or two’s complement format. If TC is LOW, the data is in two’s complement format. If TC is HIGH, the data is in unsigned format. Data present on TC is latched on the rising edge of CLK. TC only affects the data that is being latched into the LF48212. Changing TC does not affect internal data already in the pipeline. DINB11-0 — Pixel Data Input B DINB11-0 is the other 12-bit registered data input port. Data is latched on the rising edge of CLK. α11-0 — Alpha Mix Input α11-0 determines the weighting applied to the data input signals before being mixed together. DINA11-0 and DINB11-0 receive weightings of α and 1.0 – α respectively. α11-0 is unsigned and restricted to the range of 0 to 1.0. Figure 1 shows the data format for α11-0. If a value greater than 1.0 is latched into the Alpha Mix Input, internal circuitry will force the value to be equal to 1.0. Data is latched on the rising edge of CLK. DEL — Delay Data Input DEL is used to load the Delay Control Register. The Delay Control Register contains a 15-bit value which determines the number of delay stages added to the input and control signals. The 15-bit data value is loaded serially into the Delay Control Register using DEL and LD. Data present on DEL is latched on the rising edge of LD. the Delay Control Register with the appropriate value. Note that this signal is not intended to change during active operation of the LF48212. RND1-0 — Output Rounding Control MIXEN — Alpha Mix Input Enable When HIGH, data on α11-0 is latched into the LF48212 on the rising edge of CLK. When LOW, data on α11-0 is not latched and the last value loaded is held as the alpha mix value. LD — Load Strobe The rising edge of LD latches the data on DEL into the Delay Control Register. RND1-0 determines how the output of the LF48212 is rounded. The output may be rounded to 8, 10, 12, or 13-bits. Table 1 lists the different rounding possibilities and the associated value for RND1-0. Rounding is accomplished by adding a “1” to the bit to the right of what will become the least significant bit. Then the bit that had the “1” added to it and all bits to the right of it are set to “0”. Data present on RND1-0 is latched on the rising edge of CLK. When RND1-0 is latched in, it only applies to the video input data latched in at the same time. Changing RND1-0 does not affect the rounding format for internal data already in the pipeline. OE — Output Enable When OE is LOW, DOUT12-0 is enabled for output. When OE is HIGH, DOUT12-0 is placed in a highimpedance state. BYPASS — Bypass Delay Stage Control The BYPASS control is used to bypass the internal programmable delay stages. When BYPASS is set HIGH, the Delay Control Register will automatically be loaded with a “0”. This will set the number of programmable delay stages to zero for all input and control signals. When BYPASS is LOW, the desired number of delay stages can be set by loading TABLE 1. RND1-0 OUTPUT ROUNDING ROUNDING FORMAT 00 Round to 8-bits 01 Round to 10-bits 10 Round to 12-bits 11 Round to 13-bits Video Imaging Products 2 08/16/2000–LDS.48212-F LF48212 DEVICES INCORPORATED FUNCTIONAL DESCRIPTION The two video signals to be mixed together are input to the LF48212 using DINA11-0 and DINB11-0. Data present on DINA11-0 and DINB11-0 is latched on the rising edge of CLK. The input data may be in either unsigned or two’s complement format, but both inputs must be in the same format. TC determines the format of the input data. When TC is HIGH, the input data is in unsigned format. When TC is LOW, the input data is in two’s complement format. TC is latched on the rising edge of CLK and only affects the input data latched in at the same time. The data already in the pipeline is not affected when TC changes. DINA11-0 and DINB11-0 are mixed together using an alpha mix factor (α11-0) as defined by the equation listed in Figure 2. α11-0 is unsigned and restricted to the range of 0 to 1.0. MIXEN controls the loading of alpha mix data. When MIXEN is HIGH, data present on α11-0 is latched on the rising edge of CLK. When MIXEN is LOW, data present on α11-0 is not latched and the last value loaded is held as the alpha mix value. It is possible to add extra delay stages to the input data and control signals by using the programmable delay stages. The 15-bit value (DELAY14-0) stored in the Delay Control Register determines the number of delay stages added. DELAY14-0 is divided into 5 groups of 3-bits each. Each 3-bit group contains the delay information for one of the input data or control signals. Figure 3 shows the block diagram of the Delay Control Register as well as a list of the input data and control signals that may be delayed and the DELAY signals that control them. The delay length can be programmed to be from 0 to 7 stages. The delay length is set by loading the binary equivalent of the desired delay length into the appropriate 3-bit group. For example, to add four extra 12 x 12-bit Alpha Mixer delay stages to DINB11-0, DELAY5-3 should be set to “100”. DELAY14-0 is loaded serially into the Delay Control Register using DEL and LD. DELAY0 is the first value loaded and DELAY14 is the last. Data present on DEL is latched on the rising edge of LD. BYPASS is used to disable the programmable delay stages. When BYPASS is HIGH, the Delay Control Register is automatically loaded with a “0”. This sets all programmable delay stages to a length of zero. When BYPASS is LOW, the Delay Control Register may be loaded to set the desired number of delay stages. Note that BYPASS is not intended to change during active operation of the LF48212. of the internal summer output is not needed. The Adjust stage takes the output of the internal summer and left shifts the data one bit position. This removes the MSB of the internal summer output and provides one more bit of precision for the output data. The output data of the LF48212 may be rounded to 8, 10, 12, or 13-bits. RND1-0 determines how the output is rounded (See Table 1). RND1-0 is latched on the rising edge of CLK and only affects the input data latched in at the same time. The data already in the pipeline is not affected when RND1-0 changes. FIGURE 2. The Adjust stage of the LF48212 is used to maximize the precision of the output data. Since α can never be larger than 1.0, the most significant bit OUTPUT EQUATION OUTPUT = α(DINA) + (1 – α)DINB FIGURE 3. DELAY CONTROL REGISTER BLOCK DIAGRAM DELAY14 DELAY13 DEL D Q LD D Q LD D Q RND1-0 DELAY DELAY12 LD DELAY11 DELAY10 D Q D Q LD D Q TC DELAY DELAY9 LD DELAY8 DELAY7 D Q D Q LD D Q α11-0 DELAY DELAY6 LD DELAY5 DELAY4 D Q D Q LD D Q DINB11-0 DELAY DELAY3 LD DELAY2 DELAY1 D Q D LD Q D Q DINA11-0 DELAY DELAY0 LD Video Imaging Products 3 08/16/2000–LDS.48212-F LF48212 DEVICES INCORPORATED 12 x 12-bit Alpha Mixer MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) Storage temperature ........................................................................................................... –65°C to +150°C Operating ambient temperature ........................................................................................... –55°C to +125°C VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V Input signal with respect to ground ............................................................................... –0.5 V to V CC + 0.5 V Signal applied to high impedance output ...................................................................... –0.5 V to VCC + 0.5 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ............................................................................................................................... > 400 mA OPERATING CONDITIONS To meet specified electrical and switching characteristics Mode Temperature Range (Ambient) Active Operation, Commercial 0°C to +70°C Supply Voltage 4.75 V ≤ VCC ≤ 5.25 V ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) Symbol Parameter Test Condition Min VOH Output High Voltage VCC = Min., IOH = –400 µA 2.6 VOL Output Low Voltage VCC = Min., IOL = 2.0 mA VIH Input High Voltage VIL Input Low Voltage (Note 3) IIX Input Current IOZ Typ Max Unit V 0.4 V 2.0 VCC V 0.0 0.8 V Ground ≤ VIN ≤ VCC (Note 12) ±10 µA Output Leakage Current Ground ≤ VOUT ≤ VCC (Note 12) ±10 µA ICC1 VCC Current, Dynamic (Notes 5, 6) 120 mA ICC2 VCC Current, Quiescent (Note 7) 500 µA CIN Input Capacitance TA = 25°C, f = 1 MHz 10 pF COUT Output Capacitance TA = 25°C, f = 1 MHz 10 pF Video Imaging Products 4 08/16/2000–LDS.48212-F LF48212 DEVICES INCORPORATED 12 x 12-bit Alpha Mixer SWITCHING CHARACTERISTICS COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) LF48212– 25 20 Symbol Parameter Min Max Min Max tCYC Cycle Time 25 20 tPW Clock Pulse Width 10 10 tS Input Setup Time 11 11 tH Input Hold Time 0 0 tD Output Delay 14 14 tENA Three-State Output Enable Delay (Note 11) 13 13 tDIS Three-State Output Disable Delay (Note 11) 13 13 SWITCHING WAVEFORMS: DATA I/O tCYC tPW tPW CLK tS tH tS tH tS tH DINA11-0 DINB11-0 α11-0 CONTROLS* OE tD tDIS tENA HIGH IMPEDANCE DOUT12-0 *includes MIXEN, TC, and RND1-0. Video Imaging Products 5 08/16/2000–LDS.48212-F LF48212 DEVICES INCORPORATED 12 x 12-bit Alpha Mixer COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) LF48212– 25 Symbol 20 Parameter Min tLC LD Cycle Time 25 20 tLPW LD Pulse Width 10 10 tDS DEL Setup Time 12 12 tDH DEL Hold Time 0 0 SWITCHING WAVEFORMS: Max Min Max DELAY CONTROL REGISTER DATA tLC tLPW tLPW LD tDS tDH DEL Video Imaging Products 6 08/16/2000–LDS.48212-F LF48212 DEVICES INCORPORATED 12 x 12-bit Alpha Mixer NOTES 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max 2. The products described by this spec- respectively. Alternatively, a diode ification include internal circuitry de- bridge with upper and lower current signed to protect the chip from damagsources of I OH and I OL respectively, ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF less, conventional precautions should minimum, and may be distributed. be observed during storage, handling, and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current stress values. pulses and fast turn-on/turn-off times. As a result, care must be exercised in the 3. This device provides hard clamping of testing of this device. The following transient undershoot and overshoot. In- measures are recommended: put levels below ground or above VCC will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be VCC + 0.6 V. The device can withstand installed between VCC and Ground indefinite operation with inputs in the leads as close to the Device Under Test range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors tion will not be adversely affected, how- should be installed between device VCC ever, input current levels will be well in and the tester common, and device ground and tester common. excess of 100 mA. 4. Actual test conditions may vary from b. Ground and VCC supply planes those designated but operation is guar- must be brought directly to the DUT anteed as specified. socket or contactor fingers. 5. Supply current for a given applica- c. Input voltages should be adjusted to tion can be accurately approximated by: compensate for inductive ground and VCC noise to maintain required DUT input NCV2 F levels relative to the DUT ground pin. 4 where 10. Each parameter is shown as a min- 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. FIGURE A. OUTPUT LOADING CIRCUIT S1 DUT IOL VTH CL IOH FIGURE B. THRESHOLD LEVELS tENA OE Z tDIS 1.5 V 1.5 V 3.5V Vth 0 1.5 V 1.5 V Z 1 VOL* 0.2 V VOH* 0.2 V 0 Z 1 Z 0V Vth VOL* Measured VOL with IOH = –10mA and IOL = 10mA VOH* Measured VOH with IOH = –10mA and IOL = 10mA imum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the exter6. Tested with all outputs changing ev- nal system must supply at least that ery cycle and no load, at a 40 MHz clock much time to meet the worst-case requirements of all parts. Responses from rate. the internal circuitry are specified from 7. Tested with all inputs within 0.1 V of the point of view of the device. Output VCC or Ground, no load. delay, for example, is specified as a 8. These parameters are guaranteed maximum since worst-case operation of any device always provides data within but not 100% tested. that time. N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency Video Imaging Products 7 08/16/2000–LDS.48212-F LF48212 DEVICES INCORPORATED 12 x 12-bit Alpha Mixer ORDERING INFORMATION BYPASS α8 α9 α10 α11 VCC α6 α7 10 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 11 59 12 58 13 57 14 56 15 55 16 54 17 Top View 18 19 53 52 51 20 50 21 49 22 48 23 47 24 46 25 45 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 OE DOUT12 DOUT11 DOUT10 DOUT9 GND DOUT8 DOUT7 NC DOUT6 DOUT5 VCC DOUT4 DOUT3 DOUT2 DOUT1 DOUT0 LD TC DINA11 DINA10 DINA9 VCC DINA8 DINA7 NC DINA6 DINA5 DINA4 GND DINA3 DINA2 DINA1 DINA0 DINB11 DINB10 DINB9 DINB8 DINB7 DINB6 GND DINB5 NC DINB4 DINB3 DINB2 DINB1 DINB0 RND1 RND0 DEL NC α0 α1 α2 α3 α4 α5 CLK MIXEN 68-pin Plastic J-Lead Chip Carrier (J2) Speed 0°C to +70°C — COMMERCIAL SCREENING 25 ns 20 ns LF48212JC25 LF48212JC20 Video Imaging Products 8 08/16/2000–LDS.48212-F LF48212 DEVICES INCORPORATED 12 x 12-bit Alpha Mixer ORDERING INFORMATION BYPASS α8 α9 α10 α11 VCC 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 α0 α1 α2 α3 α4 α5 α6 α7 CLK MIXEN 64-pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Top View 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 OE DOUT12 DOUT11 DOUT10 DOUT9 GND DOUT8 DOUT7 DOUT6 DOUT5 VCC DOUT4 DOUT3 DOUT2 DOUT1 DOUT0 LD TC DINA11 DINA10 DINA9 VCC DINA8 DINA7 DINA6 DINA5 DINA4 GND DINA3 DINA2 DINA1 DINA0 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DINB11 DINB10 DINB9 DINB8 DINB7 DINB6 GND DINB5 DINB4 DINB3 DINB2 DINB1 DINB0 RND1 RND0 DEL Plastic Quad Flatpack (Q3) Speed 0°C to +70°C — COMMERCIAL SCREENING 25 ns 20 ns LF48212QC25 LF48212QC20 Video Imaging Products 9 08/16/2000–LDS.48212-F