PRELIMINARY V61C518256 32K X 8 HIGH SPEED STATIC RAM MOSEL VITELIC Features Description ■ High-speed: 10, 12, 15 ns ■ Low Power Dissipation: – CMOS Standby: 0.5 mA (Max.) ■ Fully static operation ■ All inputs and outputs directly compatible ■ Three state outputs ■ Ultra low data retention current (VCC = 2V) ■ Single 5V ± 10% Power Supply ■ Packages – 28-pin TSOP (Standard) – 28-pin 300 mil SOJ The V61C518256 is a 262,144-bit static random access memory organized as 32,768 words by 8 bits. It is built with MOSEL VITELIC’s high performance CMOS process. Inputs and threestate outputs are TTL compatible and allow for direct interfacing with common system bus structures. Functional Block Diagram A0 VCC A1 Row Decoder A6 GND 512 x 512 Memory Array A10 A13 A14 I/O0 Column I/O Input Data Circuit Column Decoder I/O7 A2 CE OE WE A5 A11 A12 Control Circuit 518256-01 Device Usage Chart Operating Temperature Range T N R 10 12 15 Temperature Mark 0°C to 70 °C • • • • • • Blank V61C518256 Rev. 0.3 July 1998 Package Outline Access Time (ns) 1 V61C518256 MOSEL VITELIC Pin Descriptions WE Write Enable Input An active LOW input, WE input controls read and write operations. When CE and WE inputs are both LOW, the data present on the I/O pins will be written into the selected memory location. A0–A14 Address Inputs These 15 address inputs select one of the 32,768 x 8 bit segments in the RAM. CE Chip Enable Inputs CE is an active LOW input. Chip Enable must be LOW when reading from or writing to the device. When HIGH, the device is in standby mode with I/O pins in the high impedance state. I/O0–I/O7 Data Input and Data Output Ports These 8 bidirectional ports are used to read data from and write data into the RAM. OE Output Enable Input The Output Enable input is active LOW. When OE is LOW with CE LOW and WE HIGH, data of the selected memory location will be available on the I/O pins. When OE is HIGH, the I/O pins will be in the high impedance state. VCC Power Supply GND Ground Pin Configurations (Top View) 28-Pin SOJ 28-Pin TSOP (Standard) A14 1 28 VCC A12 2 27 WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 OE A2 8 21 A10 A1 9 20 CE A0 10 19 I/O7 I/O0 11 18 I/O6 I/O1 12 17 I/O5 I/O2 13 16 I/O4 GND 14 15 I/O3 OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 21 20 19 18 17 16 15 14 13 12 11 10 9 8 518256-03 518256-01 V61C518256 Rev. 0.3 July 1998 22 23 24 25 26 27 28 1 2 3 4 5 6 7 2 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 V61C518256 MOSEL VITELIC Part Number Information V MOSEL-VITELIC MANUFACTURED 61 C 51 8 256 – TEMP. SRAM FAMILY OPERATING VOLTAGE DENSITY SPEED PKG BLANK = 0¡C to 70¡C 256K 61 = STANDARD T = TSOP STANDARD C = CMOS PROCESS R = 300-mil SOJ 51 = 5V PWR. ORGANIZATION 10 ns 12 ns 15 ns 8 = 8-bit BLANK = STANDARD 518256-05 Absolute Maximum Ratings (1) Symbol Parameter Commercial Units VCC Supply Voltage -0.5 to +7 V VN Input Voltage -0.5 to +7 V VDQ Input/Output Voltage Applied VCC + 0.5 V TBIAS Temperature Under Bias -55 to +85 °C TSTG Storage Temperature -55 to +125 °C NOTE: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Capacitance* Truth Table TA = 25°C, f = 1.0MHz Symbol Parameter CIN Input Capacitance COUT Output Capacitance Max. Unit Mode CE OE WE I/O Operation VIN = 0V 6 pF Standby H X X High Z VI/O = 0V 8 pF Read L L H DOUT Read L H H High Z Write L X L DIN Conditions NOTE: * This parameter is guaranteed by design and not tested. NOTE: X = Don’t Care, L = LOW, H = HIGH V61C518256 Rev. 0.3 July 1998 3 V61C518256 MOSEL VITELIC DC Electrical Characteristics (over all temperature ranges, VCC = 5V ± 10%) Symbol Min. Typ. Max. Units VIL Input LOW Voltage(1,2) -0.5 — 0.8 V VIH Input HIGH Voltage(1) 2.2 — 6 V IIL Input Leakage Current VCC = Max, VIN = 0V to VCC -5 — 5 mA IOL Output Leakage Current VCC = Max, CE = VIH, VOUT = 0V to VCC -5 — 5 mA VOL Output LOW Voltage VCC = Min, IOL = 8mA — — 0.4 V VOH Output HIGH Voltage VCC = Min, IOH = -4mA 2.4 — — V Com.(4) Ind. Units Symbol Parameter Test Conditions Parameter ICC1 Average Operating Current, CE £ VIL Output Open, VCC = Max., f = fMAX(3) 110 130 mA ISB TTL Standby Current CE ³ VIH, VCC = Max. 25 40 mA ISB1 CMOS Standby Current, CE ³ VCC – 0.2V, VIN ³ VCC – 0.2V or VIN £ 0.2V, VCC = Max. 1 2 mA NOTES: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. VIL (Min.) = -3.0V for pulse width < 20ns. 3. fMAX = 1/tRC. 4. Maximum values. V61C518256 Rev. 0.3 July 1998 4 V61C518256 MOSEL VITELIC Data Retention Characteristics Symbol Min. Typ.(2) Max. Units 2.0 — 5.5 V Com’l — — 150 mA Ind. — — 200 0 — — ns — — ns Parameter VDR CE ³ VCC – 0.2V VCC for Data Retention ICCDR Data Retention Current VDR = 3.0V, CE ³ VDR – 0.2V Chip Deselect to Data Retention Time tCDR tR Operation Recovery Time (see Retention Waveform) tRC (1) NOTES: 1. tRC = Read Cycle Time 2. TA = +25°C. Low VCC Data Retention Waveform Data Retention Mode VCC 4.5V VDR ³ 2V tCDR CE 4.5V tR VDR 2.2V 2.2V 518256-07 AC Test Conditions Key to Switching Waveforms Input Pulse Levels 0 to 3V Input Rise and Fall Times 3 ns Timing Reference Levels 1.5V Output Load WAVEFORM see below INPUTS OUTPUTS MUST BE STEADY WILL BE STEADY MAY CHANGE FROM H TO L WILL BE CHANGING FROM H TO L MAY CHANGE FROM L TO H WILL BE CHANGING FROM L TO H DON'T CARE: ANY CHANGE PERMITTED CHANGING: STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE “OFF” STATE AC Test Loads and Waveforms +5V 480 ½ I/O Pin 255 ½ CL = 30 pF* * Includes scope and jig capacitance +5V 480 ½ I/O Pin 255 ½ 5 pF* Output load for tCLZ, tCHZ, tOHZ, tOLZ, tWZ, tOW 518256-06 V61C518256 Rev. 0.3 July 1998 5 V61C518256 MOSEL VITELIC AC Electrical Characteristics (over all temperature ranges) Read Cycle Parameter Name -10 Parameter -12 -15 Min. Max. Min. Max. Min. Max. Unit tRC Read Cycle Time 10 — 12 — 15 — ns tAA Address Access Time — 10 — 12 — 15 ns tACS Chip Enable Access Time — 10 — 12 — 15 ns tOE Output Enable to Output Valid — 5 — 6 — 7 ns tCLZ Chip Enable to Output in Low Z 2 — 3 — 3 — ns tOLZ Output Enable to Output in Low Z 0 — 0 — 0 — ns tCHZ Chip Disable to Output in High Z 0 2 0 3 0 4 ns tOHZ Output Disable to Output in High Z 0 2 0 3 0 4 ns tOH Output Hold from Address Change 2 — 3 — 3 — ns Write Cycle Parameter Name -10 Parameter -12 -15 Min. Max. Min. Max. Min. Max. Unit tWC Write Cycle Time 10 — 12 — 15 — ns tCW Chip Enable to End of Write 9 — 10 — 12 — ns tAS Address Setup Time 0 — 0 — 0 — ns tAW Address Valid to End of Write 9 — 10 — 12 — ns tWP Write Pulse Width 8 — 9 — 11 — ns tAH Address Hold from End of Write — 0.5 — 0.5 — 0.5 ns tWHZ Write to Output High-Z 0 5 0 5 0 5 ns tDW Data Setup to End of Write 6 — 7 — 8 — ns tDH Data Hold from End of Write 0 — 0 — 0 — ns tOW Output Active from End of Write 3 — 3 — 3 — ns V61C518256 Rev. 0.3 July 1998 6 V61C518256 MOSEL VITELIC Switching Waveforms (Read Cycle) Read Cycle 1(1, 2) tRC ADDRESS tAA OE tOE tOLZ tOHZ(5) I/O 518256-08 Read Cycle 2(1, 2, 4) tRC ADDRESS tOH tAA tOH I/O 518256-09 Read Cycle 3(1, 3, 4) ADDRESS tACS CE tCLZ(5) tCHZ(5) I/O 518256-10 NOTES: 1. WE = VIH. 2. CE = VIL. 3. Address valid prior to or coincident with CE transition LOW. 4. OE = VIL. 5. Transition is measured ±500mV from steady state with CL = 5pF. This parameter is guaranteed and not 100% tested. V61C518256 Rev. 0.3 July 1998 7 V61C518256 MOSEL VITELIC Switching Waveforms (Write Cycle) Write Cycle 1 (WE Controlled)(4) tWC ADDRESS tAH(2) tCW(6) CE tAW tAS WE tWP(1) OUTPUT tWHZ(3) tDW tDH INPUT 518256-11 Write Cycle 2 (CE Controlled)(4) tWC ADDRESS tAS tAH(2) tCW(6) CE tAW WE OUTPUT Hi-Z tDW tDH (5) INPUT 518256-12 NOTES: 1. The internal write time of the memory is defined by the overlap of CE active and WE low. Both signals must be active to initiate and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 2. tAH is measured from the earlier of CE or WE going HIGH. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 4. OE = VIL or VIH. However it is recommended to keep OE at VIH during write cycle to avoid bus contention. 5. If CE is LOW during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 6. tCW is measured from CE going LOW to the end of write. V61C518256 Rev. 0.3 July 1998 8 V61C518256 MOSEL VITELIC Package Diagrams 28-pin 300 mil SOJ 14 0.265 ±0.020 [6.731 ±0.508] 1 0.334 ±0.013 [8.484 ±0.330] 15 +0.005 0.300(1)–0.008 28 +0.127 7.620 –0.203 0.715 ± 0.015(1) [18.161 ± 0.381] 0.011 ±0.003 [0.279 ±0.076] 0.100 ±0.005 [2.540 ±0.127] 0.029 ± 0.003 [0.737 ± 0.076] 0.134 ±0.006 [3.404 ±0.152] 0.034 ±0.011 [0.836 ±0.279] Unit in inches [mm] 0.050 TYP [1.270 TYP] 0.019 ±0.003 [0.483 ±0.076] 0.004 [0.102] 0.020 MIN [0.508 MIN] (1) Does not include mold flash protrusion and should be measured from the bottom of the package. 28-Pin TSOP Unit in inches [mm] 0.463 ±0.003 [11.76 ± 0.076] 0.046 ±0.004 [1.17 ± 0.102] 0.528 ±0.008 [13.41 ± 0.203] 0.315 ±0.004 [8.00 ± 0.102] +0.007 0.020 –0.008 +0.178 0.508 –0.305 V61C518256 Rev. 0.3 July 1998 0.006 ±0.002 [0.152 ± 0.051] 0.022 [0.559] BSC 9 0.006 ±0.004 [0.152 ± 0.102] V61C518256 MOSEL VITELIC Notes V61C518256 Rev. 0.3 July 1998 10 V61C518256 MOSEL VITELIC Notes V61C518256 Rev. 0.3 July 1998 11 MOSEL VITELIC WORLDWIDE OFFICES V61C518256 U.S.A. TAIWAN JAPAN 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 011-886-2-545-1213 FAX: 011-886-2-545-1209 WBG MARINE WEST 25F 6, NAKASE 2-CHOME MIHAMA-KU, CHIBA-SHI CHIBA 261-71 PHONE: 011-81-43-299-6000 FAX: 011-81-43-299-6555 HONG KONG 19 DAI FU STREET TAIPO INDUSTRIAL ESTATE TAIPO, NT, HONG KONG PHONE: 011-852-665-4883 FAX: 011-852-664-7535 1 CREATION ROAD I SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 011-886-35-783344 FAX: 011-886-35-792838 U.S. SALES OFFICES NORTHWESTERN SOUTHWESTERN CENTRAL & SOUTHEASTERN 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185 SUITE 200 5150 E. PACIFIC COAST HWY. LONG BEACH, CA 90804 PHONE: 562-498-3314 FAX: 562-597-2174 604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 972-690-1402 FAX: 972-690-0341 NORTHEASTERN SUITE 436 20 TRAFALGAR SQUARE NASHUA, NH 03063 PHONE: 603-889-4393 FAX: 603-889-9347 © Copyright 1997, MOSEL VITELIC Inc. The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC. MOSEL VITELIC 7/98 Printed in U.S.A. MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461