DATA SHEET
MOS INTEGRATED CIRCUIT
µPD16662
240 OUTPUT LCD COLUMN (SEGMENT) DRIVER WITH BUILT-IN RAM
The µPD16662 is a column (segment) driver which contains a RAM capable of full dot LCD drive.
With 240 outputs, this driver has a display RAM of 240 x 160 x 2 bits built in, and 4 gray scales of display are
possible. Any 4 gray scales can be selected from 25 levels of the gray scale pallet. The driver can be combined
with the µPD16667 to display from 240 x 160 dots to 480 x 320 dots.
Features
• Display RAM incorporated: 240 x 160 x 2 bits
• Logic voltage: 3.0V to 3.6V
• Duty: 1/160
• Output count: 240 outputs
• Capable of gray scale display: 4 gray scales (can be selected from 25 levels of the gray scale pallet)
• Memory management: packed pixel system
• 8/16-bit data base
Ordering Information
•
Part number
Package
µPD16662N -×××
TCP(TAB)
µPD16662N - 051
Standard TCP (OLB: 0.2 mm pitch; folding)
The TCP’s external shape is custom-ordered. Therefore, if you have a shape in mind, please contact an NEC
salesperson.
The information in this document is subject to change without notice.
Document No. S12738EJ3V0DS00 (3rd edition)
Date Published November 1998 NS CP (K)
Printed in Japan
The mark • shows major revised points.
©
1998
µPD16662
Pin name
Classification
CPU I/F
Control signals
Pin Name
Voltage
3.3 V
3.3 V
Note
I/O
Function
D0 to D15
I/O
Data bus 16
A0 to A16
I
Address bus 17
/CS
I
Chip select
/OE
I
Read signal
/WE
I
Write signal
/UBE
I
High byte enable
RDY
O
Ready signal to CPU (Ready state at H)
PL0
I
Specifies the LSI allocation locations (No. 0 to 3).
PL1
I
Specifies the LSI allocation locations (No. 0 to 3).
DIR
I
Specifies the liquid-crystal panel allocation direction
(longitudinal; lateral)
5.0 V
MS
I
Master/slave switching (Master mode at H)
BMODE
I
Data bus bit select pin ("H" = 8bit, "L" = 16bit)
/REFRH
I/O
Self diagnostic reset pin (Wired OR connection)
TEST
I
Test pin (Test mode at H, using the pull-down buffer)
/RESET
I
Reset
/DOFF
I
Display OFF signal input
OSC1
-
Oscillator pin
OSC2
-
Oscillator pin
STB
I/O
Column driving signal strobe
(MS signal "H" = output, MS signal "L" = input )
/FRM
I/O
Frame signal(MS pin "H" = output , MS pin "L" = input )
PULSE
I/O
25-gray level pulse modulation clock
L1
I/O
Row driver drive level selection signal (1st line)
L2
I/O
Row driver drive level selection signal (2nd line)
/DOUT
O
Display OFF signal output
Liquid-crystal drive
Y1 to Y240
O
Liquid-crystal drive output
Powers
GND
-
Ground (two 5-V pins; three 3-V pins)
VCC1
-
5-V power level
VCC2
-
3.3-V power level
V0
-
Liquid-crystal drive analog power
V1
-
Liquid-crystal drive analog power
V2
-
Liquid-crystal drive analog power
Remark /xxx indicates active low signal.
Note 3.3-V power pins : D0 - D15, A0 - A16, /CS, /OE, /WE, /UBE, RDY, BMODE, PL0, PL1, DIR, OSC1,
OSC2, /RESET, /DOFF, TEST, MS
5-V power pins
2
: STB, /FRM, L1, L2, /DOUT, PULSE
µPD16662
Block Diagram
DIR
PL0, PL1
TEST
A0 - A16
Address
input
control
Address
management
control
RAM
240 x 160 x 2 bit
Arbiter
Control
/CS, /OE,
/WE, /UBE
RDY
BMODE
D0 - D15
Data bus
control
/REFRH
Data latch (1)
/RESET
MS
STOP
OSC1
CR
oscillator
OSC2
/DOFF
Gray scale
generation
circuit
Data latch (2)
Internal timing
generation
Gray level control
Liquid crystal
timing generation
3.3 V operation
PULSE /FRM STB
Self-diagnosis
circuit
3.3 V operation
Level shifter
5.0 V operation
5.0 V operation
DEC
Liquid crystal drive circuit
240 outputs
PULSE
/FRM
STB /DOUT L1
L2
Y1 Y2 Y3
V0
V1
V2
Y240
3
µPD16662
Block Functions
(1) Address management circuit
The address management circuit converts addresses transferred from the system through A0 to A16 into addresses
compatible with the memory map of the built-in RAM. This function can be used to address up to 480 x 320 dots with
four of these LSIs, thus making it possible to configure a liquid crystal display system without difficulty. Moreover,
addresses 1FFF0H to 1FFFFH are allocated to the gray scale pallet register, making it possible to choose any 4 gray
scales from the 25-level pallet.
(2) Arbiter
The arbiter adjusts the contention between the RAM access from the system and the RAM read on the liquid-crystal
drive side.
(3) RAM
Static RAM (single port) of 240 by 160 by 2 bits
(4) Data bus control
This circuit controls the data transfer directions through the read/write from the system. It also performs an 8/16-bit
switch via the BMODE pin.
(5) Gray scale generation circuit
This circuit realizes the 25 levels by frame thinning out and pulse width modulation.
(6) Internal timing generation
Internal timing to each block is generated from /FRM and STB signals.
(7) CR oscillator
The CR oscillator generates the clock which will become a criterion of the frame frequency in master mode. 1/2592
of this oscillation becomes the frame frequency. For example, if the frame frequency is 70 Hz, the required oscillation
frequency is 181.44 kHz. As the CR oscillator has a built-in capacitor, adjust the required oscillation frequency with
an external resistor.
In slave mode, the oscillation is stopped.
(8) Liquid crystal timing generation
In master mode, /FRM (frame signal), STB (column drive signal strobe), and PULSE (25-gray-scale pallet pulse
modulation clock) are generated.
(9) Gray scale control
This circuit realizes a four-gray scale display.
(10) Data latch (1)
Reads and latches 240-pixel data from the RAM.
(11) Data latch (2)
Latches 240-pixel data synchronously with the STB signal.
4
µPD16662
(12) Level shifter
The level shifter converts from the operating voltage (3.3 V) of the internal circuit to the liquid-crystal drive circuit
and low driver interface voltage (5 V).
(13) DEC
Decodes the gray scale display data to make it compatible with the liquid-crystal drive voltages V0, V1 and V2 .
(14) Liquid crystal drive circuit
This circuit selects one of the liquid-crystal drive powers V0, V1, and V2, which are compatible with the gray scale
display data and the display OFF signal (/DOFF), to generate the liquid crystal applied voltage.
(15) Self diagnostic circuit
If the operation timing of the master chip and slave chip has deviated due to external noise, this circuit will detect
the problem and generate a total column/driver refresh signal.
Address map image diagram (Example of VGA-half size configuration)
Column direction specified with A7 to A0
Y1
Y240 Y1
Y240
L1
Address progress direction
Row direction
specified with
A16 to A8
No.0
L160
L1
No.2
Address progress direction
No.1
L160
Y240
No.3
Y1 Y240
Y1
5
µPD16662
Data bus
The byte data lined up on the data bus is based on the Little Endian - an NEC/Intel-series bus.
1. 16 bit data bus (BMODE = L)
• Bytes (8 bytes) access
Addresses proceed as
→
shown on right.
D0 to D7
D8 to D15
00000H
00001H
00002H
00003H
00004H
:
:
:
00005H
:
:
:
D0 to D7
D8 to D15
• Words (16 bits) access
00000H
Addresses proceed as
→
00002H
shown on right.
00004H
:
:
:
For the access from the system to be performed in units of words (16 bits), or of bytes (8 bytes), the /UBE (high
byte enable) and A0 are used to show whether valid data are in the bytes of either (or both) of D0 to D7 and D8 to
D15.
/CS
/OE
/UBE
A0
MODE
I/O
D0 to D7
D8 to D15
H
X
X
X
X
Not Selected
Hi-Z
Hi-Z
L
L
H
L
L
Read
Dout
Dout
L
H
Hi-Z
Dout
H
L
Dout
Hi-Z
L
H
L
L
L
Din
Din
L
H
X
Din
H
L
Din
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
L
H
H
X
X
L
X
X
H
H
Remark
X
: Don’t Care
Hi-Z : High impedance
6
/WE
Write
Output disable
µPD16662
2. 8 bit data bus (BMODE = H)
D0 to D7
00000H
Addresses proceed as
→
00001H
shown on right.
00002H
:
:
:
/CS
/OE
/WE
MODE
I/ O
D0 to D7
D8 to D15
H
X
X
Not Selected
Hi-Z
Note
L
L
H
Read
Dout
Note
L
H
L
Write
Din
Note
L
H
H
Output disable
Hi-Z
Note
Remark
X
: Don’t Care
Hi-Z : High impedance
Note Use D8 - D15 and /UBE to open or connect to the GND because they are internally pulled down when
BMODE = H.
7
µPD16662
Relationship between data bits and pixels
As the display is in four gray scales, each pixel consists of two bits.
The RAM is configured with four pixels (8 pixels per word) using the packed pixel system.
(1) BMODE = L
Bytes (8 bits) access
D0
D1
1 Pixel
D2
D3
D4
2 Pixel
D5
D6
3 Pixel
D7
D8
4 Pixel
D9
D10
5 Pixel
D11
6 Pixel
00000H
1
D12
D13
D14
7 Pixel
D15
8 Pixel
00001H
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel
Liquid-Crystal panel
00000H
00001H
00002H
00003H
Words (16 bits) access
D0
D1
1 Pixel
D2
D3
D4
2 Pixel
D5
D6
3 Pixel
D7
D8
4 Pixel
D9
D10
5 Pixel
D11
D12
6 Pixel
D13
D14
7 Pixel
D15
8 Pixel
00000H
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel
Liquid-Crystal panel
00000H
00002H
(2) BMODE = H
D0
D1
1 Pixel
D2
D3
D4
2 Pixel
D5
D6
3 Pixel
D7
D0
4 Pixel
D1
D2
5 Pixel
D3
6 Pixel
00000H
1
2
D4
D5
D6
7 Pixel
D7
8 Pixel
00001H
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel
Liquid-Crystal panel
00000H
8
00001H
00002H
00003H
µPD16662
Gray scale control
The µPD16662 gray scale control realizes 25 levels of the gray scale pallet through frame thinning and pulse width
modulation. It chooses four gray scales and records them in the gray scale pallet register before use.
Gray scale pallet register
Through the use of the gray scale pallet register, four gray scales are pre-selected from 25 levels. The gray scale
pallet register is allocated in addresses 1FFF0H to 1FFFFH, and the relationship between the register and the gray
scale data is shown in the following table. The initial values are also allocated as below. The gray scale pallet
register can set each column/driver configuration position (No.0 to 3) decided by PL0 and PL1.
Address
Configuration position
Gray scale data (Display data)
Note
Dn
Initial value
Note
No.
Dn+1
No.0
0
0
00000B
1FFF1H
0
1
01000B
1FFF2H
1
0
10000B
1FFF3H
1
1
11000B
0
0
00000B
1FFF5H
0
1
01000B
1FFF6H
1
0
10000B
1FFF7H
1
1
11000B
0
0
00000B
1FFF9H
0
1
01000B
1FFFAH
1
0
10000B
1FFFBH
1
1
11000B
0
0
00000B
1FFFDH
0
1
01000B
1FFFEH
1
0
10000B
1FFFFH
1
1
11000B
1FFF0H
1FFF4H
1FFF8H
1FFFCH
No.1
No.2
No.3
Note n = 0, 2, 4, 6
9
µPD16662
Relationship between gray scale and gray scale pallet data
The relationship between the gray scale and the gray scale pallet data that is set by the gray scale pallet register is
as follows.
PMODE
Gray scale palette data
Remark
D4
D3
D2
D1
D0
Pixel 0
0
0
0
0
0
Pixel 1
0
0
0
0
1
Pixel 2
0
0
0
1
0
Pixel 3
0
0
0
1
1
Pixel 4
0
0
1
0
0
Pixel 5
0
0
1
0
1
Pixel 6
0
0
1
1
0
Pixel 7
0
0
1
1
1
Pixel 8
0
1
0
0
0
Pixel 9
0
1
0
0
1
Pixel 10
0
1
0
1
0
Pixel 11
0
1
0
1
1
Pixel 12
0
1
1
0
0
Pixel 13
0
1
1
0
1
Pixel 14
0
1
1
1
0
Pixel 15
0
1
1
1
1
Pixel 16
1
0
0
0
0
Pixel 17
1
0
0
0
1
Pixel 18
1
0
0
1
0
Pixel 19
1
0
0
1
1
Pixel 20
1
0
1
0
0
Pixel 21
1
0
1
0
1
Pixel 22
1
0
1
1
0
Pixel 23
1
0
1
1
1
Pixel 24
1
1
0
0
0
10
OFF
1/3
2/3
ON
µPD16662
LSI arrangement and address management
Addresses can be managed to allow up to four of these LSIs to be used to configure a liquid-crystal display of up to
half VGA size (320 x 480 dots). Up to four of these LSIs can be connected on the same bus sharing the /CS, /WE,
and /OE pins. On the system side, one screen of the liquid crystal display can be treated as one memory area, and it
is not necessary to decode for more than one µPD16662. The PL0 and PL1 pins are used to specify LSI No. and to
determine the LSI arrangement. The DIR pins are used to determine the directions (vertical, horizontal) of the liquidcrystal display.
PL1
PL0
LSI No.
0
0
No. 0
0
1
No. 1
1
0
No. 2
1
1
No. 3
1. Addresses of the VGA half-size horizontally (DIR = "0")
Specified with A7 to A0
Column
Column
Y1
Specified
with
A16 to A8
X1 00000
Y240 Y1
00038
00002
00100
0003A
0003C
0013A
0013C
Y240
0003E
00076
00176
No.2
No.0
Row
00074
09E3A
09E3C
X160 09F00
09F02
09F38
09F3A
09F3C
09F3E
09F74
09F76
X1 0A000
0A002
0A038
0A03A
0A03C
0A03E
0A074
0A076
0A13A
0A13C
09E00
0A100
09E76
0A176
No.1
Row
No.3
13E00
X160 13F00
13F02
13F38
Y240
13E3A
13E3C
13F3A
13F3C
13E76
13F3E
13F74
Y1 Y240
Column
13F76
Y1
Column
11
12
Y240
Column
13F3A
13E3A
0A13A
Y1 Y240
13F3C
13F3E
13F76
13F74
13E3C
No.3
0A13C
0A03A
09F3A
13F38
0A038
09F38
00038
Column
No.1
No.0
13F02
0A002
09F02
00002
Y1
13F00
13E00
0A100
0A000
09F00
09E00
00100
00000
Y240
X1
X160
X1
X160
Row
13E76
0A176
0A03C
0A074
0A076
0A03E
09F3C
09F3E
09F74
09F76
0013A
0013C
09E3A
0003A
0003C
09E3C
No.2
0003E
09E76
00176
00074
Y240 Y1
Column
Specified
with
A7 to A0
00076
Y1
Column
µPD16662
2. Addresses of the VGA half-size horizontally (DIR = "1")
Specified with A16 to A8
Row
µPD16662
CPU Interface
1. Function of the RDY (Ready) pin
The built-in RAM is a single-port RAM. To prevent contention between the access from the CPU side and the
reading by the liquid-crystal drive side, the RDY pin performs a Wait operation on the CPU.
•
• Timing
A0 - A16, /UBE
/CS
/OE, /WE
Hi-Z
RDY
Hi-Z
Wait
Ready
Wait
• Connection of the RDY pin
The RDY pin uses a three-state buffer. The RDY pin should be connected to an external pull-up resister. If more
than one LSI are used, the RDY pins of each LSI are wired together.
VCC2
Pull-up resister
CPU
Ready input
RDY
Column driver
RDY
Column driver
13
µPD16662
•
2. Access Timing
(1) Display data read timing
A16 - A0
/UBE
/CS
/OE
RDY
D15 - D0
Hi-Z
Hi-Z
Hi-Z
Dout
Hi-Z
(2) Display data write timing
A16 - A0
/UBE
/CS
/OE
RDY
Hi-Z
D15 - D0
Hi-Z
Din
(3) Gray scale pallet data write timing
A16 - A0
/UBE
/CS
/OE
RDY
D4 - D0
14
Hi-Z
Din
µPD16662
Liquid-Crystal Timing Generation
1. Reset State
If the circuit is placed in the reset state, the internal counter is zero-cleared.
After cancelling the reset, the display OFF function operates during the 4-frame cycle even when the /DOFF pin is
at H.
/RESET
1
2
3
4
5
6
/FRM
/DOUT
Internal State
Display OFF
Display ON
15
µPD16662
2. Liquid-Crystal Timing Generating Circuit
If the circuit is set to Master mode when MS = H, the /FRM and STB signals are generated timed with a duty ratio
1/160.
Generates the driver drive voltage selection signals L1 and L2 for the row driver.
The /FRM is generated twice per frame. The STB is generated 81 times per half a frame; and 162 times per frame.
• Generation of /FRM and STB signals
OSC1
PLUSE
STB
1
2
/FRM
STB
81
1
2
81
1
2
81
1
2
Frame
• Generation of L1 and L2 signals
16
STB
1
2
3
4
…
1
2
3
4
…
1
2
3
4
…
1
2
3
4
…
L1
1
1
1
1
…
1
1
1
1
…
0
0
0
0
…
0
0
0
0
…
L2
1
0
1
0
…
0
1
0
1
…
0
1
0
1
…
1
0
1
0
…
µPD16662
Self diagnostic function
This is a function to check whether the timing of each column/driver has deviated due to external noise. The slave
chip compares the L1 and L2 generated internally with the L1 and L2 of the master chip, and when there is
discordance, it sends a total column/driver refresh signal. When a refresh signal is received, the internal reset is
activated and timing is initialized. In this case, the /REFRH = L time and the four frame interval display are turned
OFF. The L1, L2 discordance will be monitored at the rising edge of the FRM once every 1/2 frame.
L1 (Master)
discrepancy
L2 (Master)
L1 (Slave)
discrepancy
L2 (Slave)
/REFRH
initialization
initialization
• Block configuration drawing (slave side)
/RESET
Internal reset
/REFRH
Self-diagnosis circuit
L1
Internal L1 signal
L2
Internal L2 signal
17
µPD16662
System Configuration Example
An example of configuring a liquid-crystal panel of VGA half-size (480 × 320 dots lengthwise) by using four LSIs
and two row drivers.
• Each column driver sets the LSI No. with PL0, PL1 pins.
• The DIR pins of each column driver are all set to low level.
• Only one of the column drivers is set to the master; all the others are set to the slave. Signals are supplied from the
master column driver to the slave column driver and to the row driver.
• Connect a resistor for the oscillator to the OSC1 and OSC2 pins of the master. Leave the OSC1 and OSC2 pins of
the slave open.
• The signals from the system (D0 through D15, A0 through A16, /CS, /OE, /WE, /UBE, RDY, /RESET, and /DOFF)
are connected to all the column drivers in parallel. Connect a pull-up resistor to the RDY signal.
• The TEST pin is used to test the LSI. Open or connect this pin to GND when the system is configured.
VCC2
RDY
/DOFF
/RESET
D0 - D15
A0 - A16
Control
(/CS, /OE,
/WE, /UBE)
PULSE
STB
/FRM
/DOUT, /DOFF '
L1
L2
OSC1
Slave
No.1
Master
No.1
OSC2
/REFRH
Y1
Y240 Y1
Row
driver
160
Scanning
direction
Row
driver
160
Scanning
direction
Y240
Slave
No.1
Remark The /DOFF' pin is an input pin of µPD16667.
18
Y240
Y1 Y240
Slave
No.1
Y1
µPD16662
Chip set power-ON sequence
It is recommended to turn on power in the following sequence:
VCC2 → VCC1 → input → VDD, VEE → V1, V2
Be sure to turn on LCD driving power supplies V1 and V2 last.
ON
VCC2
OFF
VCC1
OFF
CPU I/F Note1
(A0 - A16, /CS, /OE, /WE,
/UBE, D0 - D15, /DOFF)
ON
4.5 V
0 s MIN.
3.3 V
0V
3.3 V
/RESET
0V
0.3 VCC2
0 s MIN.
100 ns MIN.
ON
VDD Note2
OFF
OFF
VEE Note2
ON
0 s MIN.
V1
ON
OFF
ON
V2
OFF
Notes 1. It is possible to input the selected pins (Pl0, PL1, DIR, MS, and BMODE) at the same time as VCC2.
2. It is not necessary to have VDD and VEE ON at the same time. VDD and VEE are the liquid crystal power
supply of row driver.
Caution Turn off power to the chip set in the reverse sequence to the turn-on sequence.
19
µPD16662
Example of layout of internal Schottky barrier diode of module to reinforce power supply
protection
(Use a Schottky barrier diode with Vf = 0.5 V MAX.)
VDD
VCC1
V2
V1
V0
VSS
VEE
Include the diodes enclosed in the dotted line in the above figure when V0 is not 0 V (GND).
Note VDD and VEE are the liquid crystal power supply of row driver.
20
µPD16662
Electrical specifications
1. Absolute Maximum Ratings (TA = +25 °C)
Parameter
Symbol
Rating
Unit
Notes
Supply voltage (1)
VCC1
−0.5 to +6.5
V
1
Supply voltage (2)
VCC2
−0.5 to +4.5
V
2
Input/Output voltage (1)
VI/O1
−0.5 to VCC1 +0.5
V
1
Input/Output voltage (2)
VI/O2
−0.5 to VCC2 +0.5
V
2
Input/Output voltage (3)
VI/O3
−0.5 to VCC1 +0.5
V
3, 4
Operating temperature
TA
−20 to +70
°C
Storage temperature
Tstg.
−40 to +125
°C
Notes 1. 5 V power signal (/FRM, STB, /DOUT, L1, L2, PULSE)
2. 3.3 V power signal (MS, DIR, PL0 to PL1, A0 to A16, /CS, /OE, /WE, /UBE, RDY, D0 to D15, /RESET,
OSC1, OSC2, /DOFF, TEST, BMODE, /REFRH)
3. Liquid-crystal drive powers (V0, V1, V2, Y1 to Y240)
4. V0 < V1 < V2
2. Recommended Operating Range (TA = 20 to +70 C, VO = 0 V)
Parameter
•
Symbol
MIN.
TYP.
MAX.
Unit
Supply voltage (1)
VCC1
4.5
5.0
5.5
V
Supply voltage (2)
VCC2
3.0
3.3
3.6
V
Input voltage (1)
VI1
0
VCC1
V
1
Input voltage (2)
VI2
0
VCC2
V
2
V1 Input voltage
V1
V0
V2
V
V2 Input voltage
V2
V1
VCC1
V
ROSC
30
90
kΩ
External resistance for OSC
62
Notes
Notes 1. 5 V power signal (/FRM, STB, L1, L2, PULSE)
2. 3.3 V power signal (MS, DIR, PL0 to PL1, A0 to A16, /CS, /OE, /WE, /UBE, RDY, D0 to D15, /RESET,
OSC1, OSC2, /DOFF, TEST, BMODE, /REFRH)
21
µPD16662
3. DC Characteristics
(Unless otherwise specified, VCC1 = 4.5 to 5.5 V, VCC2 = 3.0 to 3.6 V. V0 = 0 V, V1 = 1.4 to 2.0 V, V2 = 2.8 to 4.0 V, TA
= −20 to +70 °C)
Parameter
High-level input voltage (1)
V CC1
Low-level input voltage (1)
High-level input voltage (2)
Symbol
MIN.
VIH1
0.7 VCC1
VIL1
VCC2
VIH2
Low-level input voltage (2)
VIL2
High-level output voltage (1)
VIH3
Low-level output voltage (1)
VIL4
High-level output voltage (2)
VCC1
VOH1
Low-level output voltage (2)
VOL1
High-level output voltage (3)
VOH2
Low-level output voltage (3)
VOL3
High-level output voltage (3)
TYP.
VCC2
Low-level output voltage (3)
Input leakage current (1)
VOH3
MAX.
0.3VCC1
0.7 VCC2
0.3VCC2
0.8 VCC2
0.2VCC2
VCC1 −0.4
0.4
VCC1 −0.4
0.4
VCC2 −0.4
Unit
Remark
Notes
V
1
V
1
V
2
V
2
V
4
V
4
V
IOH = −1 mA
3
V
IOL = 2 mA
3
V
IOH = −2 mA
1
V
IOL = 4 mA
V
IOH = −1 mA
5
5
VOL3
0.4
V
IOL = 2 mA
II1
±10
µA
Without TEST pin,
1, 4
VI = VCC2 or GND
Input leakage current (2)
II2
10
40
100
µA
Pull down (TEST pin )
VI = VCC2
Current consumption for
VCC1
IMAS1
100
µA
master
6
VCC2
IMAS2
250
µA
master
6
VCC1
ISLV1
60
µA
slave
6
VCC2
ISLV2
150
µA
slave
6
2
kΩ
display operation (1)
Current consumption for
display operation (2)
Current consumption for
display operation (3)
Current consumption for
display operation (4)
Liquid crystal drive output on
RON
1
7
resistance
Notes 1. 5 V signal (/FRM, STB, L1, L2, PULSE)
2. 3.3 V signal (MS, DIR, PL0 to PL1, A0 to A16, /CS, /OE, /WE, /UBE, RDY, D0 to D15, /RESET, /DOFF,
TEST, BMODE)
3. /DOUT pin
4. /REFRH pin
5. D0 to 15, RDY, and OSC2 pins
6. With the frame frequency at 70 Hz without output load and CPU no access (D0 to D15, A0 to A16, /UBE =
GND, /CS, /OE, /WE = VCC2)
7. This refers to the resistance value between a Y pin and a V pin (either of V0, V1 and V2) when the load
current (ION = 100 µA) is passed to a pin of Y1 to Y240.
22
µPD16662
4. AC Characteristics 1 Display data transfer timing
(1) Master mode
(Unless otherwise specified, VCC1 = 4.5 to 5.5 V, VCC2 = 3.0 to 3.6 V. V0 = 0 V, V1 = 1.4 to 2.0 V, V2 = 2.8 to 4.0 V,
TA = −20 to +70 °C, frame frequency 70 Hz (fOSC = 181.44 kHz), output load: 100 pF)
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
STB clock cycle time
tCYC
87
16/fOSC
µs
STB high-level width
tCWH
43
8/fOSC
µs
STB low-level width
tCWL
43
8/fOSC
µs
STB rise time
tR
100
ns
STB fall time
tF
100
ns
STB -/FRM delay time
tPSF
20
µs
/FRM -STB delay time
tPFS
20
µs
Remark
tCYC
tCWL
tCWH
tF
tR
0.9 VCC1
STB (Input)
0.1 VCC1
tPSF
/FRM (Output)
tPFS
tPSF
tPFS
0.9 VCC1
0.1 VCC1
23
µPD16662
(2) Slave mode
(Unless otherwise specified, VCC1 = 4.5 to 5.5 V, VCC2 = 3.0 to 3.6 V. V0 = 0 V, V1 = 1.4 to 2.0 V, V2 = 2.8 to 4.0 V,
TA = −20 to +70 °C)
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
STB clock cycle time
tCYC
10
µs
STB High-level width
tCWH
4
µs
STB low-level width
tCWL
4
µs
STB rise time
tR
150
ns
STB fall time
tF
150
ns
/FRM setup time
tSFR
1
µs
/FRM hold time
tHFR
1
µs
Remark
tCYC
tCWL
tCWH
tF
tR
0.7 VCC1
STB (Input)
0.3 VCC1
tSFR
/FRM (Output)
24
tHFR
tSFR
tHFR
0.7 VCC1
0.3 VCC1
µPD16662
(3) Items common to the master and slaves
(Unless otherwise specified, VCC1 = 4.5 to 5.5 V, VCC2 = 3.0 to 3.6 V. V0 = 0 V, V1 = 1.4 to 2.0 V, V2 = 2.8 to 4.0 V, TA
= −20 to +70 °C)
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
Remark
Output delay time (L1, L2, /DOUT)
tDOUT1
50
100
ns
Without output load
Output delay time (Y1 to Y240)
tDOUT2
90
150
ns
Without output load
0.9 VCC1
STB (Output)
tDOUT1
tDOUT1
0.9 VCC1
L1, L2
/DOUT
tDOUT2
tDOUT2
0.9 V2
0.1 V2
Y1 - Y240
0.9 V2
0.1 V2
25
µPD16662
5. AC Characteristics 2 Graphic Access Timing
(Unless otherwise specified, VCC1 = 4.5 to 5.5 V, VCC2 = 3.0 to 3.6 V. V0 = 0 V, V1 = 1.4 to 2.0 V, V2 = 2.8 to 4.0 V,
TA = −20 to +70 °C, tr = tf = 5 ns)
Parameter
Symbol
MIN.
/OE, /WE recovery time
tRY
30
ns
Address setup time
tAS
10
ns
Address hold time
tAH
20
ns
RDY output delay time
tRYR
30
ns
•
RDY float time
tRYZ
30
ns
3
•
Wait state time
tRYW
35
ns
1
Ready state time (without contention)
tRYF1
60
100
ns
1
Ready state time (with contention)
tRYF2
650
1,200
ns
1
Data access time (Read cycle)
tACS
100
ns
2
Data float time (Read cycle)
tHZ
40
ns
3
/CS - /OE time (Read cycle)
tCSOE
10
ns
/OE - /CS time (Read cycle)
tOECS
20
ns
Write pulse width 1 (Write cycle 1)
tWP1
50
ns
1
Write pulse width 2 (Write cycle 2)
tWP2
50
ns
1
Data setup time (Write cycle 1, 2)
tDW
20
ns
Data hold time (Write cycle 1, 2)
tDH
20
ns
/CS - /WE time (Write cycle 1, 2)
tCSWE
10
ns
/WE - /CS time (Write cycle 1, 2)
tWECS
20
ns
Reset pulse width
tWRES
100
ns
RDY - /OE time
tRDOE
−
−
4
RDY - /WE time
tRDWE
−
−
4
•
Notes 1. Load circuit
TYP.
MAX.
Notes
CL = 15 pF
VCC2
1.8 kΩ
1.8 kΩ
•
Remark
2. Load circuit
VCC2
1.0 kΩ
Unit
60 pF
1.0 kΩ
100 pF
3. Load circuit
VCC2
1.8 kΩ
1.0 kΩ
5 pF
4. The display may be affected if the time from the rising of RDY to /OE or /WE is too long. It is recommended
that tRDOE and tRDWE be 1,000 ns MAX.
26
µPD16662
/OE, /WE recovery time
tRY
0.7 VCC2
/OE, /WE
•
0.3 VCC2
Read cycle
A16 - D0
0.7 VCC2
0.3 VCC2
/UBE
tAH
tAS
/CS
0.3 VCC2
tOECS
0.7 VCC2
/OE
0.3 VCC2
tRYR
RDY
D15 - D0
tOECS
tRDOE
tRYF
tRYZ
tRYW
0.9 VCC2
Hi-Z
0.1 VCC2
tACS
tHZ
OUT
Hi-Z
0.1 VCC2
0.9 VCC2
0.1 VCC2
27
µPD16662
•
Write cycle 1 (Display data write)
A16 - A0
0.7 VCC2
0.3 VCC2
/UBE
tAS
/CS
tAH
0.3 VCC2
tCSWE
tRDWE
0.7 VCC2
/WE
0.3 VCC2
tRYR
RDY
tWECS
tRYZ
tRYW
tRYF
0.9 VCC2
Hi-Z
0.1 VCC2
Hi-Z
0.1 VCC2
tWP
D15 - D0
0.7 VCC2
0.3 VCC2
IN
tDW
tDH
Write cycle 2 (Gray scale pallet data write)
A16 - A0
0.7 VCC2
0.3 VCC2
/UBE
tAS
/CS
tAH
0.3 VCC2
tWECS
tCSWE
0.7 VCC2
0.3 VCC2
/WE
tWP2
RDY
D15 - D0
Hi-Z
tDW
28
0.7 VCC2
0.3 VCC2
IN
tDH
µPD16662
Reset pulse width
/RESET
0.3 VCC2
tWRES
6. AC Characteristics 3 CR Oscillator
(VCC2 = 3.0 to 3.6 V, TA = −20 to +70 °C)
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
fOSC
160
190
220
kHz
External resistance: 62 kΩ
−
61.7
73.3
84.9
Hz
External resistance: 62 kΩ
Oscillation frequency
Frame frequency
Remark
Relation between oscillation frequency, frame frequency, and STB frequency
The relation between the oscillation frequency, frame frequency, and STB frequency is as follows:
1
Frame frequency =
x Oscillation frequency
162 x 2 x 8
1
STB frequency =
x Oscillation frequency
2x8
29
µPD16662
•
Package drawings
Standard TCP package (µPD16662N - 051)(1/3)
30
µPD16662
Standard TCP package (µPD16662N - 051)(2/3)
From PC
0.95
26.5
P0.2
0.24
0.35
0.35
0.3
0.15
0.3
0.15
0.3
0.15
16.25
16.25
0.6 ± 0.015
0.4 ± 0.015
Detail of output side test pad and alignment mark
From PC
Detail of cross mark
Right and Left
0.05 ± 0.02
0.6 ± 0.05
0.6 ± 0.05
0.05 ± 0.02
0.05 ± 0.02
0.6 ± 0.05
0.3 ± 0.05
0.05 ± 0.02
Center
TCP tape winding direction
Output leads
Unwinding Direction
Winding Direction
Cu pattern is on the backside of the tape
31
µPD16662
Standard TCP package (µPD16662N - 051) (3/3)
Pin connection
No.1
No.2
No.3
No.4
No.5
No.6
No.7
No.8
No.9
No.10
No.11
No.12
No.13
No.14
No.15
No.16
No.17
No.18
No.19
No.20
No.21
No.22
No.23
No.24
No.25
No.26
No.27
No.28
No.29
No.30
No.31
No.32
No.33
No.34
No.35
No.36
No.37
No.38
No.39
No.40
No.41
No.42
No.43
No.44
No.45
No.46
No.47
No.48
No.49
No.50
No.51
No.52
No.53
No.54
No.55
No.56
No.57
No.58
No.59
No.60
No.61
No.62
No.63
No.64
No.65
No.66
No.67
No.68
No.69
No.70
No.71
No.72
No.73
32
NC
V0
V1
V2
GND
VCC1
L1
L2
/DOUT
STB
/FRM
PULSE
GND
VCC2
MS
BMODE
TEST
/DOFF
RDY
/WE
/OE
/CS
/UBE
/RESET
/REFRH
PL1
PL0
DIR
GND
OSC2
OSC1
VCC2
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
GND
VCC2
GND
VCC1
V2
V1
V0
NC
DIE : FACE DOWN
NC
NC
NC
Y1
Y2
Y3
Y118
Y119
Y120
NC
NC
NC
NC
Y121
Y122
Y123
Y238
Y239
Y240
NC
NC
NC
No.1
No.2
No.3
No.4
No.5
No.6
No.121
No.122
No.123
No.124
No.125
No.126
No.127
No.128
No.129
No.130
No.245
No.246
No.247
No.248
No.249
No.250
µPD16662
[MEMO]
33
µPD16662
[MEMO]
34
µPD16662
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material.
All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry.
Each unused pin should be connected to V DD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
35
µPD16662
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC’s Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96. 5